From: Emil Renner Berthing <emil.renner.berthing@canonical.com>
To: Xingyu Wu <xingyu.wu@starfivetech.com>
Cc: linux-riscv@lists.infradead.org, devicetree@vger.kernel.org,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Philipp Zabel <p.zabel@pengutronix.de>,
Conor Dooley <conor@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
Hal Feng <hal.feng@starfivetech.com>,
William Qiu <william.qiu@starfivetech.com>,
linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org
Subject: Re: [RESEND PATCH v6 7/7] riscv: dts: starfive: jh7110: Add PLL clocks source in SYSCRG node
Date: Thu, 13 Jul 2023 15:24:46 +0200 [thread overview]
Message-ID: <CAJM55Z989XRDuzff14pFa+AFnL6xBsswONFfdFxKbwGy55TwoA@mail.gmail.com> (raw)
In-Reply-To: <20230704064610.292603-8-xingyu.wu@starfivetech.com>
On Tue, 4 Jul 2023 at 08:49, Xingyu Wu <xingyu.wu@starfivetech.com> wrote:
>
> Add PLL clocks input from PLL clocks driver in SYSCRG node.
>
> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> Signed-off-by: Xingyu Wu <xingyu.wu@starfivetech.com>
> ---
> arch/riscv/boot/dts/starfive/jh7110.dtsi | 8 ++++++--
> 1 file changed, 6 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> index 11dd4c9d64b0..cdfd036a0e6c 100644
> --- a/arch/riscv/boot/dts/starfive/jh7110.dtsi
> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
> @@ -452,12 +452,16 @@ syscrg: clock-controller@13020000 {
> <&gmac1_rgmii_rxin>,
> <&i2stx_bclk_ext>, <&i2stx_lrck_ext>,
> <&i2srx_bclk_ext>, <&i2srx_lrck_ext>,
> - <&tdm_ext>, <&mclk_ext>;
> + <&tdm_ext>, <&mclk_ext>,
> + <&pllclk JH7110_CLK_PLL0_OUT>,
> + <&pllclk JH7110_CLK_PLL1_OUT>,
> + <&pllclk JH7110_CLK_PLL2_OUT>;
Once these are updated to <&pll ?> or <&pllclk JH7110_PLLCLK_PLL?_OUT>
if you still want to keep the defines:
Reviewed-by: Emil Renner Berthing <emil.renner.berthing@canonical.com>
> clock-names = "osc", "gmac1_rmii_refin",
> "gmac1_rgmii_rxin",
> "i2stx_bclk_ext", "i2stx_lrck_ext",
> "i2srx_bclk_ext", "i2srx_lrck_ext",
> - "tdm_ext", "mclk_ext";
> + "tdm_ext", "mclk_ext",
> + "pll0_out", "pll1_out", "pll2_out";
> #clock-cells = <1>;
> #reset-cells = <1>;
> };
> --
> 2.25.1
>
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next prev parent reply other threads:[~2023-07-13 13:25 UTC|newest]
Thread overview: 28+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-04 6:46 [RESEND PATCH v6 0/7] Add PLL clocks driver and syscon for StarFive JH7110 SoC Xingyu Wu
2023-07-04 6:46 ` [RESEND PATCH v6 1/7] dt-bindings: clock: Add StarFive JH7110 PLL clock generator Xingyu Wu
2023-07-13 12:26 ` Emil Renner Berthing
2023-07-14 6:24 ` Xingyu Wu
2023-07-04 6:46 ` [RESEND PATCH v6 2/7] dt-bindings: soc: starfive: Add StarFive syscon module Xingyu Wu
2023-07-04 22:21 ` Conor Dooley
2023-07-05 6:29 ` Krzysztof Kozlowski
2023-07-13 12:31 ` Emil Renner Berthing
2023-07-04 6:46 ` [RESEND PATCH v6 3/7] dt-bindings: clock: jh7110-syscrg: Add PLL clock inputs Xingyu Wu
2023-07-04 22:23 ` Conor Dooley
2023-07-07 7:45 ` Xingyu Wu
2023-07-13 12:34 ` Emil Renner Berthing
2023-07-04 6:46 ` [RESEND PATCH v6 4/7] clk: starfive: Add StarFive JH7110 PLL clock driver Xingyu Wu
2023-07-13 12:37 ` Emil Renner Berthing
2023-07-04 6:46 ` [RESEND PATCH v6 5/7] clk: starfive: jh7110-sys: Add PLL clocks source from DTS Xingyu Wu
2023-07-04 22:25 ` Conor Dooley
2023-07-12 3:24 ` Hal Feng
2023-07-13 13:15 ` Emil Renner Berthing
2023-07-14 8:01 ` Xingyu Wu
2023-07-14 9:36 ` Emil Renner Berthing
2023-07-04 6:46 ` [RESEND PATCH v6 6/7] riscv: dts: starfive: jh7110: Add syscon nodes Xingyu Wu
2023-07-13 13:21 ` Emil Renner Berthing
2023-07-04 6:46 ` [RESEND PATCH v6 7/7] riscv: dts: starfive: jh7110: Add PLL clocks source in SYSCRG node Xingyu Wu
2023-07-13 13:24 ` Emil Renner Berthing [this message]
2023-07-04 22:29 ` [RESEND PATCH v6 0/7] Add PLL clocks driver and syscon for StarFive JH7110 SoC Conor Dooley
2023-07-12 16:09 ` Conor Dooley
2023-07-05 6:27 ` Krzysztof Kozlowski
2023-07-07 7:41 ` Xingyu Wu
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