From: Anup Patel <apatel@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Thomas Gleixner <tglx@linutronix.de>,
Marc Zyngier <maz@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Frank Rowand <frowand.list@gmail.com>,
Conor Dooley <conor+dt@kernel.org>
Cc: Anup Patel <apatel@ventanamicro.com>,
devicetree@vger.kernel.org,
Saravana Kannan <saravanak@google.com>,
Anup Patel <anup@brainfault.org>,
linux-kernel@vger.kernel.org, Atish Patra <atishp@atishpatra.org>,
linux-riscv@lists.infradead.org,
Andrew Jones <ajones@ventanamicro.com>
Subject: [PATCH v6 03/14] drivers: irqchip/riscv-intc: Mark all INTC nodes as initialized
Date: Wed, 19 Jul 2023 17:05:31 +0530 [thread overview]
Message-ID: <20230719113542.2293295-4-apatel@ventanamicro.com> (raw)
In-Reply-To: <20230719113542.2293295-1-apatel@ventanamicro.com>
The RISC-V INTC local interrupts are per-HART (or per-CPU) so
we create INTC IRQ domain only for the INTC node belonging to
the boot HART. This means only the boot HART INTC node will be
marked as initialized and other INTC nodes won't be marked which
results downstream interrupt controllers (such as IMSIC and APLIC
direct-mode) not being probed due to missing device suppliers.
To address this issue, we mark all INTC node for which we don't
create IRQ domain as initialized.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
drivers/irqchip/irq-riscv-intc.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/irqchip/irq-riscv-intc.c b/drivers/irqchip/irq-riscv-intc.c
index 65f4a2afb381..4e2704bc25fb 100644
--- a/drivers/irqchip/irq-riscv-intc.c
+++ b/drivers/irqchip/irq-riscv-intc.c
@@ -155,8 +155,16 @@ static int __init riscv_intc_init(struct device_node *node,
* for each INTC DT node. We only need to do INTC initialization
* for the INTC DT node belonging to boot CPU (or boot HART).
*/
- if (riscv_hartid_to_cpuid(hartid) != smp_processor_id())
+ if (riscv_hartid_to_cpuid(hartid) != smp_processor_id()) {
+ /*
+ * The INTC nodes of each CPU are suppliers for downstream
+ * interrupt controllers (such as IMSIC and APLIC direct-mode)
+ * so we should mark an INTC node as initialized if we are
+ * not creating IRQ domain for it.
+ */
+ fwnode_dev_initialized(of_fwnode_handle(node), true);
return 0;
+ }
return riscv_intc_init_common(of_node_to_fwnode(node));
}
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-07-19 11:36 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-19 11:35 [PATCH v6 00/14] Linux RISC-V AIA Support Anup Patel
2023-07-19 11:35 ` [PATCH v6 01/14] RISC-V: Add riscv_get_intc_hartid() function Anup Patel
2023-07-19 11:35 ` [PATCH v6 02/14] of: property: Add fw_devlink support for msi-parent Anup Patel
2023-07-19 22:25 ` Saravana Kannan
2023-07-20 5:21 ` Anup Patel
2023-07-19 22:37 ` Rob Herring
2023-07-20 11:55 ` Anup Patel
2023-07-19 11:35 ` Anup Patel [this message]
2023-07-19 22:14 ` [PATCH v6 03/14] drivers: irqchip/riscv-intc: Mark all INTC nodes as initialized Saravana Kannan
2023-07-20 5:21 ` Anup Patel
2023-07-19 11:35 ` [PATCH v6 04/14] irqchip/sifive-plic: Use platform driver probing for PLIC Anup Patel
2023-07-27 8:41 ` Sunil V L
2023-08-02 12:25 ` Anup Patel
2023-07-19 11:35 ` [PATCH v6 05/14] irqchip/riscv-intc: Add support for RISC-V AIA Anup Patel
2023-07-19 11:35 ` [PATCH v6 06/14] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Anup Patel
2023-07-19 11:35 ` [PATCH v6 07/14] irqchip: Add RISC-V incoming MSI controller early driver Anup Patel
2023-07-19 11:35 ` [PATCH v6 08/14] irqchip/riscv-imsic: Add support for platform MSI irqdomain Anup Patel
2023-07-19 11:35 ` [PATCH v6 09/14] irqchip/riscv-imsic: Add support for PCI " Anup Patel
2023-07-19 11:35 ` [PATCH v6 10/14] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Anup Patel
2023-07-19 11:35 ` [PATCH v6 11/14] irqchip: Add RISC-V advanced PLIC driver for direct-mode Anup Patel
2023-07-19 11:35 ` [PATCH v6 12/14] irqchip/riscv-aplic: Add support for MSI-mode Anup Patel
2023-07-19 11:35 ` [PATCH v6 13/14] RISC-V: Select APLIC and IMSIC drivers Anup Patel
2023-07-19 11:35 ` [PATCH v6 14/14] MAINTAINERS: Add entry for RISC-V AIA drivers Anup Patel
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20230719113542.2293295-4-apatel@ventanamicro.com \
--to=apatel@ventanamicro.com \
--cc=ajones@ventanamicro.com \
--cc=anup@brainfault.org \
--cc=atishp@atishpatra.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=frowand.list@gmail.com \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=maz@kernel.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=robh+dt@kernel.org \
--cc=saravanak@google.com \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).