From: Mayuresh Chitale <mchitale@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>, Anup Patel <anup@brainfault.org>
Cc: Mayuresh Chitale <mchitale@ventanamicro.com>,
Andrew Jones <ajones@ventanamicro.com>,
Atish Patra <atishp@atishpatra.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Albert Ou <aou@eecs.berkeley.edu>,
linux-riscv@lists.infradead.org, kvm-riscv@lists.infradead.org
Subject: [PATCH v1 1/6] RISC-V: Detect Smstateen extension
Date: Wed, 19 Jul 2023 21:33:11 +0530 [thread overview]
Message-ID: <20230719160316.4048022-2-mchitale@ventanamicro.com> (raw)
In-Reply-To: <20230719160316.4048022-1-mchitale@ventanamicro.com>
Extend the ISA string parsing to detect the Smstateen extension
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
---
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/kernel/cpu.c | 1 +
arch/riscv/kernel/cpufeature.c | 2 ++
3 files changed, 4 insertions(+)
diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index f041bfa7f6a0..fad1fd1fcd05 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -53,6 +53,7 @@
#define RISCV_ISA_EXT_ZICSR 40
#define RISCV_ISA_EXT_ZIFENCEI 41
#define RISCV_ISA_EXT_ZIHPM 42
+#define RISCV_ISA_EXT_SMSTATEEN 43
#define RISCV_ISA_EXT_MAX 64
#define RISCV_ISA_EXT_NAME_LEN_MAX 32
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index a2fc952318e9..fb0df651bc48 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -217,6 +217,7 @@ static struct riscv_isa_ext_data isa_ext_arr[] = {
__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
__RISCV_ISA_EXT_DATA(zbs, RISCV_ISA_EXT_ZBS),
__RISCV_ISA_EXT_DATA(smaia, RISCV_ISA_EXT_SMAIA),
+ __RISCV_ISA_EXT_DATA(smstateen, RISCV_ISA_EXT_SMSTATEEN),
__RISCV_ISA_EXT_DATA(ssaia, RISCV_ISA_EXT_SSAIA),
__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index bdcf460ea53d..41c3aefcc53f 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -301,6 +301,8 @@ void __init riscv_fill_hwcap(void)
} else {
/* sorted alphabetically */
SET_ISA_EXT_MAP("smaia", RISCV_ISA_EXT_SMAIA);
+ SET_ISA_EXT_MAP("smstateen",
+ RISCV_ISA_EXT_SMSTATEEN);
SET_ISA_EXT_MAP("ssaia", RISCV_ISA_EXT_SSAIA);
SET_ISA_EXT_MAP("sscofpmf", RISCV_ISA_EXT_SSCOFPMF);
SET_ISA_EXT_MAP("sstc", RISCV_ISA_EXT_SSTC);
--
2.34.1
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next prev parent reply other threads:[~2023-07-19 16:04 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-19 16:03 [PATCH v1 0/6] Risc-V Kvm Smstateen Mayuresh Chitale
2023-07-19 16:03 ` Mayuresh Chitale [this message]
2023-07-19 16:27 ` [PATCH v1 1/6] RISC-V: Detect Smstateen extension Conor Dooley
2023-07-21 7:49 ` mchitale
2023-07-19 16:03 ` [PATCH v1 2/6] RISC-V: KVM: Add kvm_vcpu_config Mayuresh Chitale
2023-07-19 16:03 ` [PATCH v1 3/6] RISC-V: KVM: Enable Smstateen accesses Mayuresh Chitale
2023-07-19 16:03 ` [PATCH v1 4/6] RISCV: KVM: Add senvcfg context save/restore Mayuresh Chitale
2023-07-19 16:03 ` [PATCH v1 5/6] RISCV: KVM: Add sstateen0 " Mayuresh Chitale
2023-07-19 16:03 ` [PATCH v1 6/6] RISCV: KVM: Add sstateen0 to ONE_REG Mayuresh Chitale
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