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From: Conor Dooley <conor.dooley@microchip.com>
To: Eric Lin <eric.lin@sifive.com>
Cc: Conor Dooley <conor@kernel.org>, <robh+dt@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>, <conor+dt@kernel.org>,
	<devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <zong.li@sifive.com>,
	<greentime.hu@sifive.com>, <vincent.chen@sifive.com>
Subject: Re: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller
Date: Fri, 28 Jul 2023 12:06:35 +0100	[thread overview]
Message-ID: <20230728-corrosive-crown-54dfd6dd3919@wendy> (raw)
In-Reply-To: <CAPqJEFrObCSEXx+qTOp_JY3m5Ano59x=U4fFCBJ32ufLUx+6PA@mail.gmail.com>


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On Fri, Jul 28, 2023 at 04:24:08PM +0800, Eric Lin wrote:
> On Fri, Jul 28, 2023 at 3:06 PM Conor Dooley <conor.dooley@microchip.com> wrote:
> > On Thu, Jul 20, 2023 at 06:10:51PM +0100, Conor Dooley wrote:
> > > On Thu, Jul 20, 2023 at 09:51:19PM +0800, Eric Lin wrote:

> > > > +description:
> > > > +  The SiFive Private L2 Cache Controller is per core and
> > > > +  communicates with both the upstream L1 caches and
> > > > +  downstream L3 cache or memory, enabling a high-performance
> > > > +  cache subsystem.
> > > > +
> > > > +allOf:
> > > > +  - $ref: /schemas/cache-controller.yaml#
> > > > +
> > >
> > > I'm pretty sure that I pointed out last time around that you need to add
> > > something like in the ccache driver:
> > >
> > > select:
> > >   properties:
> > >     compatible:
> > >       contains:
> > >         enum:
> > >           - sifive,ccache0
> > >           - sifive,fu540-c000-ccache
> > >           - sifive,fu740-c000-ccache
> > >
> > > otherwise this binding will be used for anything containing "cache" in
> > > the dt-binding.
> > > For this binding, I think that the following is sufficient:
> > >
> > > select:
> > >   properties:
> > >     compatible:
> > >       contains:
> > >           const: sifive,pl2cache1
> > >
> 
> Sorry, I misunderstood your meaning.
> To be honest, I'm not quite familiar with the usage of the select property.
> When should we use the select property?
> May I ask, is there a document to detail introduce each property and
> its usage like the device-tree spec?
> I think it would be very helpful for beginners writing correct
> dt-binding and it can save much reviewers time.

You need this select because otherwise this binding will match against
every other user of "cache" in the tree. It's explained here:
https://docs.kernel.org/devicetree/bindings/writing-schema.html

Thanks,
Conor.

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  reply	other threads:[~2023-07-28 11:07 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-07-20 13:51 [PATCH v2 0/3] Add SiFive Private L2 cache and PMU driver Eric Lin
2023-07-20 13:51 ` [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller Eric Lin
2023-07-20 14:47   ` Rob Herring
2023-07-21 10:21     ` Eric Lin
2023-07-20 17:10   ` Conor Dooley
2023-07-28  7:05     ` Conor Dooley
2023-07-28  8:24       ` Eric Lin
2023-07-28 11:06         ` Conor Dooley [this message]
2023-09-05 15:07     ` Eric Lin
2023-07-21  8:34   ` Krzysztof Kozlowski
2023-07-28  6:01     ` Eric Lin
2023-07-28  6:46       ` Conor Dooley
2023-07-28  7:20         ` Eric Lin
2023-07-28  6:58       ` Krzysztof Kozlowski
2023-07-28  9:04         ` Eric Lin
2023-07-28  9:39           ` Krzysztof Kozlowski
2023-08-01 10:59             ` Eric Lin
2023-07-20 13:51 ` [PATCH v2 2/3] soc: sifive: Add SiFive private L2 cache driver Eric Lin
2023-07-28  7:15   ` Conor Dooley
2023-07-20 13:51 ` [PATCH v2 3/3] soc: sifive: Add SiFive private L2 cache PMU driver Eric Lin

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