From: Eric Lin <eric.lin@sifive.com>
To: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
conor+dt@kernel.org, devicetree@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
zong.li@sifive.com, greentime.hu@sifive.com,
vincent.chen@sifive.com
Subject: Re: [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller
Date: Fri, 28 Jul 2023 14:01:28 +0800 [thread overview]
Message-ID: <CAPqJEFr5h+5+F4TdNuRMaWsrmeedbfGgbgd9wh8sUUQsj2Pw-A@mail.gmail.com> (raw)
In-Reply-To: <cbf0a8fd-3479-1684-fe90-81f2159804ef@linaro.org>
Hi Krzysztof,
On Fri, Jul 21, 2023 at 4:35 PM Krzysztof Kozlowski
<krzysztof.kozlowski@linaro.org> wrote:
>
> On 20/07/2023 15:51, Eric Lin wrote:
> > This add YAML DT binding documentation for SiFive Private L2
> > cache controller
> >
> > Signed-off-by: Eric Lin <eric.lin@sifive.com>
> > Reviewed-by: Zong Li <zong.li@sifive.com>
> > Reviewed-by: Nick Hu <nick.hu@sifive.com>
>
>
> ...
>
> > +properties:
> > + compatible:
> > + items:
> > + - const: sifive,pl2cache1
>
> I still have doubts that it is not used in any SoC. This is what you
> said last time: "is not part of any SoC."
> If not part of any SoC, then where is it? Why are you adding it to the
> kernel?
>
Sorry for the late reply. I didn't describe it clearly last time.
Currently, we have two hardware versions of pl2cache: pl2cache0 and pl2cache1.
The pl2cache0 is used in unmatched board SoC. The pl2cache1 is
utilized in our internal FPGA platform for evaluation; it's our core
IP.
>
>
> > + - const: cache
> > +
> > + cache-block-size: true
> > + cache-level: true
> > + cache-sets: true
> > + cache-size: true
> > + cache-unified: true
> > +
> > + reg:
> > + maxItems: 1
> > +
> > + next-level-cache: true
> > +
> > +required:
> > + - compatible
> > + - cache-block-size
> > + - cache-level
> > + - cache-sets
> > + - cache-size
> > + - cache-unified
> > + - reg
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + cache-controller@10104000 {
> > + compatible = "sifive,pl2cache1","cache";
>
> Missing space.
OK, I'll fix it in the next version.
>
> > + cache-block-size = <64>;
> > + cache-level = <2>;
> > + cache-sets = <512>;
> > + cache-size = <262144>;
> > + cache-unified;
> > + reg = <0x10104000 0x4000>;
>
> reg is after compatible.
OK, I'll fix it in the next version.
Thanks for your review.
Best regards,
Eric Lin
>
> > + next-level-cache = <&L4>;
> > + };
>
> Best regards,
> Krzysztof
>
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next prev parent reply other threads:[~2023-07-28 6:02 UTC|newest]
Thread overview: 20+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-20 13:51 [PATCH v2 0/3] Add SiFive Private L2 cache and PMU driver Eric Lin
2023-07-20 13:51 ` [PATCH v2 1/3] dt-bindings: riscv: sifive: Add SiFive Private L2 cache controller Eric Lin
2023-07-20 14:47 ` Rob Herring
2023-07-21 10:21 ` Eric Lin
2023-07-20 17:10 ` Conor Dooley
2023-07-28 7:05 ` Conor Dooley
2023-07-28 8:24 ` Eric Lin
2023-07-28 11:06 ` Conor Dooley
2023-09-05 15:07 ` Eric Lin
2023-07-21 8:34 ` Krzysztof Kozlowski
2023-07-28 6:01 ` Eric Lin [this message]
2023-07-28 6:46 ` Conor Dooley
2023-07-28 7:20 ` Eric Lin
2023-07-28 6:58 ` Krzysztof Kozlowski
2023-07-28 9:04 ` Eric Lin
2023-07-28 9:39 ` Krzysztof Kozlowski
2023-08-01 10:59 ` Eric Lin
2023-07-20 13:51 ` [PATCH v2 2/3] soc: sifive: Add SiFive private L2 cache driver Eric Lin
2023-07-28 7:15 ` Conor Dooley
2023-07-20 13:51 ` [PATCH v2 3/3] soc: sifive: Add SiFive private L2 cache PMU driver Eric Lin
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