From: Anup Patel <apatel@ventanamicro.com>
To: Paolo Bonzini <pbonzini@redhat.com>,
Atish Patra <atishp@atishpatra.org>,
Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Conor Dooley <conor@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Shuah Khan <shuah@kernel.org>
Cc: Andrew Jones <ajones@ventanamicro.com>,
Mayuresh Chitale <mchitale@ventanamicro.com>,
devicetree@vger.kernel.org, kvm@vger.kernel.org,
kvm-riscv@lists.infradead.org, linux-riscv@lists.infradead.org,
linux-kernel@vger.kernel.org, linux-kselftest@vger.kernel.org,
Anup Patel <apatel@ventanamicro.com>
Subject: [PATCH v3 0/6] KVM RISC-V Conditional Operations
Date: Tue, 3 Oct 2023 09:22:20 +0530 [thread overview]
Message-ID: <20231003035226.1945725-1-apatel@ventanamicro.com> (raw)
This series extends KVM RISC-V to allow Guest/VM discover and use
conditional operations related ISA extensions (namely XVentanaCondOps
and Zicond).
To try these patches, use KVMTOOL from riscv_zbx_zicntr_smstateen_condops_v1
branch at: https://github.com/avpatel/kvmtool.git
These patches are based upon the latest riscv_kvm_queue and can also be
found in the riscv_kvm_condops_v3 branch at:
https://github.com/avpatel/linux.git
Changes since v2:
- Dropped patch1, patch2, and patch5 since these patches don't meet
the requirements of patch acceptance policy.
Changes since v1:
- Rebased the series on riscv_kvm_queue
- Split PATCH1 and PATCH2 of v1 series into two patches
- Added separate test configs for XVentanaCondOps and Zicond in PATCH7
of v1 series.
Anup Patel (6):
dt-bindings: riscv: Add Zicond extension entry
RISC-V: Detect Zicond from ISA string
RISC-V: KVM: Allow Zicond extension for Guest/VM
KVM: riscv: selftests: Add senvcfg register to get-reg-list test
KVM: riscv: selftests: Add smstateen registers to get-reg-list test
KVM: riscv: selftests: Add condops extensions to get-reg-list test
.../devicetree/bindings/riscv/extensions.yaml | 6 +++
arch/riscv/include/asm/hwcap.h | 1 +
arch/riscv/include/uapi/asm/kvm.h | 1 +
arch/riscv/kernel/cpufeature.c | 1 +
arch/riscv/kvm/vcpu_onereg.c | 2 +
.../selftests/kvm/riscv/get-reg-list.c | 54 +++++++++++++++++++
6 files changed, 65 insertions(+)
--
2.34.1
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next reply other threads:[~2023-10-03 3:53 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-03 3:52 Anup Patel [this message]
2023-10-03 3:52 ` [PATCH v3 1/6] dt-bindings: riscv: Add Zicond extension entry Anup Patel
2023-10-03 3:52 ` [PATCH v3 2/6] RISC-V: Detect Zicond from ISA string Anup Patel
2023-10-04 14:07 ` Palmer Dabbelt
2023-10-05 5:50 ` Anup Patel
2023-10-03 3:52 ` [PATCH v3 3/6] RISC-V: KVM: Allow Zicond extension for Guest/VM Anup Patel
2023-10-03 3:52 ` [PATCH v3 4/6] KVM: riscv: selftests: Add senvcfg register to get-reg-list test Anup Patel
2023-10-03 3:52 ` [PATCH v3 5/6] KVM: riscv: selftests: Add smstateen registers " Anup Patel
2023-10-03 3:52 ` [PATCH v3 6/6] KVM: riscv: selftests: Add condops extensions " Anup Patel
2023-10-05 6:05 ` [PATCH v3 0/6] KVM RISC-V Conditional Operations Anup Patel
2023-10-12 14:04 ` Anup Patel
2023-11-12 0:55 ` patchwork-bot+linux-riscv
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