From: Anup Patel <anup@brainfault.org>
To: Palmer Dabbelt <palmer@dabbelt.com>
Cc: apatel@ventanamicro.com, pbonzini@redhat.com,
atishp@atishpatra.org, Paul Walmsley <paul.walmsley@sifive.com>,
Conor Dooley <conor@kernel.org>,
robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org,
shuah@kernel.org, ajones@ventanamicro.com,
mchitale@ventanamicro.com, devicetree@vger.kernel.org,
kvm@vger.kernel.org, kvm-riscv@lists.infradead.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
linux-kselftest@vger.kernel.org,
Conor Dooley <conor.dooley@microchip.com>
Subject: Re: [PATCH v3 2/6] RISC-V: Detect Zicond from ISA string
Date: Thu, 5 Oct 2023 11:20:48 +0530 [thread overview]
Message-ID: <CAAhSdy2CxWw9ny7vdBoEzsXkm_J882NGKTDQ7BfykrjuB1QR+w@mail.gmail.com> (raw)
In-Reply-To: <mhng-4ec1093a-4542-429e-a9f0-8a976cff9ac4@palmer-ri-x1c9>
On Wed, Oct 4, 2023 at 7:37 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
> On Mon, 02 Oct 2023 20:52:22 PDT (-0700), apatel@ventanamicro.com wrote:
> > The RISC-V integer conditional (Zicond) operation extension defines
> > standard conditional arithmetic and conditional-select/move operations
> > which are inspired from the XVentanaCondOps extension. In fact, QEMU
> > RISC-V also has support for emulating Zicond extension.
> >
> > Let us detect Zicond extension from ISA string available through
> > DT or ACPI.
> >
> > Signed-off-by: Anup Patel <apatel@ventanamicro.com>
> > Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > ---
> > arch/riscv/include/asm/hwcap.h | 1 +
> > arch/riscv/kernel/cpufeature.c | 1 +
> > 2 files changed, 2 insertions(+)
> >
> > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> > index 0f520f7d058a..6fc51c1b34cf 100644
> > --- a/arch/riscv/include/asm/hwcap.h
> > +++ b/arch/riscv/include/asm/hwcap.h
> > @@ -59,6 +59,7 @@
> > #define RISCV_ISA_EXT_ZIFENCEI 41
> > #define RISCV_ISA_EXT_ZIHPM 42
> > #define RISCV_ISA_EXT_SMSTATEEN 43
> > +#define RISCV_ISA_EXT_ZICOND 44
> >
> > #define RISCV_ISA_EXT_MAX 64
> >
> > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> > index 3755a8c2a9de..e3803822ab5a 100644
> > --- a/arch/riscv/kernel/cpufeature.c
> > +++ b/arch/riscv/kernel/cpufeature.c
> > @@ -167,6 +167,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = {
> > __RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
> > __RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
> > __RISCV_ISA_EXT_DATA(zicntr, RISCV_ISA_EXT_ZICNTR),
> > + __RISCV_ISA_EXT_DATA(zicond, RISCV_ISA_EXT_ZICOND),
> > __RISCV_ISA_EXT_DATA(zicsr, RISCV_ISA_EXT_ZICSR),
> > __RISCV_ISA_EXT_DATA(zifencei, RISCV_ISA_EXT_ZIFENCEI),
> > __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
>
> Acked-by: Palmer Dabbelt <palmer@rivosinc.com>
>
> Can we do a shared tag, though? These will conflict.
Thanks Palmer.
I will provide a shared tag based on 6.6-rc5 sometime
next week. I hope this is okay for you.
Regards,
Anup
>
> --
> kvm-riscv mailing list
> kvm-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/kvm-riscv
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next prev parent reply other threads:[~2023-10-05 5:51 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-03 3:52 [PATCH v3 0/6] KVM RISC-V Conditional Operations Anup Patel
2023-10-03 3:52 ` [PATCH v3 1/6] dt-bindings: riscv: Add Zicond extension entry Anup Patel
2023-10-03 3:52 ` [PATCH v3 2/6] RISC-V: Detect Zicond from ISA string Anup Patel
2023-10-04 14:07 ` Palmer Dabbelt
2023-10-05 5:50 ` Anup Patel [this message]
2023-10-03 3:52 ` [PATCH v3 3/6] RISC-V: KVM: Allow Zicond extension for Guest/VM Anup Patel
2023-10-03 3:52 ` [PATCH v3 4/6] KVM: riscv: selftests: Add senvcfg register to get-reg-list test Anup Patel
2023-10-03 3:52 ` [PATCH v3 5/6] KVM: riscv: selftests: Add smstateen registers " Anup Patel
2023-10-03 3:52 ` [PATCH v3 6/6] KVM: riscv: selftests: Add condops extensions " Anup Patel
2023-10-05 6:05 ` [PATCH v3 0/6] KVM RISC-V Conditional Operations Anup Patel
2023-10-12 14:04 ` Anup Patel
2023-11-12 0:55 ` patchwork-bot+linux-riscv
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