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From: "Clément Léger" <cleger@rivosinc.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: "Clément Léger" <cleger@rivosinc.com>,
	"Atish Patra" <atishp@rivosinc.com>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Evan Green" <evan@rivosinc.com>,
	"Björn Topel" <bjorn@rivosinc.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	"Ron Minnich" <rminnich@gmail.com>,
	"Daniel Maslowski" <cyrevolt@googlemail.com>,
	"Conor Dooley" <conor@kernel.org>
Subject: [PATCH v2 3/8] riscv: report perf event for misaligned fault
Date: Wed,  4 Oct 2023 17:14:00 +0200	[thread overview]
Message-ID: <20231004151405.521596-4-cleger@rivosinc.com> (raw)
In-Reply-To: <20231004151405.521596-1-cleger@rivosinc.com>

Add missing calls to account for misaligned fault event using
perf_sw_event().

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 arch/riscv/kernel/traps_misaligned.c | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
index 9daed7d756ae..804f6c5e0e44 100644
--- a/arch/riscv/kernel/traps_misaligned.c
+++ b/arch/riscv/kernel/traps_misaligned.c
@@ -6,6 +6,7 @@
 #include <linux/init.h>
 #include <linux/mm.h>
 #include <linux/module.h>
+#include <linux/perf_event.h>
 #include <linux/irq.h>
 #include <linux/stringify.h>
 
@@ -294,6 +295,8 @@ int handle_misaligned_load(struct pt_regs *regs)
 	unsigned long addr = regs->badaddr;
 	int i, fp = 0, shift = 0, len = 0;
 
+	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
+
 	if (get_insn(regs, epc, &insn))
 		return -1;
 
@@ -382,6 +385,8 @@ int handle_misaligned_store(struct pt_regs *regs)
 	unsigned long addr = regs->badaddr;
 	int i, len = 0;
 
+	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
+
 	if (get_insn(regs, epc, &insn))
 		return -1;
 
-- 
2.42.0


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  parent reply	other threads:[~2023-10-04 15:14 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-04 15:13 [PATCH v2 0/8] Add support to handle misaligned accesses in S-mode Clément Léger
2023-10-04 15:13 ` [PATCH v2 1/8] riscv: remove unused functions in traps_misaligned.c Clément Léger
2023-10-04 16:51   ` Björn Töpel
2023-10-09 13:02     ` Clément Léger
2023-10-04 15:13 ` [PATCH v2 2/8] riscv: add support for misaligned trap handling in S-mode Clément Léger
2023-10-04 17:00   ` Björn Töpel
2023-10-09 13:02     ` Clément Léger
2023-10-04 15:14 ` Clément Léger [this message]
2023-10-04 17:02   ` [PATCH v2 3/8] riscv: report perf event for misaligned fault Björn Töpel
2023-10-04 15:14 ` [PATCH v2 4/8] riscv: add floating point insn support to misaligned access emulation Clément Léger
2023-10-04 15:14 ` [PATCH v2 5/8] riscv: add support for sysctl unaligned_enabled control Clément Léger
2023-10-04 17:14   ` Björn Töpel
2023-10-04 15:14 ` [PATCH v2 6/8] riscv: annotate check_unaligned_access_boot_cpu() with __init Clément Léger
2023-10-04 16:14   ` Evan Green
2023-10-04 15:14 ` [PATCH v2 7/8] riscv: report misaligned accesses emulation to hwprobe Clément Léger
2023-10-04 16:14   ` Evan Green
2023-10-09 13:07     ` Clément Léger
2023-10-04 15:14 ` [PATCH v2 8/8] riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN Clément Léger
2023-10-04 17:19   ` Björn Töpel
2023-11-02 20:20 ` [PATCH v2 0/8] Add support to handle misaligned accesses in S-mode patchwork-bot+linux-riscv

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