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From: "Clément Léger" <cleger@rivosinc.com>
To: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>
Cc: "Clément Léger" <cleger@rivosinc.com>,
	"Atish Patra" <atishp@rivosinc.com>,
	"Andrew Jones" <ajones@ventanamicro.com>,
	"Evan Green" <evan@rivosinc.com>,
	"Björn Topel" <bjorn@rivosinc.com>,
	linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org,
	"Ron Minnich" <rminnich@gmail.com>,
	"Daniel Maslowski" <cyrevolt@googlemail.com>,
	"Conor Dooley" <conor@kernel.org>
Subject: [PATCH v2 5/8] riscv: add support for sysctl unaligned_enabled control
Date: Wed,  4 Oct 2023 17:14:02 +0200	[thread overview]
Message-ID: <20231004151405.521596-6-cleger@rivosinc.com> (raw)
In-Reply-To: <20231004151405.521596-1-cleger@rivosinc.com>

This sysctl tuning option allows the user to disable misaligned access
handling globally on the system. This will also be used by misaligned
detection code to temporarily disable misaligned access handling.

Signed-off-by: Clément Léger <cleger@rivosinc.com>
---
 arch/riscv/Kconfig                   | 1 +
 arch/riscv/kernel/traps_misaligned.c | 9 +++++++++
 2 files changed, 10 insertions(+)

diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 6e167358a897..1313f83bb0cb 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -638,6 +638,7 @@ config THREAD_SIZE_ORDER
 
 config RISCV_MISALIGNED
 	bool "Support misaligned load/store traps for kernel and userspace"
+	select SYSCTL_ARCH_UNALIGN_ALLOW
 	default y
 	help
 	  Say Y here if you want the kernel to embed support for misaligned
diff --git a/arch/riscv/kernel/traps_misaligned.c b/arch/riscv/kernel/traps_misaligned.c
index 041fd2dbd955..b5fb1ff078e3 100644
--- a/arch/riscv/kernel/traps_misaligned.c
+++ b/arch/riscv/kernel/traps_misaligned.c
@@ -396,6 +396,9 @@ union reg_data {
 	u64 data_u64;
 };
 
+/* sysctl hooks */
+int unaligned_enabled __read_mostly = 1;	/* Enabled by default */
+
 int handle_misaligned_load(struct pt_regs *regs)
 {
 	union reg_data val;
@@ -406,6 +409,9 @@ int handle_misaligned_load(struct pt_regs *regs)
 
 	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
 
+	if (!unaligned_enabled)
+		return -1;
+
 	if (get_insn(regs, epc, &insn))
 		return -1;
 
@@ -502,6 +508,9 @@ int handle_misaligned_store(struct pt_regs *regs)
 
 	perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS, 1, regs, addr);
 
+	if (!unaligned_enabled)
+		return -1;
+
 	if (get_insn(regs, epc, &insn))
 		return -1;
 
-- 
2.42.0


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  parent reply	other threads:[~2023-10-04 15:14 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-10-04 15:13 [PATCH v2 0/8] Add support to handle misaligned accesses in S-mode Clément Léger
2023-10-04 15:13 ` [PATCH v2 1/8] riscv: remove unused functions in traps_misaligned.c Clément Léger
2023-10-04 16:51   ` Björn Töpel
2023-10-09 13:02     ` Clément Léger
2023-10-04 15:13 ` [PATCH v2 2/8] riscv: add support for misaligned trap handling in S-mode Clément Léger
2023-10-04 17:00   ` Björn Töpel
2023-10-09 13:02     ` Clément Léger
2023-10-04 15:14 ` [PATCH v2 3/8] riscv: report perf event for misaligned fault Clément Léger
2023-10-04 17:02   ` Björn Töpel
2023-10-04 15:14 ` [PATCH v2 4/8] riscv: add floating point insn support to misaligned access emulation Clément Léger
2023-10-04 15:14 ` Clément Léger [this message]
2023-10-04 17:14   ` [PATCH v2 5/8] riscv: add support for sysctl unaligned_enabled control Björn Töpel
2023-10-04 15:14 ` [PATCH v2 6/8] riscv: annotate check_unaligned_access_boot_cpu() with __init Clément Léger
2023-10-04 16:14   ` Evan Green
2023-10-04 15:14 ` [PATCH v2 7/8] riscv: report misaligned accesses emulation to hwprobe Clément Léger
2023-10-04 16:14   ` Evan Green
2023-10-09 13:07     ` Clément Léger
2023-10-04 15:14 ` [PATCH v2 8/8] riscv: add support for PR_SET_UNALIGN and PR_GET_UNALIGN Clément Léger
2023-10-04 17:19   ` Björn Töpel
2023-11-02 20:20 ` [PATCH v2 0/8] Add support to handle misaligned accesses in S-mode patchwork-bot+linux-riscv

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