From: Conor Dooley <conor.dooley@microchip.com>
To: <linux-riscv@lists.indradead.org>
Cc: Emil Renner Berthing <kernel@esmil.dk>,
Geert Uytterhoeven <geert+renesas@glider.be>,
conor.dooley@microchip.com, Guo Ren <guoren@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
linux-riscv@lists.infradead.org,
Samuel Holland <samuel@sholland.org>,
Chen Wang <unicorn_wang@outlook.com>,
Magnus Damm <magnus.damm@gmail.com>,
Jernej Skrabec <jernej.skrabec@gmail.com>,
Chen-Yu Tsai <wens@csie.org>,
linux-sunxi@lists.linux.dev, devicetree@vger.kernel.org,
Conor Dooley <conor+dt@kernel.org>,
Albert Ou <aou@eecs.berkeley.edu>,
Rob Herring <robh+dt@kernel.org>,
Paul Walmsley <paul.walmsley@sifive.com>,
Jisheng Zhang <jszhang@kernel.org>,
Daire McNamara <daire.mcnamara@microchip.com>,
conor@kernel.org, linux-renesas-soc@vger.kernel.org,
Palmer Dabbelt <palmer@dabbelt.com>, Fu Wei <wefu@redhat.com>
Subject: [PATCH v3 2/6] riscv: dts: sifive: convert isa detection to new properties
Date: Mon, 9 Oct 2023 10:37:46 +0100 [thread overview]
Message-ID: <20231009-economic-shorty-16422a511728@wendy> (raw)
In-Reply-To: <20231009-approve-verbalize-ce9324858e76@wendy>
Convert the fu540 and fu740 devicetrees to use the new properties
"riscv,isa-base" & "riscv,isa-extensions".
For compatibility with other projects, "riscv,isa" remains.
Reviewed-by: Samuel Holland <samuel.holland@sifive.com>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
arch/riscv/boot/dts/sifive/fu540-c000.dtsi | 15 +++++++++++++++
arch/riscv/boot/dts/sifive/fu740-c000.dtsi | 15 +++++++++++++++
2 files changed, 30 insertions(+)
diff --git a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
index 24bba83bec77..156330a9bbf3 100644
--- a/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu540-c000.dtsi
@@ -30,6 +30,9 @@ cpu0: cpu@0 {
i-cache-size = <16384>;
reg = <0>;
riscv,isa = "rv64imac";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
+ "zihpm";
status = "disabled";
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -53,6 +56,9 @@ cpu1: cpu@1 {
mmu-type = "riscv,sv39";
reg = <1>;
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
tlb-split;
next-level-cache = <&l2cache>;
cpu1_intc: interrupt-controller {
@@ -77,6 +83,9 @@ cpu2: cpu@2 {
mmu-type = "riscv,sv39";
reg = <2>;
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
tlb-split;
next-level-cache = <&l2cache>;
cpu2_intc: interrupt-controller {
@@ -101,6 +110,9 @@ cpu3: cpu@3 {
mmu-type = "riscv,sv39";
reg = <3>;
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
tlb-split;
next-level-cache = <&l2cache>;
cpu3_intc: interrupt-controller {
@@ -125,6 +137,9 @@ cpu4: cpu@4 {
mmu-type = "riscv,sv39";
reg = <4>;
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
tlb-split;
next-level-cache = <&l2cache>;
cpu4_intc: interrupt-controller {
diff --git a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
index 5235fd1c9cb6..6150f3397bff 100644
--- a/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
+++ b/arch/riscv/boot/dts/sifive/fu740-c000.dtsi
@@ -31,6 +31,9 @@ cpu0: cpu@0 {
next-level-cache = <&ccache>;
reg = <0x0>;
riscv,isa = "rv64imac";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "c", "zicntr", "zicsr", "zifencei",
+ "zihpm";
status = "disabled";
cpu0_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -55,6 +58,9 @@ cpu1: cpu@1 {
next-level-cache = <&ccache>;
reg = <0x1>;
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
tlb-split;
cpu1_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -79,6 +85,9 @@ cpu2: cpu@2 {
next-level-cache = <&ccache>;
reg = <0x2>;
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
tlb-split;
cpu2_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -103,6 +112,9 @@ cpu3: cpu@3 {
next-level-cache = <&ccache>;
reg = <0x3>;
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
tlb-split;
cpu3_intc: interrupt-controller {
#interrupt-cells = <1>;
@@ -127,6 +139,9 @@ cpu4: cpu@4 {
next-level-cache = <&ccache>;
reg = <0x4>;
riscv,isa = "rv64imafdc";
+ riscv,isa-base = "rv64i";
+ riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr",
+ "zifencei", "zihpm";
tlb-split;
cpu4_intc: interrupt-controller {
#interrupt-cells = <1>;
--
2.40.1
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next prev parent reply other threads:[~2023-10-09 9:40 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-09 9:37 [PATCH v3 0/6] riscv,isa-extensions additions Conor Dooley
2023-10-09 9:37 ` [PATCH v3 1/6] riscv: dts: microchip: convert isa detection to new properties Conor Dooley
2023-10-09 9:37 ` Conor Dooley [this message]
2023-10-09 9:37 ` [PATCH v3 3/6] riscv: dts: starfive: " Conor Dooley
2023-10-09 9:37 ` [PATCH v3 4/6] riscv: dts: renesas: " Conor Dooley
2023-10-09 12:15 ` Geert Uytterhoeven
2023-10-09 16:16 ` Conor Dooley
2023-10-16 6:09 ` Yu-Chien Peter Lin
2023-10-16 7:17 ` Geert Uytterhoeven
2023-10-09 9:37 ` [PATCH v3 5/6] riscv: dts: allwinner: " Conor Dooley
2023-10-13 19:22 ` Jernej Škrabec
2023-10-09 9:37 ` [PATCH v3 6/6] riscv: dts: thead: " Conor Dooley
2023-10-15 12:22 ` (subset) [PATCH v3 0/6] riscv,isa-extensions additions Conor Dooley
2023-10-16 7:23 ` Geert Uytterhoeven
2023-10-16 8:09 ` Conor Dooley
2023-11-12 0:55 ` patchwork-bot+linux-riscv
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