* [PATCH] dt-bindings: riscv: cpus: Clarify mmu-type interpretation
@ 2023-12-27 17:57 Samuel Holland
2023-12-27 23:39 ` Conor Dooley
2024-01-11 14:50 ` patchwork-bot+linux-riscv
0 siblings, 2 replies; 3+ messages in thread
From: Samuel Holland @ 2023-12-27 17:57 UTC (permalink / raw)
To: linux-riscv
Cc: Samuel Holland, Albert Ou, Conor Dooley, Krzysztof Kozlowski,
Palmer Dabbelt, Paul Walmsley, Rob Herring, devicetree,
linux-kernel
The current description implies that only a single address translation
mode is available to the operating system. However, some implementations
support multiple address translation modes, and the operating system is
free to choose between them.
Per the RISC-V privileged specification, Sv48 implementations must also
implement Sv39, and likewise Sv57 implies support for Sv48. This means
it is possible to describe all supported address translation modes using
a single value, by naming the largest supported mode. This appears to
have been the intended usage of the property, so note it explicitly.
Fixes: 4fd669a8c487 ("dt-bindings: riscv: convert cpu binding to json-schema")
Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
---
Documentation/devicetree/bindings/riscv/cpus.yaml | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index f392e367d673..f166c729c482 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -62,8 +62,8 @@ properties:
mmu-type:
description:
- Identifies the MMU address translation mode used on this
- hart. These values originate from the RISC-V Privileged
+ Identifies the largest MMU address translation mode supported by
+ this hart. These values originate from the RISC-V Privileged
Specification document, available from
https://riscv.org/specifications/
$ref: /schemas/types.yaml#/definitions/string
--
2.42.0
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^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] dt-bindings: riscv: cpus: Clarify mmu-type interpretation
2023-12-27 17:57 [PATCH] dt-bindings: riscv: cpus: Clarify mmu-type interpretation Samuel Holland
@ 2023-12-27 23:39 ` Conor Dooley
2024-01-11 14:50 ` patchwork-bot+linux-riscv
1 sibling, 0 replies; 3+ messages in thread
From: Conor Dooley @ 2023-12-27 23:39 UTC (permalink / raw)
To: Samuel Holland
Cc: linux-riscv, Albert Ou, Krzysztof Kozlowski, Palmer Dabbelt,
Paul Walmsley, Rob Herring, devicetree, linux-kernel
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On Wed, Dec 27, 2023 at 09:57:38AM -0800, Samuel Holland wrote:
> The current description implies that only a single address translation
> mode is available to the operating system. However, some implementations
> support multiple address translation modes, and the operating system is
> free to choose between them.
>
> Per the RISC-V privileged specification, Sv48 implementations must also
> implement Sv39, and likewise Sv57 implies support for Sv48. This means
> it is possible to describe all supported address translation modes using
> a single value, by naming the largest supported mode. This appears to
> have been the intended usage of the property, so note it explicitly.
>
> Fixes: 4fd669a8c487 ("dt-bindings: riscv: convert cpu binding to json-schema")
> Signed-off-by: Samuel Holland <samuel.holland@sifive.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
Cheers,
Conor.
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] dt-bindings: riscv: cpus: Clarify mmu-type interpretation
2023-12-27 17:57 [PATCH] dt-bindings: riscv: cpus: Clarify mmu-type interpretation Samuel Holland
2023-12-27 23:39 ` Conor Dooley
@ 2024-01-11 14:50 ` patchwork-bot+linux-riscv
1 sibling, 0 replies; 3+ messages in thread
From: patchwork-bot+linux-riscv @ 2024-01-11 14:50 UTC (permalink / raw)
To: Samuel Holland
Cc: linux-riscv, aou, conor, krzysztof.kozlowski+dt, palmer,
paul.walmsley, robh+dt, devicetree, linux-kernel
Hello:
This patch was applied to riscv/linux.git (for-next)
by Palmer Dabbelt <palmer@rivosinc.com>:
On Wed, 27 Dec 2023 09:57:38 -0800 you wrote:
> The current description implies that only a single address translation
> mode is available to the operating system. However, some implementations
> support multiple address translation modes, and the operating system is
> free to choose between them.
>
> Per the RISC-V privileged specification, Sv48 implementations must also
> implement Sv39, and likewise Sv57 implies support for Sv48. This means
> it is possible to describe all supported address translation modes using
> a single value, by naming the largest supported mode. This appears to
> have been the intended usage of the property, so note it explicitly.
>
> [...]
Here is the summary with links:
- dt-bindings: riscv: cpus: Clarify mmu-type interpretation
https://git.kernel.org/riscv/c/b4070c2a242e
You are awesome, thank you!
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2023-12-27 17:57 [PATCH] dt-bindings: riscv: cpus: Clarify mmu-type interpretation Samuel Holland
2023-12-27 23:39 ` Conor Dooley
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