From: Yu Chien Peter Lin <peterlin@andestech.com>
To: <acme@kernel.org>, <adrian.hunter@intel.com>,
<ajones@ventanamicro.com>, <alexander.shishkin@linux.intel.com>,
<andre.przywara@arm.com>, <anup@brainfault.org>,
<aou@eecs.berkeley.edu>, <atishp@atishpatra.org>,
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<conor@kernel.org>, <devicetree@vger.kernel.org>,
<dminus@andestech.com>, <evan@rivosinc.com>,
<geert+renesas@glider.be>, <guoren@kernel.org>, <heiko@sntech.de>,
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<namhyung@kernel.org>, <palmer@dabbelt.com>,
<paul.walmsley@sifive.com>, <peterlin@andestech.com>,
<peterz@infradead.org>, <prabhakar.mahadev-lad.rj@bp.renesas.com>,
<rdunlap@infradead.org>, <robh+dt@kernel.org>,
<samuel@sholland.org>, <sunilvl@ventanamicro.com>,
<tglx@linutronix.de>, <tim609@andestech.com>, <uwu@icenowy.me>,
<wens@csie.org>, <will@kernel.org>, <ycliang@andestech.com>,
<inochiama@outlook.com>, <chao.wei@sophgo.com>,
<unicorn_wang@outlook.com>, <wefu@redhat.com>
Subject: [PATCH v7 10/16] dt-bindings: riscv: Add Andes PMU extension description
Date: Wed, 10 Jan 2024 15:39:11 +0800 [thread overview]
Message-ID: <20240110073917.2398826-11-peterlin@andestech.com> (raw)
In-Reply-To: <20240110073917.2398826-1-peterlin@andestech.com>
Document the ISA string for Andes Technology performance monitor
extension which provides counter overflow interrupt and mode
filtering mechanisms.
Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
---
Changes v2 -> v3:
- New patch
Changes v3 -> v4:
- Include Conor's Acked-by
Changes v4 -> v5:
- Include Prabhakar's Reviewed-by
Changes v5 -> v6:
- No change
Changes v6 -> v7:
- No change
---
Documentation/devicetree/bindings/riscv/extensions.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/riscv/extensions.yaml b/Documentation/devicetree/bindings/riscv/extensions.yaml
index ee0747f29d6d..ecc7a105e7fc 100644
--- a/Documentation/devicetree/bindings/riscv/extensions.yaml
+++ b/Documentation/devicetree/bindings/riscv/extensions.yaml
@@ -477,6 +477,13 @@ properties:
latency, as ratified in commit 56ed795 ("Update
riscv-crypto-spec-vector.adoc") of riscv-crypto.
+ - const: xandespmu
+ description:
+ The Andes Technology performance monitor extension for counter overflow
+ and privilege mode filtering. For more details, see Counter Related
+ Registers in the AX45MP datasheet.
+ https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
+
- const: xtheadpmu
description:
The T-Head performance monitor extension for counter overflow, as ratified
--
2.34.1
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next prev parent reply other threads:[~2024-01-10 7:41 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-10 7:39 [PATCH v7 00/16] Support Andes PMU extension Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 01/16] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 02/16] irqchip/riscv-intc: Allow large non-standard interrupt number Yu Chien Peter Lin
2024-01-10 15:11 ` Anup Patel
2024-01-12 23:44 ` Atish Patra
2024-01-10 7:39 ` [PATCH v7 03/16] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Yu Chien Peter Lin
2024-01-10 15:12 ` Anup Patel
2024-01-12 23:43 ` Atish Patra
2024-01-10 7:39 ` [PATCH v7 04/16] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin
2024-01-12 23:50 ` Atish Patra
2024-01-13 0:19 ` Conor Dooley
2024-01-13 0:31 ` Atish Patra
2024-01-10 7:39 ` [PATCH v7 05/16] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 06/16] perf: RISC-V: Eliminate redundant interrupt enable/disable operations Yu Chien Peter Lin
2024-01-12 20:17 ` Atish Patra
2024-01-10 7:39 ` [PATCH v7 07/16] RISC-V: Move T-Head PMU to CPU feature alternative framework Yu Chien Peter Lin
2024-01-16 20:55 ` Atish Patra
2024-01-17 0:16 ` Conor Dooley
2024-01-17 8:58 ` Atish Patra
2024-01-17 9:17 ` Conor Dooley
2024-01-17 22:32 ` Atish Patra
2024-01-17 23:02 ` Conor Dooley
2024-01-17 23:10 ` Palmer Dabbelt
2024-01-22 8:48 ` Yu-Chien Peter Lin
2024-01-17 3:35 ` Anup Patel
2024-01-17 9:01 ` Atish Patra
2024-01-10 7:39 ` [PATCH v7 08/16] perf: RISC-V: Introduce Andes PMU for perf event sampling Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 09/16] dt-bindings: riscv: Add T-Head PMU extension description Yu Chien Peter Lin
2024-01-10 7:39 ` Yu Chien Peter Lin [this message]
2024-01-10 7:39 ` [PATCH v7 11/16] riscv: dts: allwinner: Add T-Head PMU extension for sun20i-d1s Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 12/16] riscv: dts: sophgo: Add T-Head PMU extension for cv1800b Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 13/16] riscv: dts: sophgo: Add T-Head PMU extension for sg2042 Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 14/16] riscv: dts: thead: Add T-Head PMU extension for th1520 Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 15/16] riscv: dts: renesas: Add Andes PMU extension for r9a07g043f Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 16/16] riscv: andes: Support specifying symbolic firmware and hardware raw events Yu Chien Peter Lin
2024-01-13 0:04 ` Atish Patra
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