From: Conor Dooley <conor@kernel.org>
To: Atish Patra <atishp@atishpatra.org>
Cc: mark.rutland@arm.com, irogers@google.com, heiko@sntech.de,
geert+renesas@glider.be, alexander.shishkin@linux.intel.com,
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linux-riscv@lists.infradead.org, will@kernel.org,
linux-renesas-soc@vger.kernel.org, tim609@andestech.com,
Yu Chien Peter Lin <peterlin@andestech.com>,
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palmer@dabbelt.com, jolsa@kernel.org, unicorn_wang@outlook.com,
wefu@redhat.com
Subject: Re: [PATCH v7 04/16] dt-bindings: riscv: Add Andes interrupt controller compatible string
Date: Sat, 13 Jan 2024 00:19:02 +0000 [thread overview]
Message-ID: <20240113-sensuous-scraggly-dee35f3e213f@spud> (raw)
In-Reply-To: <CAOnJCUJ0fN5=+b4jDx+NPqUwgwGKuBNYt7d86dXYNyjzUYFAWQ@mail.gmail.com>
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On Fri, Jan 12, 2024 at 03:50:15PM -0800, Atish Patra wrote:
> On Tue, Jan 9, 2024 at 11:40 PM Yu Chien Peter Lin
> <peterlin@andestech.com> wrote:
> >
> > Add "andestech,cpu-intc" compatible string to indicate that
> > Andes specific local interrupt is supported on the core,
> > e.g. AX45MP cores have 3 types of non-standard local interrupt
> > which can be handled in supervisor mode:
> >
>
> PATCH1 in this series renames everything from ANDESTECH to ANDES to be
> consistent.
> Here you are adding DT binding with "andestech". Is there any
> fundamental difference between these two to demand
> this change ?
This one is the vendor prefix and the company has been assigned
"andestech" and they're not getting a second one. The rename of the
variables is a bit gratuitous tbf.
Cheers,
Conor.
> FYI: I don't mind either way as I don't have skin in the game. Just
> something I noticed while reviewing the series.
>
> > - Slave port ECC error interrupt
> > - Bus write transaction error interrupt
> > - Performance monitor overflow interrupt
> >
> > These interrupts are enabled/disabled via a custom register
> > SLIE instead of the standard interrupt enable register SIE.
> >
> > Signed-off-by: Yu Chien Peter Lin <peterlin@andestech.com>
> > Acked-by: Conor Dooley <conor.dooley@microchip.com>
> > Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> > ---
> > Changes v1 -> v2:
> > - New patch
> > Changes v2 -> v3:
> > - Updated commit message
> > - Fixed possible compatibles for Andes INTC
> > Changes v3 -> v4:
> > - Add const entry instead of enum (Suggested by Conor)
> > Changes v4 -> v5:
> > - Include Conor's Acked-by
> > - Include Prabhakar's Reviewed-by
> > Changes v5 -> v6:
> > - No change
> > Changes v6 -> v7:
> > - No change
> > ---
> > Documentation/devicetree/bindings/riscv/cpus.yaml | 6 +++++-
> > 1 file changed, 5 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > index 23646b684ea2..33c2b620a59f 100644
> > --- a/Documentation/devicetree/bindings/riscv/cpus.yaml
> > +++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
> > @@ -101,7 +101,11 @@ properties:
> > const: 1
> >
> > compatible:
> > - const: riscv,cpu-intc
> > + oneOf:
> > + - items:
> > + - const: andestech,cpu-intc
> > + - const: riscv,cpu-intc
> > + - const: riscv,cpu-intc
> >
> > interrupt-controller: true
> >
> > --
> > 2.34.1
> >
>
>
> --
> Regards,
> Atish
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next prev parent reply other threads:[~2024-01-13 0:19 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-01-10 7:39 [PATCH v7 00/16] Support Andes PMU extension Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 01/16] riscv: errata: Rename defines for Andes Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 02/16] irqchip/riscv-intc: Allow large non-standard interrupt number Yu Chien Peter Lin
2024-01-10 15:11 ` Anup Patel
2024-01-12 23:44 ` Atish Patra
2024-01-10 7:39 ` [PATCH v7 03/16] irqchip/riscv-intc: Introduce Andes hart-level interrupt controller Yu Chien Peter Lin
2024-01-10 15:12 ` Anup Patel
2024-01-12 23:43 ` Atish Patra
2024-01-10 7:39 ` [PATCH v7 04/16] dt-bindings: riscv: Add Andes interrupt controller compatible string Yu Chien Peter Lin
2024-01-12 23:50 ` Atish Patra
2024-01-13 0:19 ` Conor Dooley [this message]
2024-01-13 0:31 ` Atish Patra
2024-01-10 7:39 ` [PATCH v7 05/16] riscv: dts: renesas: r9a07g043f: Update compatible string to use Andes INTC Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 06/16] perf: RISC-V: Eliminate redundant interrupt enable/disable operations Yu Chien Peter Lin
2024-01-12 20:17 ` Atish Patra
2024-01-10 7:39 ` [PATCH v7 07/16] RISC-V: Move T-Head PMU to CPU feature alternative framework Yu Chien Peter Lin
2024-01-16 20:55 ` Atish Patra
2024-01-17 0:16 ` Conor Dooley
2024-01-17 8:58 ` Atish Patra
2024-01-17 9:17 ` Conor Dooley
2024-01-17 22:32 ` Atish Patra
2024-01-17 23:02 ` Conor Dooley
2024-01-17 23:10 ` Palmer Dabbelt
2024-01-22 8:48 ` Yu-Chien Peter Lin
2024-01-17 3:35 ` Anup Patel
2024-01-17 9:01 ` Atish Patra
2024-01-10 7:39 ` [PATCH v7 08/16] perf: RISC-V: Introduce Andes PMU for perf event sampling Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 09/16] dt-bindings: riscv: Add T-Head PMU extension description Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 10/16] dt-bindings: riscv: Add Andes " Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 11/16] riscv: dts: allwinner: Add T-Head PMU extension for sun20i-d1s Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 12/16] riscv: dts: sophgo: Add T-Head PMU extension for cv1800b Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 13/16] riscv: dts: sophgo: Add T-Head PMU extension for sg2042 Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 14/16] riscv: dts: thead: Add T-Head PMU extension for th1520 Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 15/16] riscv: dts: renesas: Add Andes PMU extension for r9a07g043f Yu Chien Peter Lin
2024-01-10 7:39 ` [PATCH v7 16/16] riscv: andes: Support specifying symbolic firmware and hardware raw events Yu Chien Peter Lin
2024-01-13 0:04 ` Atish Patra
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