From: Anup Patel <apatel@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Thomas Gleixner <tglx@linutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Frank Rowand <frowand.list@gmail.com>,
Conor Dooley <conor+dt@kernel.org>
Cc: "Anup Patel" <apatel@ventanamicro.com>,
devicetree@vger.kernel.org,
"Conor Dooley" <conor.dooley@microchip.com>,
"Saravana Kannan" <saravanak@google.com>,
"Marc Zyngier" <maz@kernel.org>,
"Anup Patel" <anup@brainfault.org>,
linux-kernel@vger.kernel.org, "Björn Töpel" <bjorn@kernel.org>,
"Atish Patra" <atishp@atishpatra.org>,
linux-riscv@lists.infradead.org,
linux-arm-kernel@lists.infradead.org,
"Andrew Jones" <ajones@ventanamicro.com>
Subject: [PATCH v14 14/18] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC
Date: Thu, 22 Feb 2024 15:10:02 +0530 [thread overview]
Message-ID: <20240222094006.1030709-15-apatel@ventanamicro.com> (raw)
In-Reply-To: <20240222094006.1030709-1-apatel@ventanamicro.com>
Add DT bindings document for RISC-V advanced platform level interrupt
controller (APLIC) defined by the RISC-V advanced interrupt architecture
(AIA) specification.
Signed-off-by: Anup Patel <apatel@ventanamicro.com>
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
---
.../interrupt-controller/riscv,aplic.yaml | 172 ++++++++++++++++++
1 file changed, 172 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
diff --git a/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
new file mode 100644
index 000000000000..190a6499c932
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/riscv,aplic.yaml
@@ -0,0 +1,172 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interrupt-controller/riscv,aplic.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: RISC-V Advanced Platform Level Interrupt Controller (APLIC)
+
+maintainers:
+ - Anup Patel <anup@brainfault.org>
+
+description:
+ The RISC-V advanced interrupt architecture (AIA) defines an advanced
+ platform level interrupt controller (APLIC) for handling wired interrupts
+ in a RISC-V platform. The RISC-V AIA specification can be found at
+ https://github.com/riscv/riscv-aia.
+
+ The RISC-V APLIC is implemented as hierarchical APLIC domains where all
+ interrupt sources connect to the root APLIC domain and a parent APLIC
+ domain can delegate interrupt sources to it's child APLIC domains. There
+ is one device tree node for each APLIC domain.
+
+allOf:
+ - $ref: /schemas/interrupt-controller.yaml#
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - qemu,aplic
+ - const: riscv,aplic
+
+ reg:
+ maxItems: 1
+
+ interrupt-controller: true
+
+ "#interrupt-cells":
+ const: 2
+
+ interrupts-extended:
+ minItems: 1
+ maxItems: 16384
+ description:
+ Given APLIC domain directly injects external interrupts to a set of
+ RISC-V HARTS (or CPUs). Each node pointed to should be a riscv,cpu-intc
+ node, which has a CPU node (i.e. RISC-V HART) as parent.
+
+ msi-parent:
+ description:
+ Given APLIC domain forwards wired interrupts as MSIs to a AIA incoming
+ message signaled interrupt controller (IMSIC). If both "msi-parent" and
+ "interrupts-extended" properties are present then it means the APLIC
+ domain supports both MSI mode and Direct mode in HW. In this case, the
+ APLIC driver has to choose between MSI mode or Direct mode.
+
+ riscv,num-sources:
+ $ref: /schemas/types.yaml#/definitions/uint32
+ minimum: 1
+ maximum: 1023
+ description:
+ Specifies the number of wired interrupt sources supported by this
+ APLIC domain.
+
+ riscv,children:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ minItems: 1
+ maxItems: 1024
+ items:
+ maxItems: 1
+ description:
+ A list of child APLIC domains for the given APLIC domain. Each child
+ APLIC domain is assigned a child index in increasing order, with the
+ first child APLIC domain assigned child index 0. The APLIC domain child
+ index is used by firmware to delegate interrupts from the given APLIC
+ domain to a particular child APLIC domain.
+
+ riscv,delegation:
+ $ref: /schemas/types.yaml#/definitions/phandle-array
+ minItems: 1
+ maxItems: 1024
+ items:
+ items:
+ - description: child APLIC domain phandle
+ - description: first interrupt number of the parent APLIC domain (inclusive)
+ - description: last interrupt number of the parent APLIC domain (inclusive)
+ description:
+ A interrupt delegation list where each entry is a triple consisting
+ of child APLIC domain phandle, first interrupt number of the parent
+ APLIC domain, and last interrupt number of the parent APLIC domain.
+ Firmware must configure interrupt delegation registers based on
+ interrupt delegation list.
+
+dependencies:
+ riscv,delegation: [ "riscv,children" ]
+
+required:
+ - compatible
+ - reg
+ - interrupt-controller
+ - "#interrupt-cells"
+ - riscv,num-sources
+
+anyOf:
+ - required:
+ - interrupts-extended
+ - required:
+ - msi-parent
+
+unevaluatedProperties: false
+
+examples:
+ - |
+ // Example 1 (APLIC domains directly injecting interrupt to HARTs):
+
+ interrupt-controller@c000000 {
+ compatible = "qemu,aplic", "riscv,aplic";
+ interrupts-extended = <&cpu1_intc 11>,
+ <&cpu2_intc 11>,
+ <&cpu3_intc 11>,
+ <&cpu4_intc 11>;
+ reg = <0xc000000 0x4080>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ riscv,num-sources = <63>;
+ riscv,children = <&aplic1>, <&aplic2>;
+ riscv,delegation = <&aplic1 1 63>;
+ };
+
+ aplic1: interrupt-controller@d000000 {
+ compatible = "qemu,aplic", "riscv,aplic";
+ interrupts-extended = <&cpu1_intc 9>,
+ <&cpu2_intc 9>;
+ reg = <0xd000000 0x4080>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ riscv,num-sources = <63>;
+ };
+
+ aplic2: interrupt-controller@e000000 {
+ compatible = "qemu,aplic", "riscv,aplic";
+ interrupts-extended = <&cpu3_intc 9>,
+ <&cpu4_intc 9>;
+ reg = <0xe000000 0x4080>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ riscv,num-sources = <63>;
+ };
+
+ - |
+ // Example 2 (APLIC domains forwarding interrupts as MSIs):
+
+ interrupt-controller@c000000 {
+ compatible = "qemu,aplic", "riscv,aplic";
+ msi-parent = <&imsic_mlevel>;
+ reg = <0xc000000 0x4000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ riscv,num-sources = <63>;
+ riscv,children = <&aplic3>;
+ riscv,delegation = <&aplic3 1 63>;
+ };
+
+ aplic3: interrupt-controller@d000000 {
+ compatible = "qemu,aplic", "riscv,aplic";
+ msi-parent = <&imsic_slevel>;
+ reg = <0xd000000 0x4000>;
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ riscv,num-sources = <63>;
+ };
+...
--
2.34.1
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next prev parent reply other threads:[~2024-02-22 9:43 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-02-22 9:39 [PATCH v14 00/18] Linux RISC-V AIA Support Anup Patel
2024-02-22 9:39 ` [PATCH v14 01/18] irqchip/sifive-plic: Convert PLIC driver into a platform driver Anup Patel
2024-04-03 8:29 ` Lad, Prabhakar
2024-04-03 14:16 ` Anup Patel
2024-04-03 15:49 ` Lad, Prabhakar
2024-04-03 16:28 ` Samuel Holland
2024-04-03 18:10 ` Lad, Prabhakar
2024-04-03 16:42 ` Anup Patel
2024-04-03 17:19 ` Anup Patel
2024-02-22 9:39 ` [PATCH v14 02/18] irqchip/sifive-plic: Use dev_xyz() in-place of pr_xyz() Anup Patel
2024-02-22 9:39 ` [PATCH v14 03/18] irqchip/sifive-plic: Use devm_xyz() for managed allocation Anup Patel
2024-02-22 9:39 ` [PATCH v14 04/18] irqchip/sifive-plic: Use riscv_get_intc_hwnode() to get parent fwnode Anup Patel
2024-02-22 9:39 ` [PATCH v14 05/18] irqchip/sifive-plic: Cleanup PLIC contexts upon irqdomain creation failure Anup Patel
2024-02-22 9:39 ` [PATCH v14 06/18] irqchip/sifive-plic: Parse number of irqs and contexts early in plic_probe Anup Patel
2024-02-22 9:39 ` [PATCH v14 07/18] irqchip/sifive-plic: Improve locking safety by using irqsave/irqrestore Anup Patel
2024-02-22 9:39 ` [PATCH v14 08/18] irqchip/riscv-intc: Add support for RISC-V AIA Anup Patel
2024-02-22 9:39 ` [PATCH v14 09/18] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Anup Patel
2024-02-22 9:39 ` [PATCH v14 10/18] genirq/matrix: Dynamic bitmap allocation Anup Patel
2024-02-22 9:39 ` [PATCH v14 11/18] irqchip: Add RISC-V incoming MSI controller early driver Anup Patel
2024-02-22 13:13 ` Björn Töpel
2024-02-22 13:42 ` Anup Patel
2024-02-22 14:15 ` Björn Töpel
2024-02-23 8:28 ` Thomas Gleixner
2024-02-23 9:52 ` Anup Patel
2024-02-22 9:40 ` [PATCH v14 12/18] irqchip/riscv-imsic: Add device MSI domain support for platform devices Anup Patel
2024-02-22 13:15 ` Björn Töpel
2024-02-22 13:44 ` Anup Patel
2024-02-22 9:40 ` [PATCH v14 13/18] irqchip/riscv-imsic: Add device MSI domain support for PCI devices Anup Patel
2024-02-22 13:14 ` Björn Töpel
2024-02-22 13:30 ` Anup Patel
2024-02-22 14:05 ` Björn Töpel
2024-02-22 9:40 ` Anup Patel [this message]
2024-02-22 9:40 ` [PATCH v14 15/18] irqchip: Add RISC-V advanced PLIC driver for direct-mode Anup Patel
2024-02-22 9:40 ` [PATCH v14 16/18] irqchip/riscv-aplic: Add support for MSI-mode Anup Patel
2024-02-22 9:40 ` [PATCH v14 17/18] RISC-V: Select APLIC and IMSIC drivers Anup Patel
2024-02-22 9:40 ` [PATCH v14 18/18] MAINTAINERS: Add entry for RISC-V AIA drivers Anup Patel
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