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From: Anup Patel <apatel@ventanamicro.com>
To: Palmer Dabbelt <palmer@dabbelt.com>,
	Paul Walmsley <paul.walmsley@sifive.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
	Frank Rowand <frowand.list@gmail.com>,
	Conor Dooley <conor+dt@kernel.org>
Cc: "Anup Patel" <apatel@ventanamicro.com>,
	devicetree@vger.kernel.org,
	"Saravana Kannan" <saravanak@google.com>,
	"Marc Zyngier" <maz@kernel.org>,
	"Anup Patel" <anup@brainfault.org>,
	linux-kernel@vger.kernel.org, "Björn Töpel" <bjorn@kernel.org>,
	"Atish Patra" <atishp@atishpatra.org>,
	linux-riscv@lists.infradead.org,
	linux-arm-kernel@lists.infradead.org,
	"Andrew Jones" <ajones@ventanamicro.com>
Subject: [PATCH v14 03/18] irqchip/sifive-plic: Use devm_xyz() for managed allocation
Date: Thu, 22 Feb 2024 15:09:51 +0530	[thread overview]
Message-ID: <20240222094006.1030709-4-apatel@ventanamicro.com> (raw)
In-Reply-To: <20240222094006.1030709-1-apatel@ventanamicro.com>

Use devm_xyz() for allocations and mappings managed by the
Linux device driver framework.

Signed-off-by: Anup Patel <apatel@ventanamicro.com>
---
 drivers/irqchip/irq-sifive-plic.c | 49 ++++++++++---------------------
 1 file changed, 16 insertions(+), 33 deletions(-)

diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
index 3d7a61c35572..558ae63795d9 100644
--- a/drivers/irqchip/irq-sifive-plic.c
+++ b/drivers/irqchip/irq-sifive-plic.c
@@ -435,39 +435,30 @@ static int plic_probe(struct platform_device *pdev)
 			plic_quirks = (unsigned long)id->data;
 	}
 
-	priv = kzalloc(sizeof(*priv), GFP_KERNEL);
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
 	if (!priv)
 		return -ENOMEM;
 
 	priv->dev = dev;
 	priv->plic_quirks = plic_quirks;
 
-	priv->regs = of_iomap(to_of_node(dev->fwnode), 0);
-	if (WARN_ON(!priv->regs)) {
-		error = -EIO;
-		goto out_free_priv;
-	}
+	priv->regs = devm_platform_ioremap_resource(pdev, 0);
+	if (WARN_ON(!priv->regs))
+		return -EIO;
 
-	error = -EINVAL;
 	of_property_read_u32(to_of_node(dev->fwnode), "riscv,ndev", &nr_irqs);
 	if (WARN_ON(!nr_irqs))
-		goto out_iounmap;
+		return -EINVAL;
 
 	priv->nr_irqs = nr_irqs;
 
-	priv->prio_save = bitmap_alloc(nr_irqs, GFP_KERNEL);
+	priv->prio_save = devm_bitmap_zalloc(dev, nr_irqs, GFP_KERNEL);
 	if (!priv->prio_save)
-		goto out_free_priority_reg;
+		return -ENOMEM;
 
 	nr_contexts = of_irq_count(to_of_node(dev->fwnode));
 	if (WARN_ON(!nr_contexts))
-		goto out_free_priority_reg;
-
-	error = -ENOMEM;
-	priv->irqdomain = irq_domain_add_linear(to_of_node(dev->fwnode), nr_irqs + 1,
-						&plic_irqdomain_ops, priv);
-	if (WARN_ON(!priv->irqdomain))
-		goto out_free_priority_reg;
+		return -EINVAL;
 
 	for (i = 0; i < nr_contexts; i++) {
 		struct of_phandle_args parent;
@@ -538,10 +529,10 @@ static int plic_probe(struct platform_device *pdev)
 			i * CONTEXT_ENABLE_SIZE;
 		handler->priv = priv;
 
-		handler->enable_save =  kcalloc(DIV_ROUND_UP(nr_irqs, 32),
-						sizeof(*handler->enable_save), GFP_KERNEL);
+		handler->enable_save = devm_kcalloc(dev, DIV_ROUND_UP(nr_irqs, 32),
+						    sizeof(*handler->enable_save), GFP_KERNEL);
 		if (!handler->enable_save)
-			goto out_free_enable_reg;
+			return -ENOMEM;
 done:
 		for (hwirq = 1; hwirq <= nr_irqs; hwirq++) {
 			plic_toggle(handler, hwirq, 0);
@@ -551,6 +542,11 @@ static int plic_probe(struct platform_device *pdev)
 		nr_handlers++;
 	}
 
+	priv->irqdomain = irq_domain_add_linear(to_of_node(dev->fwnode), nr_irqs + 1,
+						&plic_irqdomain_ops, priv);
+	if (WARN_ON(!priv->irqdomain))
+		return -ENOMEM;
+
 	/*
 	 * We can have multiple PLIC instances so setup cpuhp state
 	 * and register syscore operations only once after context
@@ -577,19 +573,6 @@ static int plic_probe(struct platform_device *pdev)
 	dev_info(dev, "mapped %d interrupts with %d handlers for %d contexts.\n",
 		 nr_irqs, nr_handlers, nr_contexts);
 	return 0;
-
-out_free_enable_reg:
-	for_each_cpu(cpu, cpu_present_mask) {
-		handler = per_cpu_ptr(&plic_handlers, cpu);
-		kfree(handler->enable_save);
-	}
-out_free_priority_reg:
-	kfree(priv->prio_save);
-out_iounmap:
-	iounmap(priv->regs);
-out_free_priv:
-	kfree(priv);
-	return error;
 }
 
 static struct platform_driver plic_driver = {
-- 
2.34.1


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  parent reply	other threads:[~2024-02-22  9:40 UTC|newest]

Thread overview: 36+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-02-22  9:39 [PATCH v14 00/18] Linux RISC-V AIA Support Anup Patel
2024-02-22  9:39 ` [PATCH v14 01/18] irqchip/sifive-plic: Convert PLIC driver into a platform driver Anup Patel
2024-04-03  8:29   ` Lad, Prabhakar
2024-04-03 14:16     ` Anup Patel
2024-04-03 15:49       ` Lad, Prabhakar
2024-04-03 16:28         ` Samuel Holland
2024-04-03 18:10           ` Lad, Prabhakar
2024-04-03 16:42         ` Anup Patel
2024-04-03 17:19         ` Anup Patel
2024-02-22  9:39 ` [PATCH v14 02/18] irqchip/sifive-plic: Use dev_xyz() in-place of pr_xyz() Anup Patel
2024-02-22  9:39 ` Anup Patel [this message]
2024-02-22  9:39 ` [PATCH v14 04/18] irqchip/sifive-plic: Use riscv_get_intc_hwnode() to get parent fwnode Anup Patel
2024-02-22  9:39 ` [PATCH v14 05/18] irqchip/sifive-plic: Cleanup PLIC contexts upon irqdomain creation failure Anup Patel
2024-02-22  9:39 ` [PATCH v14 06/18] irqchip/sifive-plic: Parse number of irqs and contexts early in plic_probe Anup Patel
2024-02-22  9:39 ` [PATCH v14 07/18] irqchip/sifive-plic: Improve locking safety by using irqsave/irqrestore Anup Patel
2024-02-22  9:39 ` [PATCH v14 08/18] irqchip/riscv-intc: Add support for RISC-V AIA Anup Patel
2024-02-22  9:39 ` [PATCH v14 09/18] dt-bindings: interrupt-controller: Add RISC-V incoming MSI controller Anup Patel
2024-02-22  9:39 ` [PATCH v14 10/18] genirq/matrix: Dynamic bitmap allocation Anup Patel
2024-02-22  9:39 ` [PATCH v14 11/18] irqchip: Add RISC-V incoming MSI controller early driver Anup Patel
2024-02-22 13:13   ` Björn Töpel
2024-02-22 13:42     ` Anup Patel
2024-02-22 14:15       ` Björn Töpel
2024-02-23  8:28   ` Thomas Gleixner
2024-02-23  9:52     ` Anup Patel
2024-02-22  9:40 ` [PATCH v14 12/18] irqchip/riscv-imsic: Add device MSI domain support for platform devices Anup Patel
2024-02-22 13:15   ` Björn Töpel
2024-02-22 13:44     ` Anup Patel
2024-02-22  9:40 ` [PATCH v14 13/18] irqchip/riscv-imsic: Add device MSI domain support for PCI devices Anup Patel
2024-02-22 13:14   ` Björn Töpel
2024-02-22 13:30     ` Anup Patel
2024-02-22 14:05       ` Björn Töpel
2024-02-22  9:40 ` [PATCH v14 14/18] dt-bindings: interrupt-controller: Add RISC-V advanced PLIC Anup Patel
2024-02-22  9:40 ` [PATCH v14 15/18] irqchip: Add RISC-V advanced PLIC driver for direct-mode Anup Patel
2024-02-22  9:40 ` [PATCH v14 16/18] irqchip/riscv-aplic: Add support for MSI-mode Anup Patel
2024-02-22  9:40 ` [PATCH v14 17/18] RISC-V: Select APLIC and IMSIC drivers Anup Patel
2024-02-22  9:40 ` [PATCH v14 18/18] MAINTAINERS: Add entry for RISC-V AIA drivers Anup Patel

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