Re: [PATCH v15,RESEND 21/23] PCI: starfive: Add JH7110 PCIe controller

[Kevin Xie <kevin.xie@starfivetech.com>]

> On Tue, Feb 27, 2024 at 06:35:20PM +0800, Minda Chen wrote:
> > Add StarFive JH7110 SoC PCIe controller platform driver codes, JH7110
> > with PLDA host PCIe core.
> >
> > Signed-off-by: Minda Chen <minda.chen@starfivetech.com>
> > Co-developed-by: Kevin Xie <kevin.xie@starfivetech.com>
> > Reviewed-by: Mason Huo <mason.huo@starfivetech.com>
> > ---
> >  MAINTAINERS                                 |   7 +
> >  drivers/pci/controller/plda/Kconfig         |  12 +
> >  drivers/pci/controller/plda/Makefile        |   1 +
> >  drivers/pci/controller/plda/pcie-plda.h     |  71 ++-
> >  drivers/pci/controller/plda/pcie-starfive.c | 473
> > ++++++++++++++++++++
> >  5 files changed, 563 insertions(+), 1 deletion(-)  create mode 100644
> > drivers/pci/controller/plda/pcie-starfive.c
> >
> > diff --git a/MAINTAINERS b/MAINTAINERS index
> > fc9576e69a71..d3b0a0fb754f 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -17078,6 +17078,13 @@ S:	Maintained
> >  F:	Documentation/devicetree/bindings/pci/socionext,uniphier-pcie*
> >  F:	drivers/pci/controller/dwc/pcie-uniphier*
> >
> > +PCIE DRIVER FOR STARFIVE JH71x0
> > +M:	Kevin Xie <kevin.xie@starfivetech.com>
> > +L:	linux-pci@vger.kernel.org
> > +S:	Maintained
> > +F:	Documentation/devicetree/bindings/pci/starfive*
> > +F:	drivers/pci/controller/plda/pcie-starfive.c
> > +
> >  PCIE DRIVER FOR ST SPEAR13XX
> >  M:	Pratyush Anand <pratyush.anand@gmail.com>
> >  L:	linux-pci@vger.kernel.org

> > diff --git a/drivers/pci/controller/plda/pcie-plda.h
> > b/drivers/pci/controller/plda/pcie-plda.h
> > index 7b69891700a4..04e385758a2f 100644
> > --- a/drivers/pci/controller/plda/pcie-plda.h
> > +++ b/drivers/pci/controller/plda/pcie-plda.h
> > @@ -10,10 +10,20 @@
> >  #define PLDA_MAX_NUM_MSI_IRQS			32
> >
> >  /* PCIe Bridge Phy Regs */
> > +#define GEN_SETTINGS				0x80
> > +#define  RP_ENABLE				1
> > +#define PCIE_PCI_IDS_DW1			0x9c
> > +#define  IDS_CLASS_CODE_SHIFT			16
> > +#define  REVISION_ID_MASK			GENMASK(7, 0)
> > +#define  CLASS_CODE_ID_MASK			GENMASK(31, 8)
> >  #define PCIE_PCI_IRQ_DW0			0xa8
> >  #define  MSIX_CAP_MASK				BIT(31)
> >  #define  NUM_MSI_MSGS_MASK			GENMASK(6, 4)
> >  #define  NUM_MSI_MSGS_SHIFT			4
> > +#define PCI_MISC				0xb4
> > +#define  PHY_FUNCTION_DIS			BIT(15)
> > +#define PCIE_WINROM				0xfc
> > +#define  PREF_MEM_WIN_64_SUPPORT		BIT(3)
> >
> >  #define IMASK_LOCAL				0x180
> >  #define  DMA_END_ENGINE_0_MASK			0x00000000u
> > @@ -65,6 +75,8 @@
> >  #define ISTATUS_HOST				0x18c
> >  #define IMSI_ADDR				0x190
> >  #define ISTATUS_MSI				0x194
> > +#define PMSG_SUPPORT_RX				0x3f0
> > +#define  PMSG_LTR_SUPPORT			BIT(2)
> >
> >  /* PCIe Master table init defines */
> >  #define ATR0_PCIE_WIN0_SRCADDR_PARAM		0x600u
> > @@ -86,6 +98,8 @@
> >  #define  PCIE_TX_RX_INTERFACE			0x00000000u
> >  #define  PCIE_CONFIG_INTERFACE			0x00000001u
> >
> > +#define CONFIG_SPACE_ADDR_OFFSET		0x1000u
> > +
> >  #define ATR_ENTRY_SIZE				32
> >
> >  enum plda_int_event {
> > @@ -200,4 +214,59 @@ static inline void plda_set_default_msi(struct
> plda_msi *msi)
> >  	msi->vector_phy = IMSI_ADDR;
> >  	msi->num_vectors = PLDA_MAX_NUM_MSI_IRQS;  } -#endif
> > +
> > +static inline void plda_pcie_enable_root_port(struct plda_pcie_rp
> > +*plda) {
> > +	u32 value;
> > +
> > +	value = readl_relaxed(plda->bridge_addr + GEN_SETTINGS);
> > +	value |= RP_ENABLE;
> > +	writel_relaxed(value, plda->bridge_addr + GEN_SETTINGS); }
> > +
> > +static inline void plda_pcie_set_standard_class(struct plda_pcie_rp
> > +*plda) {
> > +	u32 value;
> > +
> > +	/* set class code and reserve revision id */
> > +	value = readl_relaxed(plda->bridge_addr + PCIE_PCI_IDS_DW1);
> > +	value &= REVISION_ID_MASK;
> > +	value |= (PCI_CLASS_BRIDGE_PCI << IDS_CLASS_CODE_SHIFT);
> > +	writel_relaxed(value, plda->bridge_addr + PCIE_PCI_IDS_DW1); }
> > +
> > +static inline void plda_pcie_set_pref_win_64bit(struct plda_pcie_rp
> > +*plda) {
> > +	u32 value;
> > +
> > +	value = readl_relaxed(plda->bridge_addr + PCIE_WINROM);
> > +	value |= PREF_MEM_WIN_64_SUPPORT;
> > +	writel_relaxed(value, plda->bridge_addr + PCIE_WINROM); }
> 
> What does this do ?
> 

This is an internal register to enable the prefetchable memory window
64-bit addressing support. ( disabled by default)
After this enable configuration, the address translation config in DTS
and ATU about 64-bit prefetchable memory are useful.

I will add the annotation here in the next version.

> > +static inline void plda_pcie_disable_ltr(struct plda_pcie_rp *plda) {
> > +	u32 value;
> > +
> > +	value = readl_relaxed(plda->bridge_addr + PMSG_SUPPORT_RX);
> > +	value &= ~PMSG_LTR_SUPPORT;
> > +	writel_relaxed(value, plda->bridge_addr + PMSG_SUPPORT_RX); }
> > +
> > +static inline void plda_pcie_disable_func(struct plda_pcie_rp *plda)
> > +{
> > +	u32 value;
> > +
> > +	value = readl_relaxed(plda->bridge_addr + PCI_MISC);
> > +	value |= PHY_FUNCTION_DIS;
> > +	writel_relaxed(value, plda->bridge_addr + PCI_MISC); }
> > +
> > +static inline void plda_pcie_write_rc_bar(struct plda_pcie_rp *plda,
> > +u64 val) {
> > +	void __iomem *addr = plda->bridge_addr +
> CONFIG_SPACE_ADDR_OFFSET;
> > +
> > +	writel_relaxed(lower_32_bits(val), addr + PCI_BASE_ADDRESS_0);
> > +	writel_relaxed(upper_32_bits(val), addr + PCI_BASE_ADDRESS_1); }
> > +#endif /* _PCIE_PLDA_H */
> > diff --git a/drivers/pci/controller/plda/pcie-starfive.c
> > b/drivers/pci/controller/plda/pcie-starfive.c
> > new file mode 100644
> > index 000000000000..9bb9f0e29565
> > --- /dev/null
> > +++ b/drivers/pci/controller/plda/pcie-starfive.c
> > @@ -0,0 +1,473 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * PCIe host controller driver for StarFive JH7110 Soc.
> > + *
> > + * Copyright (C) 2023 StarFive Technology Co., Ltd.
> > + */
> > +
> > +#include <linux/bitfield.h>
> > +#include <linux/clk.h>
> > +#include <linux/delay.h>
> > +#include <linux/gpio/consumer.h>
> > +#include <linux/interrupt.h>
> > +#include <linux/kernel.h>
> > +#include <linux/mfd/syscon.h>
> > +#include <linux/module.h>
> > +#include <linux/of_address.h>
> > +#include <linux/of_irq.h>
> > +#include <linux/of_pci.h>
> > +#include <linux/pci.h>
> > +#include <linux/phy/phy.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_runtime.h>
> > +#include <linux/regmap.h>
> > +#include <linux/reset.h>
> > +#include "../../pci.h"
> > +
> > +#include "pcie-plda.h"
> > +
> > +#define PCIE_FUNC_NUM			4
> > +
> > +/* system control */
> > +#define STG_SYSCON_PCIE0_BASE			0x48
> > +#define STG_SYSCON_PCIE1_BASE			0x1f8
> > +
> > +#define STG_SYSCON_AR_OFFSET			0x78
> > +#define STG_SYSCON_AXI4_SLVL_AR_MASK		GENMASK(22, 8)
> > +#define STG_SYSCON_AXI4_SLVL_PHY_AR(x)
> 	FIELD_PREP(GENMASK(20, 17), x)
> > +#define STG_SYSCON_AW_OFFSET			0x7c
> > +#define STG_SYSCON_AXI4_SLVL_AW_MASK		GENMASK(14, 0)
> > +#define STG_SYSCON_AXI4_SLVL_PHY_AW(x)
> 	FIELD_PREP(GENMASK(12, 9), x)
> > +#define STG_SYSCON_CLKREQ			BIT(22)
> > +#define STG_SYSCON_CKREF_SRC_MASK		GENMASK(19, 18)
> > +#define STG_SYSCON_RP_NEP_OFFSET		0xe8
> > +#define STG_SYSCON_K_RP_NEP			BIT(8)
> > +#define STG_SYSCON_LNKSTA_OFFSET		0x170
> > +#define DATA_LINK_ACTIVE			BIT(5)
> > +
> > +/* Parameters for the waiting for link up routine */
> > +#define LINK_WAIT_MAX_RETRIES	10
> > +#define LINK_WAIT_USLEEP_MIN	90000
> > +#define LINK_WAIT_USLEEP_MAX	100000
> > +
> > +struct starfive_jh7110_pcie {
> > +	struct plda_pcie_rp plda;
> > +	struct reset_control *resets;
> > +	struct clk_bulk_data *clks;
> > +	struct regmap *reg_syscon;
> > +	struct gpio_desc *power_gpio;
> > +	struct gpio_desc *reset_gpio;
> > +	struct phy *phy;
> > +
> > +	unsigned int stg_pcie_base;
> > +	int num_clks;
> > +};
> > +
> > +/*
> > + * The BAR0/1 of bridge should be hidden during enumeration to
> > + * avoid the sizing and resource allocation by PCIe core.
> 
> Please explain. This is what's preventing this driver to re-use the
> PCI_HOST_COMMON infrastructure and it is unclear why.
> 

Sorry, we didn't explain it clearly enough here.
JH7110 PCIe port BAR0/1 is configured as 64-bit prefetchable memory
space, PCIe read and write requests targeting BAR0/1 are routed to so
called 'Bridge Configuration space' in PLDA datasheet, which contains
the bridge internal registers, such as interrupt, DMA & ATU registers...

JH7110 can access the Bridge Configuration space by local bus, and don`t
want the bridge internal registers accessed by the DMA from EP devices.
Thus, they are unimplemented and should be hidden.

I will modify the annotation in next version if you think it is ok.

> > + */
> > +static bool starfive_pcie_hide_rc_bar(struct pci_bus *bus, unsigned int
> devfn,
> > +				      int offset)
> > +{
> > +	if (pci_is_root_bus(bus) && !devfn &&
> > +	    (offset == PCI_BASE_ADDRESS_0 || offset == PCI_BASE_ADDRESS_1))
> > +		return true;
> > +
> > +	return false;
> > +}
> > +
> > +static int starfive_pcie_config_write(struct pci_bus *bus, unsigned int devfn,
> > +				      int where, int size, u32 value) {
> > +	if (starfive_pcie_hide_rc_bar(bus, devfn, where))
> > +		return PCIBIOS_SUCCESSFUL;
> > +
> > +	return pci_generic_config_write(bus, devfn, where, size, value); }
> > +
> > +static int starfive_pcie_config_read(struct pci_bus *bus, unsigned int devfn,
> > +				     int where, int size, u32 *value) {
> > +	if (starfive_pcie_hide_rc_bar(bus, devfn, where)) {
> > +		*value = 0;
> > +		return PCIBIOS_SUCCESSFUL;
> > +	}
> > +
> > +	return pci_generic_config_read(bus, devfn, where, size, value); }
> > +
> > +static int starfive_pcie_parse_dt(struct starfive_jh7110_pcie *pcie,
> > +				  struct device *dev)
> > +{
> > +	int domain_nr;
> > +
> > +	pcie->num_clks = devm_clk_bulk_get_all(dev, &pcie->clks);
> > +	if (pcie->num_clks < 0)
> > +		return dev_err_probe(dev, pcie->num_clks,
> > +				     "failed to get pcie clocks\n");
> > +
> > +	pcie->resets = devm_reset_control_array_get_exclusive(dev);
> > +	if (IS_ERR(pcie->resets))
> > +		return dev_err_probe(dev, PTR_ERR(pcie->resets),
> > +				     "failed to get pcie resets");
> > +
> > +	pcie->reg_syscon =
> > +		syscon_regmap_lookup_by_phandle(dev->of_node,
> > +						"starfive,stg-syscon");
> > +
> > +	if (IS_ERR(pcie->reg_syscon))
> > +		return dev_err_probe(dev, PTR_ERR(pcie->reg_syscon),
> > +				     "failed to parse starfive,stg-syscon\n");
> > +
> > +	pcie->phy = devm_phy_optional_get(dev, NULL);
> > +	if (IS_ERR(pcie->phy))
> > +		return dev_err_probe(dev, PTR_ERR(pcie->phy),
> > +				     "failed to get pcie phy\n");
> > +
> > +	domain_nr = of_get_pci_domain_nr(dev->of_node);
> > +
> > +	if (domain_nr < 0 || domain_nr > 1)
> > +		return dev_err_probe(dev, -ENODEV,
> > +				     "failed to get valid pcie domain\n");
> > +
> > +	if (domain_nr == 0)
> > +		pcie->stg_pcie_base = STG_SYSCON_PCIE0_BASE;
> > +	else
> > +		pcie->stg_pcie_base = STG_SYSCON_PCIE1_BASE;
> 
> I don't agree with this. The domain number is a software allocated value
> attached to a controller. It is written nowhere that you can't swap them and
> leave this code path broken.
> 

We set 'linux,pci-domain = <0>' in our pcie0 DTS node, and <1> for 
pcie1. The value should be static now.

As the STG system controller defines different bases in PCIe RP0 & RP1,
we have to identify which controller is doing the hardware initialization.
We discussed this before with other maintainers, do you have a better
suggestion?

> > +	pcie->reset_gpio = devm_gpiod_get_optional(dev, "perst",
> > +						   GPIOD_OUT_HIGH);
> > +	if (IS_ERR(pcie->reset_gpio))
> > +		return dev_err_probe(dev, PTR_ERR(pcie->reset_gpio),
> > +				     "failed to get perst-gpio\n");
> > +
> > +	pcie->power_gpio = devm_gpiod_get_optional(dev, "enable",
> > +						   GPIOD_OUT_LOW);
> > +	if (IS_ERR(pcie->power_gpio))
> > +		return dev_err_probe(dev, PTR_ERR(pcie->power_gpio),
> > +				     "failed to get power-gpio\n");
> > +
> > +	return 0;
> > +}
> > +
> > +static struct pci_ops starfive_pcie_ops = {
> > +	.map_bus	= plda_pcie_map_bus,
> 
> It looks like this is an ECAM driver with the read/config quirks for read/write in
> the method below. Please explain why they are needed.
> 

Yes, that's for the hide RC BAR operations mentioned above.

> > +	.read           = starfive_pcie_config_read,
> > +	.write          = starfive_pcie_config_write,
> > +};
> > +
> > +static int starfive_pcie_clk_rst_init(struct starfive_jh7110_pcie
> > +*pcie) {
> > +	struct device *dev = pcie->plda.dev;
> > +	int ret;
> > +
> > +	/* PCIe PCI Standard Configuration Identification Settings. */
> > +	plda_pcie_set_standard_class(plda);
> > +
> > +	/*
> > +	 * The LTR message forwarding of PCIe Message Reception was set by
> > +core
> 
> "LTR message forwarding of PCIe Message Reception".
> 
> What is this referring to ?
> 

Sorry, this sentence is ambiguous.
"PCIe Message Reception" is a register to enable the function about forwarding
specific PCIe messages to AXI application, such as ATS/LTR/OBFF messages...
Here we clear bit 2 to disable the LTR message forwarding to the AXI application.

I will modify the annotation in next version if you think it is ok.

Thank you for your valuable comments.
Kevin.

> Thanks,
> Lorenzo
> 
> > +	 * as default, but the forward id & addr are also need to be reset.
> > +	 * If we do not disable LTR message forwarding here, or set a legal
> > +	 * forwarding address, the kernel will get stuck after the driver probe.
> > +	 * To workaround, disable the LTR message forwarding support on
> > +	 * PCIe Message Reception.
> > +	 */
> > +	plda_pcie_disable_ltr(plda);
> > +
> > +	/* Prefetchable memory window 64-bit addressing support */
> > +	plda_pcie_set_pref_win_64bit(plda);
> > +
> >
> > _______________________________________________
> > linux-riscv mailing list
> > linux-riscv@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-riscv

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