From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: William Qiu <william.qiu@starfivetech.com>,
devicetree@vger.kernel.org, linux-spi@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Cc: Mark Brown <broonie@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
Conor Dooley <conor+dt@kernel.org>,
Emil Renner Berthing <kernel@esmil.dk>,
Ziv Xu <ziv.xu@starfivetech.com>
Subject: Re: [PATCH v3 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks for StarFive JH7110 SoC
Date: Wed, 21 Jun 2023 10:10:49 +0200 [thread overview]
Message-ID: <adc4d83e-5bec-b925-b55e-43ad441ad8ee@linaro.org> (raw)
In-Reply-To: <fb608232-f44d-21cf-7e0e-28829196e677@starfivetech.com>
On 21/06/2023 08:45, William Qiu wrote:
>
>
> On 2023/6/19 20:17, Krzysztof Kozlowski wrote:
>> On 19/06/2023 10:35, William Qiu wrote:
>>> The QSPI controller needs three clock items to work properly on StarFive
>>> JH7110 SoC, so there is need to change the maxItems's value to 3. Other
>>> platforms do not have this constraint.
>>>
>>> Signed-off-by: William Qiu <william.qiu@starfivetech.com>
>>> Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
>>> Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
>>> ---
>>> .../bindings/spi/cdns,qspi-nor.yaml | 20 ++++++++++++++++++-
>>> 1 file changed, 19 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
>>> index b310069762dd..1b83cbb9a086 100644
>>> --- a/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
>>> +++ b/Documentation/devicetree/bindings/spi/cdns,qspi-nor.yaml
>>> @@ -26,6 +26,15 @@ allOf:
>>> const: starfive,jh7110-qspi
>>> then:
>>> properties:
>>> + clocks:
>>> + maxItems: 3
>>> +
>>> + clock-names:
>>> + items:
>>> + - const: ref
>>> + - const: ahb
>>> + - const: apb
>>
>> You are duplicating top-level property. Define the items only in one
>> place. If this list is applicable to everything, then in top-level property.
>>
> Only in JH7110 SoC need there clocks, other platforms do not have this constraint.
> So I need to duplicating top-level property.
You don't need, why? Why writing something twice is an answer to "JH7110
needs 3 clocks"? It's not related.
What is the clock for all other variants?
>>> +
>>> resets:
>>> minItems: 2
>>> maxItems: 3
>>> @@ -38,6 +47,9 @@ allOf:
>>>
>>> else:
>>> properties:
>>> + clocks:
>>> + maxItems: 1
>>
>> clock-names is missing. They must be in sync with clocks. What is the
>> first clock?
>>
> But there are no clock-names before, should I add it?
Then let's just disallow it. Either you define it or you not allow it.
>>> +
>>> resets:
>>> maxItems: 2
>>>
>>> @@ -70,7 +82,13 @@ properties:
>>> maxItems: 1
>>>
>>> clocks:
>>> - maxItems: 1
>>> + maxItems: 3
>>
>>
>> You did not test it before sending. minItems is missing.
>>
> I will add it.
> As for other platforms, should I use enum to constraint the clocks?
What is the clock on other platforms?
Best regards,
Krzysztof
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-06-21 8:11 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-19 8:35 [PATCH v3 0/3] Add initialization of clock for StarFive JH7110 SoC William Qiu
2023-06-19 8:35 ` [PATCH v3 1/3] dt-bindings: qspi: cdns,qspi-nor: Add clocks " William Qiu
2023-06-19 9:16 ` Rob Herring
2023-06-21 6:16 ` William Qiu
2023-06-19 12:17 ` Krzysztof Kozlowski
2023-06-21 6:45 ` William Qiu
2023-06-21 8:10 ` Krzysztof Kozlowski [this message]
2023-06-27 7:53 ` William Qiu
2023-06-19 8:35 ` [PATCH v3 2/3] spi: cadence-quadspi: Add clock configuration for StarFive JH7110 QSPI William Qiu
2023-06-19 8:35 ` [PATCH v3 3/3] riscv: dts: starfive: Add QSPI controller node for StarFive JH7110 SoC William Qiu
2023-06-19 12:20 ` Krzysztof Kozlowski
2023-06-21 6:04 ` William Qiu
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=adc4d83e-5bec-b925-b55e-43ad441ad8ee@linaro.org \
--to=krzysztof.kozlowski@linaro.org \
--cc=broonie@kernel.org \
--cc=conor+dt@kernel.org \
--cc=devicetree@vger.kernel.org \
--cc=kernel@esmil.dk \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=linux-spi@vger.kernel.org \
--cc=robh+dt@kernel.org \
--cc=william.qiu@starfivetech.com \
--cc=ziv.xu@starfivetech.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).