From: Paul Walmsley <paul.walmsley@sifive.com>
To: daniel.lezcano@linaro.org, tglx@linutronix.de
Cc: Damien Le Moal <damien.lemoal@wdc.com>,
Anup Patel <anup@brainfault.org>,
Palmer Dabbelt <palmer@sifive.com>,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
Christoph Hellwig <hch@lst.de>
Subject: Re: [PATCH 06/12] riscv: add support for MMIO access to the timer registers
Date: Tue, 5 Nov 2019 10:01:10 -0800 (PST) [thread overview]
Message-ID: <alpine.DEB.2.21.9999.1911050958020.20606@viisi.sifive.com> (raw)
In-Reply-To: <20191028121043.22934-7-hch@lst.de>
Daniel, Thomas,
On Mon, 28 Oct 2019, Christoph Hellwig wrote:
> When running in M-mode we can't use the SBI to set the timer, and
> don't have access to the time CSR as that usually is emulated by
> M-mode. Instead provide code that directly accesses the MMIO for
> the timer.
>
> Signed-off-by: Christoph Hellwig <hch@lst.de>
> Reviewed-by: Anup Patel <anup@brainfault.org>
Care to give a quick ack to the drivers/clocksource/timer-riscv.c changes?
thanks,
- Paul
> ---
> arch/riscv/include/asm/sbi.h | 3 ++-
> arch/riscv/include/asm/timex.h | 19 +++++++++++++++++--
> drivers/clocksource/timer-riscv.c | 21 +++++++++++++++++----
> 3 files changed, 36 insertions(+), 7 deletions(-)
>
> diff --git a/arch/riscv/include/asm/sbi.h b/arch/riscv/include/asm/sbi.h
> index 0cb74eccc73f..a4774bafe033 100644
> --- a/arch/riscv/include/asm/sbi.h
> +++ b/arch/riscv/include/asm/sbi.h
> @@ -95,7 +95,8 @@ static inline void sbi_remote_sfence_vma_asid(const unsigned long *hart_mask,
> SBI_CALL_4(SBI_REMOTE_SFENCE_VMA_ASID, hart_mask, start, size, asid);
> }
> #else /* CONFIG_RISCV_SBI */
> -/* stub to for code is only reachable under IS_ENABLED(CONFIG_RISCV_SBI): */
> +/* stubs to for code is only reachable under IS_ENABLED(CONFIG_RISCV_SBI): */
> +void sbi_set_timer(uint64_t stime_value);
> void sbi_remote_fence_i(const unsigned long *hart_mask);
> #endif /* CONFIG_RISCV_SBI */
> #endif /* _ASM_RISCV_SBI_H */
> diff --git a/arch/riscv/include/asm/timex.h b/arch/riscv/include/asm/timex.h
> index c7ef131b9e4c..e17837d61667 100644
> --- a/arch/riscv/include/asm/timex.h
> +++ b/arch/riscv/include/asm/timex.h
> @@ -7,12 +7,25 @@
> #define _ASM_RISCV_TIMEX_H
>
> #include <asm/csr.h>
> +#include <asm/io.h>
>
> typedef unsigned long cycles_t;
>
> +extern u64 __iomem *riscv_time_val;
> +extern u64 __iomem *riscv_time_cmp;
> +
> +#ifdef CONFIG_64BIT
> +#define mmio_get_cycles() readq_relaxed(riscv_time_val)
> +#else
> +#define mmio_get_cycles() readl_relaxed(riscv_time_val)
> +#define mmio_get_cycles_hi() readl_relaxed(((u32 *)riscv_time_val) + 1)
> +#endif
> +
> static inline cycles_t get_cycles(void)
> {
> - return csr_read(CSR_TIME);
> + if (IS_ENABLED(CONFIG_RISCV_SBI))
> + return csr_read(CSR_TIME);
> + return mmio_get_cycles();
> }
> #define get_cycles get_cycles
>
> @@ -24,7 +37,9 @@ static inline u64 get_cycles64(void)
> #else /* CONFIG_64BIT */
> static inline u32 get_cycles_hi(void)
> {
> - return csr_read(CSR_TIMEH);
> + if (IS_ENABLED(CONFIG_RISCV_SBI))
> + return csr_read(CSR_TIMEH);
> + return mmio_get_cycles_hi();
> }
>
> static inline u64 get_cycles64(void)
> diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> index d083bfb535f6..f3eb0c04401a 100644
> --- a/drivers/clocksource/timer-riscv.c
> +++ b/drivers/clocksource/timer-riscv.c
> @@ -3,9 +3,9 @@
> * Copyright (C) 2012 Regents of the University of California
> * Copyright (C) 2017 SiFive
> *
> - * All RISC-V systems have a timer attached to every hart. These timers can be
> - * read from the "time" and "timeh" CSRs, and can use the SBI to setup
> - * events.
> + * All RISC-V systems have a timer attached to every hart. These timers can
> + * either be read from the "time" and "timeh" CSRs, and can use the SBI to
> + * setup events, or directly accessed using MMIO registers.
> */
> #include <linux/clocksource.h>
> #include <linux/clockchips.h>
> @@ -13,14 +13,27 @@
> #include <linux/delay.h>
> #include <linux/irq.h>
> #include <linux/sched_clock.h>
> +#include <linux/io-64-nonatomic-lo-hi.h>
> #include <asm/smp.h>
> #include <asm/sbi.h>
>
> +u64 __iomem *riscv_time_cmp;
> +u64 __iomem *riscv_time_val;
> +
> +static inline void mmio_set_timer(u64 val)
> +{
> + writeq_relaxed(val,
> + riscv_time_cmp + cpuid_to_hartid_map(smp_processor_id()));
> +}
> +
> static int riscv_clock_next_event(unsigned long delta,
> struct clock_event_device *ce)
> {
> csr_set(CSR_IE, IE_TIE);
> - sbi_set_timer(get_cycles64() + delta);
> + if (IS_ENABLED(CONFIG_RISCV_SBI))
> + sbi_set_timer(get_cycles64() + delta);
> + else
> + mmio_set_timer(get_cycles64() + delta);
> return 0;
> }
>
> --
> 2.20.1
>
>
- Paul
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next prev parent reply other threads:[~2019-11-05 18:01 UTC|newest]
Thread overview: 40+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-28 12:10 RISC-V nommu support v6 Christoph Hellwig
2019-10-28 12:10 ` [PATCH 01/12] riscv: abstract out CSR names for supervisor vs machine mode Christoph Hellwig
2019-11-05 17:56 ` Paul Walmsley
2019-11-05 17:57 ` Paul Walmsley
2019-11-05 18:02 ` Marc Zyngier
2019-11-12 10:38 ` Thomas Gleixner
2019-11-14 7:30 ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 02/12] riscv: don't allow selecting SBI based drivers for M-mode Christoph Hellwig
2019-11-14 7:31 ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 03/12] riscv: poison SBI calls " Christoph Hellwig
2019-10-31 23:55 ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 04/12] riscv: cleanup the default power off implementation Christoph Hellwig
2019-10-31 20:49 ` Paul Walmsley
2019-10-31 23:56 ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 05/12] riscv: implement remote sfence.i using IPIs Christoph Hellwig
2019-10-31 23:57 ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 06/12] riscv: add support for MMIO access to the timer registers Christoph Hellwig
2019-11-05 18:01 ` Paul Walmsley [this message]
2019-11-12 10:39 ` Thomas Gleixner
2019-11-17 23:06 ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 07/12] riscv: provide native clint access for M-mode Christoph Hellwig
2019-10-28 12:10 ` [PATCH 08/12] riscv: read the hart ID from mhartid on boot Christoph Hellwig
2019-10-28 12:10 ` [PATCH 09/12] riscv: clear the instruction cache and all registers when booting Christoph Hellwig
2019-11-14 7:45 ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 10/12] riscv: add nommu support Christoph Hellwig
2019-11-17 23:13 ` Paul Walmsley
2019-12-16 22:03 ` David Abdurachmanov
2019-12-17 3:18 ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 11/12] riscv: provide a flat image loader Christoph Hellwig
2019-11-17 23:14 ` Paul Walmsley
2019-10-28 12:10 ` [PATCH 12/12] riscv: disable the EFI PECOFF header for M-mode Christoph Hellwig
2019-10-30 20:21 ` RISC-V nommu support v6 Paul Walmsley
2019-10-31 15:52 ` Christoph Hellwig
2019-10-31 20:13 ` Paul Walmsley
2019-11-23 2:19 ` Paul Walmsley
2019-12-11 8:42 ` Greentime Hu
2020-02-12 12:19 ` Greentime Hu
2019-11-11 9:47 ` Christoph Hellwig
2019-11-11 17:02 ` Paul Walmsley
2019-11-13 13:18 ` Christoph Hellwig
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