From: Maximilian Luz <luzmaximilian@gmail.com>
To: Sunil V L <sunilvl@ventanamicro.com>
Cc: linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-riscv@lists.infradead.org, linux-acpi@vger.kernel.org,
linux-crypto@vger.kernel.org,
platform-driver-x86@vger.kernel.org, llvm@lists.linux.dev,
Jonathan Corbet <corbet@lwn.net>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>, Len Brown <lenb@kernel.org>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>,
Weili Qian <qianweili@huawei.com>,
Zhou Wang <wangzhou1@hisilicon.com>,
Herbert Xu <herbert@gondor.apana.org.au>,
Marc Zyngier <maz@kernel.org>,
Hans de Goede <hdegoede@redhat.com>,
Mark Gross <markgross@kernel.org>,
Nathan Chancellor <nathan@kernel.org>,
Nick Desaulniers <ndesaulniers@google.com>,
Tom Rix <trix@redhat.com>,
"Rafael J . Wysocki" <rafael@kernel.org>,
"David S . Miller" <davem@davemloft.net>
Subject: Re: [PATCH V4 22/23] platform/surface: Disable for RISC-V
Date: Wed, 5 Apr 2023 13:35:45 +0200 [thread overview]
Message-ID: <bedd7426-5875-dbd7-38fe-2e943c7109f8@gmail.com> (raw)
In-Reply-To: <ZC1XUdD3DFnNauQ2@sunil-laptop>
On 4/5/23 13:11, Sunil V L wrote:
> On Wed, Apr 05, 2023 at 11:33:00AM +0200, Maximilian Luz wrote:
>> On 4/4/23 20:20, Sunil V L wrote:
>>> With CONFIG_ACPI enabled for RISC-V, this driver gets enabled
>>> in allmodconfig build. However, RISC-V doesn't support sub-word
>>> atomics which is used by this driver. Due to this, the build fails
>>> with below error.
>>>
>>> In function ‘ssh_seq_next’,
>>> inlined from ‘ssam_request_write_data’ at drivers/platform/surface/aggregator/controller.c:1483:8:
>>> ././include/linux/compiler_types.h:399:45: error: call to ‘__compiletime_assert_335’ declared with attribute error: BUILD_BUG failed
>>> 399 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
>>> | ^
>>> ./include/linux/compiler.h:78:45: note: in definition of macro ‘unlikely’
>>> 78 | # define unlikely(x) __builtin_expect(!!(x), 0)
>>> | ^
>>> ././include/linux/compiler_types.h:387:9: note: in expansion of macro ‘__compiletime_assert’
>>> 387 | __compiletime_assert(condition, msg, prefix, suffix)
>>> | ^~~~~~~~~~~~~~~~~~~~
>>> ././include/linux/compiler_types.h:399:9: note: in expansion of macro ‘_compiletime_assert’
>>> 399 | _compiletime_assert(condition, msg, __compiletime_assert_, __COUNTER__)
>>> | ^~~~~~~~~~~~~~~~~~~
>>> ./include/linux/build_bug.h:39:37: note: in expansion of macro ‘compiletime_assert’
>>> 39 | #define BUILD_BUG_ON_MSG(cond, msg) compiletime_assert(!(cond), msg)
>>> | ^~~~~~~~~~~~~~~~~~
>>> ./include/linux/build_bug.h:59:21: note: in expansion of macro ‘BUILD_BUG_ON_MSG’
>>> 59 | #define BUILD_BUG() BUILD_BUG_ON_MSG(1, "BUILD_BUG failed")
>>> | ^~~~~~~~~~~~~~~~
>>> ./arch/riscv/include/asm/cmpxchg.h:335:17: note: in expansion of macro ‘BUILD_BUG’
>>> 335 | BUILD_BUG(); \
>>> | ^~~~~~~~~
>>> ./arch/riscv/include/asm/cmpxchg.h:344:30: note: in expansion of macro ‘__cmpxchg’
>>> 344 | (__typeof__(*(ptr))) __cmpxchg((ptr), \
>>> | ^~~~~~~~~
>>> ./include/linux/atomic/atomic-instrumented.h:1916:9: note: in expansion of macro ‘arch_cmpxchg’
>>> 1916 | arch_cmpxchg(__ai_ptr, __VA_ARGS__); \
>>> | ^~~~~~~~~~~~
>>> drivers/platform/surface/aggregator/controller.c:61:32: note: in expansion of macro ‘cmpxchg’
>>> 61 | while (unlikely((ret = cmpxchg(&c->value, old, new)) != old)) {
>>> | ^~~~~~~
>>>
>>> So, disable this driver for RISC-V even when ACPI is enabled for now.
>>
>> CONFIG_SURFACE_PLATFORMS should be enabled for ARM64 || X86 || COMPILE_TEST only,
>> so I guess the issue only happens when compiling with the latter enabled?
>>
>> I'm not aware of any current plans of MS to release RISC-V-based Surface
>> devices, so you could maybe also just explicitly disable CONFIG_SURFACE_PLATFORMS.
>> In any case, I don't see any issues with disabling the whole platform/surface
>> or only individual drivers for RISC-V, so for either solution:
>>
>> Acked-by: Maximilian Luz <luzmaximilian@gmail.com>
>>
> Hi Maximilian,
>
> Thanks!. Yes, COMPILE_TEST gets enabled for allmodconfig builds. Since
> the whole intention of COMPILE_TEST appears to be able to compile-test
> drivers on a platform than they are supposed to be used, I think it is
> better not to skip whole set of drivers but only that which can not build.
> So, I prefer to keep this change as is.
Hi Sunil,
What I wanted to say with my previous mail: I'm fairly confident that
platform/surface drivers will not be actively used on RISC-V hardware any
time soon (not sure if that came over in this way). But whatever you/others
prefer, I'm happy with either.
Best regards,
Max
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-04-05 11:36 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-04 18:20 [PATCH V4 00/23] Add basic ACPI support for RISC-V Sunil V L
2023-04-04 18:20 ` [PATCH V4 01/23] riscv: move sbi_init() earlier before jump_label_init() Sunil V L
2023-04-04 18:20 ` [PATCH V4 02/23] ACPICA: MADT: Add RISC-V INTC interrupt controller Sunil V L
2023-04-04 18:20 ` [PATCH V4 03/23] ACPICA: Add structure definitions for RISC-V RHCT Sunil V L
2023-04-04 18:20 ` [PATCH V4 04/23] ACPI: tables: Print RINTC information when MADT is parsed Sunil V L
2023-04-04 18:20 ` [PATCH V4 05/23] ACPI: OSL: Make should_use_kmap() 0 for RISC-V Sunil V L
2023-04-26 16:47 ` Björn Töpel
2023-04-27 9:27 ` Sunil V L
2023-04-27 11:24 ` Björn Töpel
2023-04-04 18:20 ` [PATCH V4 06/23] RISC-V: Add support to build the ACPI core Sunil V L
2023-04-26 18:44 ` Palmer Dabbelt
2023-04-04 18:20 ` [PATCH V4 07/23] ACPI: processor_core: RISC-V: Enable mapping processor to the hartid Sunil V L
2023-04-04 18:20 ` [PATCH V4 08/23] RISC-V: ACPI: Cache and retrieve the RINTC structure Sunil V L
2023-04-04 20:14 ` Conor Dooley
2023-04-05 15:17 ` Andrew Jones
2023-04-06 3:46 ` Sunil V L
2023-04-26 18:45 ` Palmer Dabbelt
2023-04-27 9:22 ` Sunil V L
2023-04-27 10:25 ` Andrew Jones
2023-04-27 10:52 ` Sunil V L
2023-04-27 13:13 ` Andrew Jones
2023-04-04 18:20 ` [PATCH V4 09/23] drivers/acpi: RISC-V: Add RHCT related code Sunil V L
2023-04-26 18:45 ` Palmer Dabbelt
2023-04-04 18:20 ` [PATCH V4 10/23] RISC-V: smpboot: Create wrapper smp_setup() Sunil V L
2023-04-26 18:45 ` Palmer Dabbelt
2023-04-04 18:20 ` [PATCH V4 11/23] RISC-V: smpboot: Add ACPI support in smp_setup() Sunil V L
2023-04-05 14:58 ` Andrew Jones
2023-04-04 18:20 ` [PATCH V4 12/23] RISC-V: cpufeature: Avoid calling riscv_of_processor_hartid() Sunil V L
2023-04-04 20:46 ` Conor Dooley
2023-04-04 18:20 ` [PATCH V4 13/23] RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap() Sunil V L
2023-04-04 20:57 ` Conor Dooley
2023-04-05 13:35 ` Sunil V L
2023-04-05 14:31 ` Conor Dooley
2023-04-05 15:37 ` Andrew Jones
2023-04-29 10:31 ` Conor Dooley
2023-05-02 1:28 ` Sunil V L
2023-04-04 18:20 ` [PATCH V4 14/23] RISC-V: cpu: Enable cpuinfo for ACPI systems Sunil V L
2023-04-04 21:04 ` Conor Dooley
2023-04-04 18:20 ` [PATCH V4 15/23] irqchip/riscv-intc: Add ACPI support Sunil V L
2023-04-05 15:48 ` Andrew Jones
2023-04-06 3:47 ` Sunil V L
2023-04-04 18:20 ` [PATCH V4 16/23] clocksource/timer-riscv: Refactor riscv_timer_init_dt() Sunil V L
2023-04-04 21:25 ` Conor Dooley
2023-04-05 10:55 ` Sunil V L
2023-04-04 18:20 ` [PATCH V4 17/23] clocksource/timer-riscv: Add ACPI support Sunil V L
2023-04-04 21:27 ` Conor Dooley
2023-04-04 18:20 ` [PATCH V4 18/23] RISC-V: time.c: Add ACPI support for time_init() Sunil V L
2023-04-04 18:20 ` [PATCH V4 19/23] RISC-V: Add ACPI initialization in setup_arch() Sunil V L
2023-04-04 21:38 ` Conor Dooley
2023-04-05 15:11 ` Sunil V L
2023-04-05 15:30 ` Conor Dooley
2023-04-04 18:20 ` [PATCH V4 20/23] RISC-V: Enable ACPI in defconfig Sunil V L
2023-04-04 21:43 ` Conor Dooley
2023-04-05 10:58 ` Sunil V L
2023-04-04 18:20 ` [PATCH V4 21/23] MAINTAINERS: Add entry for drivers/acpi/riscv Sunil V L
2023-04-04 18:20 ` [PATCH V4 22/23] platform/surface: Disable for RISC-V Sunil V L
2023-04-05 4:19 ` Jessica Clarke
2023-04-05 11:29 ` Sunil V L
2023-04-05 9:33 ` Maximilian Luz
2023-04-05 11:11 ` Sunil V L
2023-04-05 11:35 ` Maximilian Luz [this message]
2023-04-04 18:20 ` [PATCH V4 23/23] crypto: hisilicon/qm: Workaround to enable build with RISC-V clang Sunil V L
2023-04-04 21:59 ` Conor Dooley
2023-04-05 10:46 ` Sunil V L
2023-04-05 8:16 ` Arnd Bergmann
2023-04-11 11:42 ` Weili Qian
2023-04-19 14:34 ` Arnd Bergmann
2023-04-04 18:42 ` [PATCH V4 00/23] Add basic ACPI support for RISC-V Conor Dooley
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=bedd7426-5875-dbd7-38fe-2e943c7109f8@gmail.com \
--to=luzmaximilian@gmail.com \
--cc=aou@eecs.berkeley.edu \
--cc=corbet@lwn.net \
--cc=daniel.lezcano@linaro.org \
--cc=davem@davemloft.net \
--cc=hdegoede@redhat.com \
--cc=herbert@gondor.apana.org.au \
--cc=lenb@kernel.org \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-crypto@vger.kernel.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=llvm@lists.linux.dev \
--cc=markgross@kernel.org \
--cc=maz@kernel.org \
--cc=nathan@kernel.org \
--cc=ndesaulniers@google.com \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=platform-driver-x86@vger.kernel.org \
--cc=qianweili@huawei.com \
--cc=rafael@kernel.org \
--cc=sunilvl@ventanamicro.com \
--cc=tglx@linutronix.de \
--cc=trix@redhat.com \
--cc=wangzhou1@hisilicon.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).