From: Palmer Dabbelt <palmer@dabbelt.com>
To: sunilvl@ventanamicro.com
Cc: rafael.j.wysocki@intel.com, linux-doc@vger.kernel.org,
trix@redhat.com, llvm@lists.linux.dev,
platform-driver-x86@vger.kernel.org,
linux-riscv@lists.infradead.org, qianweili@huawei.com,
herbert@gondor.apana.org.au, corbet@lwn.net,
Marc Zyngier <maz@kernel.org>,
daniel.lezcano@linaro.org, linux-acpi@vger.kernel.org,
lenb@kernel.org, aou@eecs.berkeley.edu, markgross@kernel.org,
hdegoede@redhat.com, Paul Walmsley <paul.walmsley@sifive.com>,
tglx@linutronix.de, nathan@kernel.org, ndesaulniers@google.com,
linux-kernel@vger.kernel.org, wangzhou1@hisilicon.com,
linux-crypto@vger.kernel.org, rafael@kernel.org,
ajones@ventanamicro.com, luzmaximilian@gmail.com,
davem@davemloft.net
Subject: Re: [PATCH V4 09/23] drivers/acpi: RISC-V: Add RHCT related code
Date: Wed, 26 Apr 2023 11:45:02 -0700 (PDT) [thread overview]
Message-ID: <mhng-c1242642-931b-4585-8c65-02a0ec5e6a84@palmer-ri-x1c9a> (raw)
In-Reply-To: <20230404182037.863533-10-sunilvl@ventanamicro.com>
On Tue, 04 Apr 2023 11:20:23 PDT (-0700), sunilvl@ventanamicro.com wrote:
> RHCT is a new table defined for RISC-V to communicate the
> features of the CPU to the OS. Create a new architecture folder
> in drivers/acpi and add RHCT parsing code.
>
> Signed-off-by: Sunil V L <sunilvl@ventanamicro.com>
> Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
> Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
> ---
> arch/riscv/include/asm/acpi.h | 9 ++++
> drivers/acpi/Makefile | 2 +
> drivers/acpi/riscv/Makefile | 2 +
> drivers/acpi/riscv/rhct.c | 83 +++++++++++++++++++++++++++++++++++
> 4 files changed, 96 insertions(+)
> create mode 100644 drivers/acpi/riscv/Makefile
> create mode 100644 drivers/acpi/riscv/rhct.c
>
> diff --git a/arch/riscv/include/asm/acpi.h b/arch/riscv/include/asm/acpi.h
> index 1606dce8992e..2b3e78d5a13b 100644
> --- a/arch/riscv/include/asm/acpi.h
> +++ b/arch/riscv/include/asm/acpi.h
> @@ -61,6 +61,15 @@ static inline void arch_fix_phys_package_id(int num, u32 slot) { }
>
> struct acpi_madt_rintc *acpi_cpu_get_madt_rintc(int cpu);
> u32 get_acpi_id_for_cpu(int cpu);
> +int acpi_get_riscv_isa(struct acpi_table_header *table,
> + unsigned int cpu, const char **isa);
> +#else
> +static inline int acpi_get_riscv_isa(struct acpi_table_header *table,
> + unsigned int cpu, const char **isa)
> +{
> + return -EINVAL;
> +}
> +
> #endif /* CONFIG_ACPI */
>
> #endif /*_ASM_ACPI_H*/
> diff --git a/drivers/acpi/Makefile b/drivers/acpi/Makefile
> index feb36c0b9446..3fc5a0d54f6e 100644
> --- a/drivers/acpi/Makefile
> +++ b/drivers/acpi/Makefile
> @@ -131,3 +131,5 @@ obj-y += dptf/
> obj-$(CONFIG_ARM64) += arm64/
>
> obj-$(CONFIG_ACPI_VIOT) += viot.o
> +
> +obj-$(CONFIG_RISCV) += riscv/
> diff --git a/drivers/acpi/riscv/Makefile b/drivers/acpi/riscv/Makefile
> new file mode 100644
> index 000000000000..8b3b126e0b94
> --- /dev/null
> +++ b/drivers/acpi/riscv/Makefile
> @@ -0,0 +1,2 @@
> +# SPDX-License-Identifier: GPL-2.0-only
> +obj-y += rhct.o
> diff --git a/drivers/acpi/riscv/rhct.c b/drivers/acpi/riscv/rhct.c
> new file mode 100644
> index 000000000000..ea78d906a0fe
> --- /dev/null
> +++ b/drivers/acpi/riscv/rhct.c
> @@ -0,0 +1,83 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2022-2023, Ventana Micro Systems Inc
> + * Author: Sunil V L <sunilvl@ventanamicro.com>
> + *
> + */
> +
> +#define pr_fmt(fmt) "ACPI: RHCT: " fmt
> +
> +#include <linux/acpi.h>
> +
> +static struct acpi_table_header *acpi_get_rhct(void)
> +{
> + static struct acpi_table_header *rhct;
> + acpi_status status;
> +
> + /*
> + * RHCT will be used at runtime on every CPU, so we
> + * don't need to call acpi_put_table() to release the table mapping.
> + */
> + if (!rhct) {
> + status = acpi_get_table(ACPI_SIG_RHCT, 0, &rhct);
> + if (ACPI_FAILURE(status)) {
> + pr_warn_once("No RHCT table found\n");
> + return NULL;
> + }
> + }
> +
> + return rhct;
> +}
> +
> +/*
> + * During early boot, the caller should call acpi_get_table() and pass its pointer to
> + * these functions(and free up later). At run time, since this table can be used
> + * multiple times, NULL may be passed in order to use the cached table.
> + */
> +int acpi_get_riscv_isa(struct acpi_table_header *table, unsigned int cpu, const char **isa)
> +{
> + struct acpi_rhct_node_header *node, *ref_node, *end;
> + u32 size_hdr = sizeof(struct acpi_rhct_node_header);
> + u32 size_hartinfo = sizeof(struct acpi_rhct_hart_info);
> + struct acpi_rhct_hart_info *hart_info;
> + struct acpi_rhct_isa_string *isa_node;
> + struct acpi_table_rhct *rhct;
> + u32 *hart_info_node_offset;
> + u32 acpi_cpu_id = get_acpi_id_for_cpu(cpu);
> +
> + BUG_ON(acpi_disabled);
> +
> + if (!table) {
> + rhct = (struct acpi_table_rhct *)acpi_get_rhct();
> + if (!rhct)
> + return -ENOENT;
> + } else {
> + rhct = (struct acpi_table_rhct *)table;
> + }
> +
> + end = ACPI_ADD_PTR(struct acpi_rhct_node_header, rhct, rhct->header.length);
> +
> + for (node = ACPI_ADD_PTR(struct acpi_rhct_node_header, rhct, rhct->node_offset);
> + node < end;
> + node = ACPI_ADD_PTR(struct acpi_rhct_node_header, node, node->length)) {
> + if (node->type == ACPI_RHCT_NODE_TYPE_HART_INFO) {
> + hart_info = ACPI_ADD_PTR(struct acpi_rhct_hart_info, node, size_hdr);
> + hart_info_node_offset = ACPI_ADD_PTR(u32, hart_info, size_hartinfo);
> + if (acpi_cpu_id != hart_info->uid)
> + continue;
> +
> + for (int i = 0; i < hart_info->num_offsets; i++) {
> + ref_node = ACPI_ADD_PTR(struct acpi_rhct_node_header,
> + rhct, hart_info_node_offset[i]);
> + if (ref_node->type == ACPI_RHCT_NODE_TYPE_ISA_STRING) {
> + isa_node = ACPI_ADD_PTR(struct acpi_rhct_isa_string,
> + ref_node, size_hdr);
> + *isa = isa_node->isa;
> + return 0;
> + }
> + }
> + }
> + }
> +
> + return -1;
> +}
Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2023-04-26 18:45 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-04-04 18:20 [PATCH V4 00/23] Add basic ACPI support for RISC-V Sunil V L
2023-04-04 18:20 ` [PATCH V4 01/23] riscv: move sbi_init() earlier before jump_label_init() Sunil V L
2023-04-04 18:20 ` [PATCH V4 02/23] ACPICA: MADT: Add RISC-V INTC interrupt controller Sunil V L
2023-04-04 18:20 ` [PATCH V4 03/23] ACPICA: Add structure definitions for RISC-V RHCT Sunil V L
2023-04-04 18:20 ` [PATCH V4 04/23] ACPI: tables: Print RINTC information when MADT is parsed Sunil V L
2023-04-04 18:20 ` [PATCH V4 05/23] ACPI: OSL: Make should_use_kmap() 0 for RISC-V Sunil V L
2023-04-26 16:47 ` Björn Töpel
2023-04-27 9:27 ` Sunil V L
2023-04-27 11:24 ` Björn Töpel
2023-04-04 18:20 ` [PATCH V4 06/23] RISC-V: Add support to build the ACPI core Sunil V L
2023-04-26 18:44 ` Palmer Dabbelt
2023-04-04 18:20 ` [PATCH V4 07/23] ACPI: processor_core: RISC-V: Enable mapping processor to the hartid Sunil V L
2023-04-04 18:20 ` [PATCH V4 08/23] RISC-V: ACPI: Cache and retrieve the RINTC structure Sunil V L
2023-04-04 20:14 ` Conor Dooley
2023-04-05 15:17 ` Andrew Jones
2023-04-06 3:46 ` Sunil V L
2023-04-26 18:45 ` Palmer Dabbelt
2023-04-27 9:22 ` Sunil V L
2023-04-27 10:25 ` Andrew Jones
2023-04-27 10:52 ` Sunil V L
2023-04-27 13:13 ` Andrew Jones
2023-04-04 18:20 ` [PATCH V4 09/23] drivers/acpi: RISC-V: Add RHCT related code Sunil V L
2023-04-26 18:45 ` Palmer Dabbelt [this message]
2023-04-04 18:20 ` [PATCH V4 10/23] RISC-V: smpboot: Create wrapper smp_setup() Sunil V L
2023-04-26 18:45 ` Palmer Dabbelt
2023-04-04 18:20 ` [PATCH V4 11/23] RISC-V: smpboot: Add ACPI support in smp_setup() Sunil V L
2023-04-05 14:58 ` Andrew Jones
2023-04-04 18:20 ` [PATCH V4 12/23] RISC-V: cpufeature: Avoid calling riscv_of_processor_hartid() Sunil V L
2023-04-04 20:46 ` Conor Dooley
2023-04-04 18:20 ` [PATCH V4 13/23] RISC-V: cpufeature: Add ACPI support in riscv_fill_hwcap() Sunil V L
2023-04-04 20:57 ` Conor Dooley
2023-04-05 13:35 ` Sunil V L
2023-04-05 14:31 ` Conor Dooley
2023-04-05 15:37 ` Andrew Jones
2023-04-29 10:31 ` Conor Dooley
2023-05-02 1:28 ` Sunil V L
2023-04-04 18:20 ` [PATCH V4 14/23] RISC-V: cpu: Enable cpuinfo for ACPI systems Sunil V L
2023-04-04 21:04 ` Conor Dooley
2023-04-04 18:20 ` [PATCH V4 15/23] irqchip/riscv-intc: Add ACPI support Sunil V L
2023-04-05 15:48 ` Andrew Jones
2023-04-06 3:47 ` Sunil V L
2023-04-04 18:20 ` [PATCH V4 16/23] clocksource/timer-riscv: Refactor riscv_timer_init_dt() Sunil V L
2023-04-04 21:25 ` Conor Dooley
2023-04-05 10:55 ` Sunil V L
2023-04-04 18:20 ` [PATCH V4 17/23] clocksource/timer-riscv: Add ACPI support Sunil V L
2023-04-04 21:27 ` Conor Dooley
2023-04-04 18:20 ` [PATCH V4 18/23] RISC-V: time.c: Add ACPI support for time_init() Sunil V L
2023-04-04 18:20 ` [PATCH V4 19/23] RISC-V: Add ACPI initialization in setup_arch() Sunil V L
2023-04-04 21:38 ` Conor Dooley
2023-04-05 15:11 ` Sunil V L
2023-04-05 15:30 ` Conor Dooley
2023-04-04 18:20 ` [PATCH V4 20/23] RISC-V: Enable ACPI in defconfig Sunil V L
2023-04-04 21:43 ` Conor Dooley
2023-04-05 10:58 ` Sunil V L
2023-04-04 18:20 ` [PATCH V4 21/23] MAINTAINERS: Add entry for drivers/acpi/riscv Sunil V L
2023-04-04 18:20 ` [PATCH V4 22/23] platform/surface: Disable for RISC-V Sunil V L
2023-04-05 4:19 ` Jessica Clarke
2023-04-05 11:29 ` Sunil V L
2023-04-05 9:33 ` Maximilian Luz
2023-04-05 11:11 ` Sunil V L
2023-04-05 11:35 ` Maximilian Luz
2023-04-04 18:20 ` [PATCH V4 23/23] crypto: hisilicon/qm: Workaround to enable build with RISC-V clang Sunil V L
2023-04-04 21:59 ` Conor Dooley
2023-04-05 10:46 ` Sunil V L
2023-04-05 8:16 ` Arnd Bergmann
2023-04-11 11:42 ` Weili Qian
2023-04-19 14:34 ` Arnd Bergmann
2023-04-04 18:42 ` [PATCH V4 00/23] Add basic ACPI support for RISC-V Conor Dooley
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=mhng-c1242642-931b-4585-8c65-02a0ec5e6a84@palmer-ri-x1c9a \
--to=palmer@dabbelt.com \
--cc=ajones@ventanamicro.com \
--cc=aou@eecs.berkeley.edu \
--cc=corbet@lwn.net \
--cc=daniel.lezcano@linaro.org \
--cc=davem@davemloft.net \
--cc=hdegoede@redhat.com \
--cc=herbert@gondor.apana.org.au \
--cc=lenb@kernel.org \
--cc=linux-acpi@vger.kernel.org \
--cc=linux-crypto@vger.kernel.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=llvm@lists.linux.dev \
--cc=luzmaximilian@gmail.com \
--cc=markgross@kernel.org \
--cc=maz@kernel.org \
--cc=nathan@kernel.org \
--cc=ndesaulniers@google.com \
--cc=paul.walmsley@sifive.com \
--cc=platform-driver-x86@vger.kernel.org \
--cc=qianweili@huawei.com \
--cc=rafael.j.wysocki@intel.com \
--cc=rafael@kernel.org \
--cc=sunilvl@ventanamicro.com \
--cc=tglx@linutronix.de \
--cc=trix@redhat.com \
--cc=wangzhou1@hisilicon.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).