[PATCH 0/3] RISC-V: Export Zba, Zbb to usermode via hwprobe

[PATCH 0/3] RISC-V: Export Zba, Zbb to usermode via hwprobe

[Evan Green]

This change detects the presence of Zba and Zbb extensions and exports
them per-hart to userspace via the hwprobe mechanism. Glibc can then use
these in setting up hwcaps-based library search paths.

There's a little bit of extra housekeeping here: the first change adds
Zba to the set of extensions the kernel recognizes, and the second
change starts tracking ISA features per-hart (in addition to the ANDed
mask of features across all harts which the kernel uses to make
decisions). Now that we track the ISA information per-hart, we could
even fix up /proc/cpuinfo to accurately report extension per-hart,
though I've left that out of this series for now.


Evan Green (3):
  RISC-V: Add Zba extension probing
  RISC-V: Track ISA extensions per hart
  RISC-V: hwprobe: Expose Zba and Zbb

 Documentation/riscv/hwprobe.rst       |  7 +++++
 arch/riscv/include/asm/cpufeature.h   | 10 +++++++
 arch/riscv/include/asm/hwcap.h        |  1 +
 arch/riscv/include/uapi/asm/hwprobe.h |  2 ++
 arch/riscv/kernel/cpu.c               |  1 +
 arch/riscv/kernel/cpufeature.c        | 19 ++++++++----
 arch/riscv/kernel/sys_riscv.c         | 43 ++++++++++++++++++++++-----
 7 files changed, 70 insertions(+), 13 deletions(-)

-- 
2.25.1


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[PATCH 1/3] RISC-V: Add Zba extension probing

[Evan Green]

Add the Zba address bit manipulation extension into those the kernel is
aware of and maintains in its riscv_isa bitmap.

Signed-off-by: Evan Green <evan@rivosinc.com>
---

 arch/riscv/include/asm/hwcap.h | 1 +
 arch/riscv/kernel/cpu.c        | 1 +
 arch/riscv/kernel/cpufeature.c | 1 +
 3 files changed, 3 insertions(+)

diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
index 9af793970855..fa36db9281ab 100644
--- a/arch/riscv/include/asm/hwcap.h
+++ b/arch/riscv/include/asm/hwcap.h
@@ -44,6 +44,7 @@
 #define RISCV_ISA_EXT_ZIHINTPAUSE	32
 #define RISCV_ISA_EXT_SVNAPOT		33
 #define RISCV_ISA_EXT_ZICBOZ		34
+#define RISCV_ISA_EXT_ZBA		35
 
 #define RISCV_ISA_EXT_MAX		64
 #define RISCV_ISA_EXT_NAME_LEN_MAX	32
diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
index 3df38052dcbd..2f85b1656557 100644
--- a/arch/riscv/kernel/cpu.c
+++ b/arch/riscv/kernel/cpu.c
@@ -184,6 +184,7 @@ static struct riscv_isa_ext_data isa_ext_arr[] = {
 	__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
 	__RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
 	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
+	__RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
 	__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
 	__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
 	__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 52585e088873..1a80474e308e 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -233,6 +233,7 @@ void __init riscv_fill_hwcap(void)
 				SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
 				SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT);
 				SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
+				SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA);
 				SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB);
 				SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
 				SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ);
-- 
2.25.1


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[PATCH 2/3] RISC-V: Track ISA extensions per hart

[Evan Green]

The kernel maintains a mask of ISA extensions ANDed together across all
harts. Let's also keep a bitmap of ISA extensions for each CPU. Although
the kernel is currently unlikely to enable a feature that exists only on
some CPUs, we want the ability to report asymmetric CPU extensions
accurately to usermode.

Note that riscv_fill_hwcaps() runs before the per_cpu_offsets are built,
which is why I've used a [NR_CPUS] array rather than per_cpu() data.

Signed-off-by: Evan Green <evan@rivosinc.com>
---

 arch/riscv/include/asm/cpufeature.h | 10 ++++++++++
 arch/riscv/kernel/cpufeature.c      | 18 ++++++++++++------
 2 files changed, 22 insertions(+), 6 deletions(-)

diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
index 808d5403f2ac..23fed53b8815 100644
--- a/arch/riscv/include/asm/cpufeature.h
+++ b/arch/riscv/include/asm/cpufeature.h
@@ -6,6 +6,9 @@
 #ifndef _ASM_CPUFEATURE_H
 #define _ASM_CPUFEATURE_H
 
+#include <linux/bitmap.h>
+#include <asm/hwcap.h>
+
 /*
  * These are probed via a device_initcall(), via either the SBI or directly
  * from the corresponding CSRs.
@@ -16,8 +19,15 @@ struct riscv_cpuinfo {
 	unsigned long mimpid;
 };
 
+struct riscv_isainfo {
+	DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX);
+};
+
 DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
 
 DECLARE_PER_CPU(long, misaligned_access_speed);
 
+/* Per-cpu ISA extensions. */
+extern struct riscv_isainfo hart_isa[NR_CPUS];
+
 #endif
diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
index 1a80474e308e..0e9d66580478 100644
--- a/arch/riscv/kernel/cpufeature.c
+++ b/arch/riscv/kernel/cpufeature.c
@@ -14,6 +14,7 @@
 #include <linux/of.h>
 #include <asm/alternative.h>
 #include <asm/cacheflush.h>
+#include <asm/cpufeature.h>
 #include <asm/hwcap.h>
 #include <asm/patch.h>
 #include <asm/processor.h>
@@ -25,6 +26,9 @@ unsigned long elf_hwcap __read_mostly;
 /* Host ISA bitmap */
 static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
 
+/* Per-cpu ISA extensions. */
+struct riscv_isainfo hart_isa[NR_CPUS];
+
 /* Performance information */
 DEFINE_PER_CPU(long, misaligned_access_speed);
 
@@ -112,14 +116,17 @@ void __init riscv_fill_hwcap(void)
 	bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
 
 	for_each_of_cpu_node(node) {
+		struct riscv_isainfo *isainfo;
 		unsigned long this_hwcap = 0;
-		DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
 		const char *temp;
+		unsigned int cpu_id;
 
 		rc = riscv_of_processor_hartid(node, &hartid);
 		if (rc < 0)
 			continue;
 
+		cpu_id = riscv_hartid_to_cpuid(hartid);
+		isainfo = &hart_isa[cpu_id];
 		if (of_property_read_string(node, "riscv,isa", &isa)) {
 			pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
 			continue;
@@ -136,7 +143,6 @@ void __init riscv_fill_hwcap(void)
 		/* The riscv,isa DT property must start with rv64 or rv32 */
 		if (temp == isa)
 			continue;
-		bitmap_zero(this_isa, RISCV_ISA_EXT_MAX);
 		for (; *isa; ++isa) {
 			const char *ext = isa++;
 			const char *ext_end = isa;
@@ -214,7 +220,7 @@ void __init riscv_fill_hwcap(void)
 				if ((ext_end - ext == sizeof(name) - 1) &&	\
 				     !memcmp(ext, name, sizeof(name) - 1) &&	\
 				     riscv_isa_extension_check(bit))		\
-					set_bit(bit, this_isa);			\
+					set_bit(bit, isainfo->isa);		\
 			} while (false)						\
 
 			if (unlikely(ext_err))
@@ -224,7 +230,7 @@ void __init riscv_fill_hwcap(void)
 
 				if (riscv_isa_extension_check(nr)) {
 					this_hwcap |= isa2hwcap[nr];
-					set_bit(nr, this_isa);
+					set_bit(nr, isainfo->isa);
 				}
 			} else {
 				/* sorted alphabetically */
@@ -253,9 +259,9 @@ void __init riscv_fill_hwcap(void)
 			elf_hwcap = this_hwcap;
 
 		if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
-			bitmap_copy(riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
+			bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
 		else
-			bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
+			bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
 	}
 
 	/* We don't support systems with F but without D, so mask those out
-- 
2.25.1


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[PATCH 3/3] RISC-V: hwprobe: Expose Zba and Zbb

[Evan Green]

Add two new bits to the IMA_EXT_0 key for ZBA and ZBB extensions. These
are accurately reported per CPU.

Signed-off-by: Evan Green <evan@rivosinc.com>

---

 Documentation/riscv/hwprobe.rst       |  7 +++++
 arch/riscv/include/uapi/asm/hwprobe.h |  2 ++
 arch/riscv/kernel/sys_riscv.c         | 43 ++++++++++++++++++++++-----
 3 files changed, 45 insertions(+), 7 deletions(-)

diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst
index 9f0dd62dcb5d..21f444a38359 100644
--- a/Documentation/riscv/hwprobe.rst
+++ b/Documentation/riscv/hwprobe.rst
@@ -64,6 +64,13 @@ The following keys are defined:
   * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined
     by version 2.2 of the RISC-V ISA manual.
 
+  * :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is
+       supported, as defined in version 1.0 of the Bit-Manipulation ISA
+       extensions.
+
+  * :c:macro:`RISCV_HWPROBE_IMA_ZBB`: The Zbb extension is supporte, as defined
+       in version 1.0 of the Bit-Manipulation ISA extensions.
+
 * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
   information about the selected set of processors.
 
diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
index 8d745a4ad8a2..ef3b060d4e8d 100644
--- a/arch/riscv/include/uapi/asm/hwprobe.h
+++ b/arch/riscv/include/uapi/asm/hwprobe.h
@@ -25,6 +25,8 @@ struct riscv_hwprobe {
 #define RISCV_HWPROBE_KEY_IMA_EXT_0	4
 #define		RISCV_HWPROBE_IMA_FD		(1 << 0)
 #define		RISCV_HWPROBE_IMA_C		(1 << 1)
+#define		RISCV_HWPROBE_EXT_ZBA		(1 << 2)
+#define		RISCV_HWPROBE_EXT_ZBB		(1 << 3)
 #define RISCV_HWPROBE_KEY_CPUPERF_0	5
 #define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)
 #define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)
diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
index 5db29683ebee..adfcb6b64db7 100644
--- a/arch/riscv/kernel/sys_riscv.c
+++ b/arch/riscv/kernel/sys_riscv.c
@@ -121,6 +121,41 @@ static void hwprobe_arch_id(struct riscv_hwprobe *pair,
 	pair->value = id;
 }
 
+static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
+			     const struct cpumask *cpus)
+{
+	int cpu;
+	u64 missing = 0;
+
+	pair->value = 0;
+	if (has_fpu())
+		pair->value |= RISCV_HWPROBE_IMA_FD;
+
+	if (riscv_isa_extension_available(NULL, c))
+		pair->value |= RISCV_HWPROBE_IMA_C;
+
+	/*
+	 * Loop through and record extensions that 1) anyone has, and 2) anyone
+	 * doesn't have.
+	 */
+	for_each_cpu(cpu, cpus) {
+		struct riscv_isainfo *isainfo = &hart_isa[cpu];
+
+		if (riscv_isa_extension_available(isainfo->isa, ZBA))
+			pair->value |= RISCV_HWPROBE_EXT_ZBA;
+		else
+			missing |= RISCV_HWPROBE_EXT_ZBA;
+
+		if (riscv_isa_extension_available(isainfo->isa, ZBB))
+			pair->value |= RISCV_HWPROBE_EXT_ZBB;
+		else
+			missing |= RISCV_HWPROBE_EXT_ZBB;
+	}
+
+	/* Now turn off reporting features if any CPU is missing it. */
+	pair->value &= ~missing;
+}
+
 static u64 hwprobe_misaligned(const struct cpumask *cpus)
 {
 	int cpu;
@@ -164,13 +199,7 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
 		break;
 
 	case RISCV_HWPROBE_KEY_IMA_EXT_0:
-		pair->value = 0;
-		if (has_fpu())
-			pair->value |= RISCV_HWPROBE_IMA_FD;
-
-		if (riscv_isa_extension_available(NULL, c))
-			pair->value |= RISCV_HWPROBE_IMA_C;
-
+		hwprobe_isa_ext0(pair, cpus);
 		break;
 
 	case RISCV_HWPROBE_KEY_CPUPERF_0:
-- 
2.25.1


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Re: [PATCH 0/3] RISC-V: Export Zba, Zbb to usermode via hwprobe

[Andrew Jones]

On Fri, Apr 28, 2023 at 12:06:05PM -0700, Evan Green wrote:
> 
> This change detects the presence of Zba and Zbb extensions and exports
> them per-hart to userspace via the hwprobe mechanism. Glibc can then use
> these in setting up hwcaps-based library search paths.
> 
> There's a little bit of extra housekeeping here: the first change adds
> Zba to the set of extensions the kernel recognizes, and the second
> change starts tracking ISA features per-hart (in addition to the ANDed
> mask of features across all harts which the kernel uses to make
> decisions). Now that we track the ISA information per-hart, we could
> even fix up /proc/cpuinfo to accurately report extension per-hart,
> though I've left that out of this series for now.
> 
> 
> Evan Green (3):
>   RISC-V: Add Zba extension probing
>   RISC-V: Track ISA extensions per hart
>   RISC-V: hwprobe: Expose Zba and Zbb
> 
>  Documentation/riscv/hwprobe.rst       |  7 +++++
>  arch/riscv/include/asm/cpufeature.h   | 10 +++++++
>  arch/riscv/include/asm/hwcap.h        |  1 +
>  arch/riscv/include/uapi/asm/hwprobe.h |  2 ++
>  arch/riscv/kernel/cpu.c               |  1 +
>  arch/riscv/kernel/cpufeature.c        | 19 ++++++++----
>  arch/riscv/kernel/sys_riscv.c         | 43 ++++++++++++++++++++++-----
>  7 files changed, 70 insertions(+), 13 deletions(-)
> 
> -- 
> 2.25.1
>

For the series

Reviewed-by: Andrew Jones <ajones@ventanamicro.com>

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Re: [PATCH 2/3] RISC-V: Track ISA extensions per hart

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 868 bytes --]

On Fri, Apr 28, 2023 at 12:06:07PM -0700, Evan Green wrote:

> @@ -112,14 +116,17 @@ void __init riscv_fill_hwcap(void)
>  	bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
>  
>  	for_each_of_cpu_node(node) {
> +		struct riscv_isainfo *isainfo;
>  		unsigned long this_hwcap = 0;
> -		DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
>  		const char *temp;
> +		unsigned int cpu_id;
>  
>  		rc = riscv_of_processor_hartid(node, &hartid);
>  		if (rc < 0)
>  			continue;
>  
> +		cpu_id = riscv_hartid_to_cpuid(hartid);
> +		isainfo = &hart_isa[cpu_id];
>  		if (of_property_read_string(node, "riscv,isa", &isa)) {

Would you mind adding a blank line above the if statement please?
Otherwise,
Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

Thanks,
Conor.

>  			pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
>  			continue;

[-- Attachment #1.2: signature.asc --]
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[-- Attachment #2: Type: text/plain, Size: 161 bytes --]

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Re: [PATCH 3/3] RISC-V: hwprobe: Expose Zba and Zbb

[Conor Dooley]

[-- Attachment #1.1: Type: text/plain, Size: 4015 bytes --]

On Fri, Apr 28, 2023 at 12:06:08PM -0700, Evan Green wrote:
> Add two new bits to the IMA_EXT_0 key for ZBA and ZBB extensions. These
> are accurately reported per CPU.
> 
> Signed-off-by: Evan Green <evan@rivosinc.com>
> 
> ---
> 
>  Documentation/riscv/hwprobe.rst       |  7 +++++
>  arch/riscv/include/uapi/asm/hwprobe.h |  2 ++
>  arch/riscv/kernel/sys_riscv.c         | 43 ++++++++++++++++++++++-----
>  3 files changed, 45 insertions(+), 7 deletions(-)
> 
> diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst
> index 9f0dd62dcb5d..21f444a38359 100644
> --- a/Documentation/riscv/hwprobe.rst
> +++ b/Documentation/riscv/hwprobe.rst
> @@ -64,6 +64,13 @@ The following keys are defined:
>    * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined
>      by version 2.2 of the RISC-V ISA manual.
>  
> +  * :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is
> +       supported, as defined in version 1.0 of the Bit-Manipulation ISA
> +       extensions.
> +
> +  * :c:macro:`RISCV_HWPROBE_IMA_ZBB`: The Zbb extension is supporte, as defined

Why is one EXT_ZBA and the other is IMA_ZBB? You do not use IMA below,
so I assume this is a copy-paste mistake.

Also, s/supporte/supported.

Otherwise, looks fine.
Cheers,
Conor.

> +       in version 1.0 of the Bit-Manipulation ISA extensions.
> +
>  * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
>    information about the selected set of processors.
>  
> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
> index 8d745a4ad8a2..ef3b060d4e8d 100644
> --- a/arch/riscv/include/uapi/asm/hwprobe.h
> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
> @@ -25,6 +25,8 @@ struct riscv_hwprobe {
>  #define RISCV_HWPROBE_KEY_IMA_EXT_0	4
>  #define		RISCV_HWPROBE_IMA_FD		(1 << 0)
>  #define		RISCV_HWPROBE_IMA_C		(1 << 1)
> +#define		RISCV_HWPROBE_EXT_ZBA		(1 << 2)
> +#define		RISCV_HWPROBE_EXT_ZBB		(1 << 3)
>  #define RISCV_HWPROBE_KEY_CPUPERF_0	5
>  #define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)
>  #define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)
> diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
> index 5db29683ebee..adfcb6b64db7 100644
> --- a/arch/riscv/kernel/sys_riscv.c
> +++ b/arch/riscv/kernel/sys_riscv.c
> @@ -121,6 +121,41 @@ static void hwprobe_arch_id(struct riscv_hwprobe *pair,
>  	pair->value = id;
>  }
>  
> +static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
> +			     const struct cpumask *cpus)
> +{
> +	int cpu;
> +	u64 missing = 0;
> +
> +	pair->value = 0;
> +	if (has_fpu())
> +		pair->value |= RISCV_HWPROBE_IMA_FD;
> +
> +	if (riscv_isa_extension_available(NULL, c))
> +		pair->value |= RISCV_HWPROBE_IMA_C;
> +
> +	/*
> +	 * Loop through and record extensions that 1) anyone has, and 2) anyone
> +	 * doesn't have.
> +	 */
> +	for_each_cpu(cpu, cpus) {
> +		struct riscv_isainfo *isainfo = &hart_isa[cpu];
> +
> +		if (riscv_isa_extension_available(isainfo->isa, ZBA))
> +			pair->value |= RISCV_HWPROBE_EXT_ZBA;
> +		else
> +			missing |= RISCV_HWPROBE_EXT_ZBA;
> +
> +		if (riscv_isa_extension_available(isainfo->isa, ZBB))
> +			pair->value |= RISCV_HWPROBE_EXT_ZBB;
> +		else
> +			missing |= RISCV_HWPROBE_EXT_ZBB;
> +	}
> +
> +	/* Now turn off reporting features if any CPU is missing it. */
> +	pair->value &= ~missing;
> +}
> +
>  static u64 hwprobe_misaligned(const struct cpumask *cpus)
>  {
>  	int cpu;
> @@ -164,13 +199,7 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
>  		break;
>  
>  	case RISCV_HWPROBE_KEY_IMA_EXT_0:
> -		pair->value = 0;
> -		if (has_fpu())
> -			pair->value |= RISCV_HWPROBE_IMA_FD;
> -
> -		if (riscv_isa_extension_available(NULL, c))
> -			pair->value |= RISCV_HWPROBE_IMA_C;
> -
> +		hwprobe_isa_ext0(pair, cpus);
>  		break;
>  
>  	case RISCV_HWPROBE_KEY_CPUPERF_0:
> -- 
> 2.25.1
> 

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Re: [PATCH 1/3] RISC-V: Add Zba extension probing

[Conor Dooley]

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Reviewed-by: Conor Dooley <conor.dooley@microchip.com>

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Re: [PATCH 1/3] RISC-V: Add Zba extension probing

[Palmer Dabbelt]

On Fri, 28 Apr 2023 12:06:06 PDT (-0700), Evan Green wrote:
> Add the Zba address bit manipulation extension into those the kernel is
> aware of and maintains in its riscv_isa bitmap.
>
> Signed-off-by: Evan Green <evan@rivosinc.com>
> ---
>
>  arch/riscv/include/asm/hwcap.h | 1 +
>  arch/riscv/kernel/cpu.c        | 1 +
>  arch/riscv/kernel/cpufeature.c | 1 +
>  3 files changed, 3 insertions(+)
>
> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h
> index 9af793970855..fa36db9281ab 100644
> --- a/arch/riscv/include/asm/hwcap.h
> +++ b/arch/riscv/include/asm/hwcap.h
> @@ -44,6 +44,7 @@
>  #define RISCV_ISA_EXT_ZIHINTPAUSE	32
>  #define RISCV_ISA_EXT_SVNAPOT		33
>  #define RISCV_ISA_EXT_ZICBOZ		34
> +#define RISCV_ISA_EXT_ZBA		35
>
>  #define RISCV_ISA_EXT_MAX		64
>  #define RISCV_ISA_EXT_NAME_LEN_MAX	32
> diff --git a/arch/riscv/kernel/cpu.c b/arch/riscv/kernel/cpu.c
> index 3df38052dcbd..2f85b1656557 100644
> --- a/arch/riscv/kernel/cpu.c
> +++ b/arch/riscv/kernel/cpu.c
> @@ -184,6 +184,7 @@ static struct riscv_isa_ext_data isa_ext_arr[] = {
>  	__RISCV_ISA_EXT_DATA(zicbom, RISCV_ISA_EXT_ZICBOM),
>  	__RISCV_ISA_EXT_DATA(zicboz, RISCV_ISA_EXT_ZICBOZ),
>  	__RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE),
> +	__RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA),
>  	__RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB),
>  	__RISCV_ISA_EXT_DATA(sscofpmf, RISCV_ISA_EXT_SSCOFPMF),
>  	__RISCV_ISA_EXT_DATA(sstc, RISCV_ISA_EXT_SSTC),
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 52585e088873..1a80474e308e 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -233,6 +233,7 @@ void __init riscv_fill_hwcap(void)
>  				SET_ISA_EXT_MAP("svinval", RISCV_ISA_EXT_SVINVAL);
>  				SET_ISA_EXT_MAP("svnapot", RISCV_ISA_EXT_SVNAPOT);
>  				SET_ISA_EXT_MAP("svpbmt", RISCV_ISA_EXT_SVPBMT);
> +				SET_ISA_EXT_MAP("zba", RISCV_ISA_EXT_ZBA);
>  				SET_ISA_EXT_MAP("zbb", RISCV_ISA_EXT_ZBB);
>  				SET_ISA_EXT_MAP("zicbom", RISCV_ISA_EXT_ZICBOM);
>  				SET_ISA_EXT_MAP("zicboz", RISCV_ISA_EXT_ZICBOZ);

Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>

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Re: [PATCH 2/3] RISC-V: Track ISA extensions per hart

[Palmer Dabbelt]

On Fri, 28 Apr 2023 12:06:07 PDT (-0700), Evan Green wrote:
> The kernel maintains a mask of ISA extensions ANDed together across all
> harts. Let's also keep a bitmap of ISA extensions for each CPU. Although
> the kernel is currently unlikely to enable a feature that exists only on
> some CPUs, we want the ability to report asymmetric CPU extensions
> accurately to usermode.
>
> Note that riscv_fill_hwcaps() runs before the per_cpu_offsets are built,
> which is why I've used a [NR_CPUS] array rather than per_cpu() data.
>
> Signed-off-by: Evan Green <evan@rivosinc.com>
> ---
>
>  arch/riscv/include/asm/cpufeature.h | 10 ++++++++++
>  arch/riscv/kernel/cpufeature.c      | 18 ++++++++++++------
>  2 files changed, 22 insertions(+), 6 deletions(-)
>
> diff --git a/arch/riscv/include/asm/cpufeature.h b/arch/riscv/include/asm/cpufeature.h
> index 808d5403f2ac..23fed53b8815 100644
> --- a/arch/riscv/include/asm/cpufeature.h
> +++ b/arch/riscv/include/asm/cpufeature.h
> @@ -6,6 +6,9 @@
>  #ifndef _ASM_CPUFEATURE_H
>  #define _ASM_CPUFEATURE_H
>
> +#include <linux/bitmap.h>
> +#include <asm/hwcap.h>
> +
>  /*
>   * These are probed via a device_initcall(), via either the SBI or directly
>   * from the corresponding CSRs.
> @@ -16,8 +19,15 @@ struct riscv_cpuinfo {
>  	unsigned long mimpid;
>  };
>
> +struct riscv_isainfo {
> +	DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX);
> +};
> +
>  DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
>
>  DECLARE_PER_CPU(long, misaligned_access_speed);
>
> +/* Per-cpu ISA extensions. */
> +extern struct riscv_isainfo hart_isa[NR_CPUS];
> +
>  #endif
> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c
> index 1a80474e308e..0e9d66580478 100644
> --- a/arch/riscv/kernel/cpufeature.c
> +++ b/arch/riscv/kernel/cpufeature.c
> @@ -14,6 +14,7 @@
>  #include <linux/of.h>
>  #include <asm/alternative.h>
>  #include <asm/cacheflush.h>
> +#include <asm/cpufeature.h>
>  #include <asm/hwcap.h>
>  #include <asm/patch.h>
>  #include <asm/processor.h>
> @@ -25,6 +26,9 @@ unsigned long elf_hwcap __read_mostly;
>  /* Host ISA bitmap */
>  static DECLARE_BITMAP(riscv_isa, RISCV_ISA_EXT_MAX) __read_mostly;
>
> +/* Per-cpu ISA extensions. */
> +struct riscv_isainfo hart_isa[NR_CPUS];
> +
>  /* Performance information */
>  DEFINE_PER_CPU(long, misaligned_access_speed);
>
> @@ -112,14 +116,17 @@ void __init riscv_fill_hwcap(void)
>  	bitmap_zero(riscv_isa, RISCV_ISA_EXT_MAX);
>
>  	for_each_of_cpu_node(node) {
> +		struct riscv_isainfo *isainfo;
>  		unsigned long this_hwcap = 0;
> -		DECLARE_BITMAP(this_isa, RISCV_ISA_EXT_MAX);
>  		const char *temp;
> +		unsigned int cpu_id;
>
>  		rc = riscv_of_processor_hartid(node, &hartid);
>  		if (rc < 0)
>  			continue;
>
> +		cpu_id = riscv_hartid_to_cpuid(hartid);
> +		isainfo = &hart_isa[cpu_id];
>  		if (of_property_read_string(node, "riscv,isa", &isa)) {
>  			pr_warn("Unable to find \"riscv,isa\" devicetree entry\n");
>  			continue;
> @@ -136,7 +143,6 @@ void __init riscv_fill_hwcap(void)
>  		/* The riscv,isa DT property must start with rv64 or rv32 */
>  		if (temp == isa)
>  			continue;
> -		bitmap_zero(this_isa, RISCV_ISA_EXT_MAX);
>  		for (; *isa; ++isa) {
>  			const char *ext = isa++;
>  			const char *ext_end = isa;
> @@ -214,7 +220,7 @@ void __init riscv_fill_hwcap(void)
>  				if ((ext_end - ext == sizeof(name) - 1) &&	\
>  				     !memcmp(ext, name, sizeof(name) - 1) &&	\
>  				     riscv_isa_extension_check(bit))		\
> -					set_bit(bit, this_isa);			\
> +					set_bit(bit, isainfo->isa);		\
>  			} while (false)						\
>
>  			if (unlikely(ext_err))
> @@ -224,7 +230,7 @@ void __init riscv_fill_hwcap(void)
>
>  				if (riscv_isa_extension_check(nr)) {
>  					this_hwcap |= isa2hwcap[nr];
> -					set_bit(nr, this_isa);
> +					set_bit(nr, isainfo->isa);
>  				}
>  			} else {
>  				/* sorted alphabetically */
> @@ -253,9 +259,9 @@ void __init riscv_fill_hwcap(void)
>  			elf_hwcap = this_hwcap;
>
>  		if (bitmap_empty(riscv_isa, RISCV_ISA_EXT_MAX))
> -			bitmap_copy(riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
> +			bitmap_copy(riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
>  		else
> -			bitmap_and(riscv_isa, riscv_isa, this_isa, RISCV_ISA_EXT_MAX);
> +			bitmap_and(riscv_isa, riscv_isa, isainfo->isa, RISCV_ISA_EXT_MAX);
>  	}
>
>  	/* We don't support systems with F but without D, so mask those out

Reviewed-by: Palmer Dabbelt <palmer@rivosinc.com>

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Re: [PATCH 3/3] RISC-V: hwprobe: Expose Zba and Zbb

[Palmer Dabbelt]

On Sat, 29 Apr 2023 06:40:51 PDT (-0700), Conor Dooley wrote:
> On Fri, Apr 28, 2023 at 12:06:08PM -0700, Evan Green wrote:
>> Add two new bits to the IMA_EXT_0 key for ZBA and ZBB extensions. These
>> are accurately reported per CPU.
>> 
>> Signed-off-by: Evan Green <evan@rivosinc.com>
>> 
>> ---
>> 
>>  Documentation/riscv/hwprobe.rst       |  7 +++++
>>  arch/riscv/include/uapi/asm/hwprobe.h |  2 ++
>>  arch/riscv/kernel/sys_riscv.c         | 43 ++++++++++++++++++++++-----
>>  3 files changed, 45 insertions(+), 7 deletions(-)
>> 
>> diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst
>> index 9f0dd62dcb5d..21f444a38359 100644
>> --- a/Documentation/riscv/hwprobe.rst
>> +++ b/Documentation/riscv/hwprobe.rst
>> @@ -64,6 +64,13 @@ The following keys are defined:
>>    * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined
>>      by version 2.2 of the RISC-V ISA manual.
>>  
>> +  * :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is
>> +       supported, as defined in version 1.0 of the Bit-Manipulation ISA
>> +       extensions.
>> +
>> +  * :c:macro:`RISCV_HWPROBE_IMA_ZBB`: The Zbb extension is supporte, as defined
>
> Why is one EXT_ZBA and the other is IMA_ZBB? You do not use IMA below,
> so I assume this is a copy-paste mistake.

Looks like it.  Either way this was too late for the current merge 
window, so no big deal.

>
> Also, s/supporte/supported.
>
> Otherwise, looks fine.
> Cheers,
> Conor.
>
>> +       in version 1.0 of the Bit-Manipulation ISA extensions.
>> +
>>  * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance
>>    information about the selected set of processors.
>>  
>> diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h
>> index 8d745a4ad8a2..ef3b060d4e8d 100644
>> --- a/arch/riscv/include/uapi/asm/hwprobe.h
>> +++ b/arch/riscv/include/uapi/asm/hwprobe.h
>> @@ -25,6 +25,8 @@ struct riscv_hwprobe {
>>  #define RISCV_HWPROBE_KEY_IMA_EXT_0	4
>>  #define		RISCV_HWPROBE_IMA_FD		(1 << 0)
>>  #define		RISCV_HWPROBE_IMA_C		(1 << 1)
>> +#define		RISCV_HWPROBE_EXT_ZBA		(1 << 2)
>> +#define		RISCV_HWPROBE_EXT_ZBB		(1 << 3)
>>  #define RISCV_HWPROBE_KEY_CPUPERF_0	5
>>  #define		RISCV_HWPROBE_MISALIGNED_UNKNOWN	(0 << 0)
>>  #define		RISCV_HWPROBE_MISALIGNED_EMULATED	(1 << 0)
>> diff --git a/arch/riscv/kernel/sys_riscv.c b/arch/riscv/kernel/sys_riscv.c
>> index 5db29683ebee..adfcb6b64db7 100644
>> --- a/arch/riscv/kernel/sys_riscv.c
>> +++ b/arch/riscv/kernel/sys_riscv.c
>> @@ -121,6 +121,41 @@ static void hwprobe_arch_id(struct riscv_hwprobe *pair,
>>  	pair->value = id;
>>  }
>>  
>> +static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
>> +			     const struct cpumask *cpus)
>> +{
>> +	int cpu;
>> +	u64 missing = 0;
>> +
>> +	pair->value = 0;
>> +	if (has_fpu())
>> +		pair->value |= RISCV_HWPROBE_IMA_FD;
>> +
>> +	if (riscv_isa_extension_available(NULL, c))
>> +		pair->value |= RISCV_HWPROBE_IMA_C;
>> +
>> +	/*
>> +	 * Loop through and record extensions that 1) anyone has, and 2) anyone
>> +	 * doesn't have.
>> +	 */
>> +	for_each_cpu(cpu, cpus) {
>> +		struct riscv_isainfo *isainfo = &hart_isa[cpu];
>> +
>> +		if (riscv_isa_extension_available(isainfo->isa, ZBA))
>> +			pair->value |= RISCV_HWPROBE_EXT_ZBA;
>> +		else
>> +			missing |= RISCV_HWPROBE_EXT_ZBA;
>> +
>> +		if (riscv_isa_extension_available(isainfo->isa, ZBB))
>> +			pair->value |= RISCV_HWPROBE_EXT_ZBB;
>> +		else
>> +			missing |= RISCV_HWPROBE_EXT_ZBB;
>> +	}
>> +
>> +	/* Now turn off reporting features if any CPU is missing it. */
>> +	pair->value &= ~missing;
>> +}
>> +
>>  static u64 hwprobe_misaligned(const struct cpumask *cpus)
>>  {
>>  	int cpu;
>> @@ -164,13 +199,7 @@ static void hwprobe_one_pair(struct riscv_hwprobe *pair,
>>  		break;
>>  
>>  	case RISCV_HWPROBE_KEY_IMA_EXT_0:
>> -		pair->value = 0;
>> -		if (has_fpu())
>> -			pair->value |= RISCV_HWPROBE_IMA_FD;
>> -
>> -		if (riscv_isa_extension_available(NULL, c))
>> -			pair->value |= RISCV_HWPROBE_IMA_C;
>> -
>> +		hwprobe_isa_ext0(pair, cpus);
>>  		break;
>>  
>>  	case RISCV_HWPROBE_KEY_CPUPERF_0:
>> -- 
>> 2.25.1
>> 

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Re: [PATCH 3/3] RISC-V: hwprobe: Expose Zba and Zbb

[Evan Green]

On Sat, Apr 29, 2023 at 1:07 PM Palmer Dabbelt <palmer@dabbelt.com> wrote:
>
> On Sat, 29 Apr 2023 06:40:51 PDT (-0700), Conor Dooley wrote:
> > On Fri, Apr 28, 2023 at 12:06:08PM -0700, Evan Green wrote:
> >> Add two new bits to the IMA_EXT_0 key for ZBA and ZBB extensions. These
> >> are accurately reported per CPU.
> >>
> >> Signed-off-by: Evan Green <evan@rivosinc.com>
> >>
> >> ---
> >>
> >>  Documentation/riscv/hwprobe.rst       |  7 +++++
> >>  arch/riscv/include/uapi/asm/hwprobe.h |  2 ++
> >>  arch/riscv/kernel/sys_riscv.c         | 43 ++++++++++++++++++++++-----
> >>  3 files changed, 45 insertions(+), 7 deletions(-)
> >>
> >> diff --git a/Documentation/riscv/hwprobe.rst b/Documentation/riscv/hwprobe.rst
> >> index 9f0dd62dcb5d..21f444a38359 100644
> >> --- a/Documentation/riscv/hwprobe.rst
> >> +++ b/Documentation/riscv/hwprobe.rst
> >> @@ -64,6 +64,13 @@ The following keys are defined:
> >>    * :c:macro:`RISCV_HWPROBE_IMA_C`: The C extension is supported, as defined
> >>      by version 2.2 of the RISC-V ISA manual.
> >>
> >> +  * :c:macro:`RISCV_HWPROBE_EXT_ZBA`: The Zba address generation extension is
> >> +       supported, as defined in version 1.0 of the Bit-Manipulation ISA
> >> +       extensions.
> >> +
> >> +  * :c:macro:`RISCV_HWPROBE_IMA_ZBB`: The Zbb extension is supporte, as defined
> >
> > Why is one EXT_ZBA and the other is IMA_ZBB? You do not use IMA below,
> > so I assume this is a copy-paste mistake.
>
> Looks like it.  Either way this was too late for the current merge
> window, so no big deal.

Copypasta! I'll fix it.
-Evan

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