Question: Can transfer speed change mid message

Question: Can transfer speed change mid message

[H Hartley Sweeten]

Hello David,

I'm getting ready to post a SPI master driver for the EP93xx ARM processor.
Before I do I have a question.

My driver uses a work queue to process the struct spi_message's for the
devices.  It pulls each message out of the queue and then process all the
struct spi_transfer's for the message.  At the start of the message the
appropriate clock rate, SPI mode and bits/word are setup.  Then the device
is chip selected followed by actually sending/receiving the data for the
transfer.

My question is, if a message is composed of multiple transfers, is it possible
for the speed to change mid message?  If it is, does this need to be handled?

Thanks,
Hartley

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Re: Question: Can transfer speed change mid message

[Linus Walleij]

2009/8/17 H Hartley Sweeten <hartleys-3FF4nKcrg1dE2c76skzGb0EOCMrvLtNR@public.gmane.org>:

> My question is, if a message is composed of multiple transfers, is it possible
> for the speed to change mid message?  If it is, does this need to be handled?

Typically your SPI HW is clocked by some on-chip clock line, and then
the SPI speed is derived from this clock line by a simple counter/divider
register that you set up.

So if that clock line coming in from the outside can change frequency in
the middle of the message this can of course happen.
The divided speed will change proportionally at that point..

So if you want full control you also need to hook into the clk framework
if you have SW control over your platforms clocks, then add some
prechange and postchange notifiers for clock speed change and make
sure you don't exit the prechange in the middle of a message and not
process a new one until after the postchange has completed.

There is nothing like that in the generic clk framework right now to
help you unfortunately, I've been thinking a bit about it.

Linus Walleij

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Re: Question: Can transfer speed change mid message

[David Brownell]

On Monday 17 August 2009, H Hartley Sweeten wrote:
> Hello David,
> 
> I'm getting ready to post a SPI master driver for the EP93xx ARM processor.
> Before I do I have a question.
> 
> My driver uses a work queue to process the struct spi_message's for the
> devices.  It pulls each message out of the queue and then process all the
> struct spi_transfer's for the message.  At the start of the message the
> appropriate clock rate, SPI mode and bits/word are setup.  Then the device
> is chip selected followed by actually sending/receiving the data for the
> transfer.

Sounds right.


> My question is, if a message is composed of multiple transfers, is it possible
> for the speed to change mid message?

Yes; spi_transfer.speed_hz can override the default
setting in spi_device.


> If it is, does this need to be handled? 

Either handle it or reject transfers which try using
that mechanism before queueing them up.

- Dave



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