* [PATCH v2 0/4] Add interconnects to QUPs on SM8250
@ 2023-07-03 20:15 Konrad Dybcio
2023-07-03 20:15 ` [PATCH v2 1/4] dt-bindings: interconnect: qcom,rpmh: Add SM8250 QUP virt Konrad Dybcio
` (4 more replies)
0 siblings, 5 replies; 9+ messages in thread
From: Konrad Dybcio @ 2023-07-03 20:15 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Mark Brown, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Greg Kroah-Hartman,
Andi Shyti, Georgi Djakov, Odelu Kukatla, Jonathan Marek,
Sibi Sankar
Cc: Marijn Suijten, Krzysztof Kozlowski, linux-arm-msm, linux-spi,
devicetree, linux-kernel, linux-serial, linux-i2c, linux-pm,
Konrad Dybcio
SM8250 (like SM8150 but unlike all other QUP-equipped SoCs) doesn't
provide a qup-core path. Adjust the bindings and drivers as necessary,
and then describe the icc paths in the device tree. This makes it possible
for interconnect sync_state succeed so long as you don't use UFS.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
Changes in v2:
- drop everything, fix icc instead of messing with bindings
- Link to v1: https://lore.kernel.org/r/20230703-topic-8250_qup_icc-v1-0-fea39aa07525@linaro.org
---
Konrad Dybcio (4):
dt-bindings: interconnect: qcom,rpmh: Add SM8250 QUP virt
dt-bindings: interconnect: qcom,sm8250: Add QUP virt
interconnect: qcom: sm8250: Fix QUP0 nodes
arm64: dts: qcom: sm8250: Add interconnects and power-domains to QUPs
.../bindings/interconnect/qcom,rpmh.yaml | 18 +-
arch/arm64/boot/dts/qcom/sm8250.dtsi | 286 +++++++++++++++++++++
drivers/interconnect/qcom/sm8250.c | 74 +++++-
drivers/interconnect/qcom/sm8250.h | 6 +
include/dt-bindings/interconnect/qcom,sm8250.h | 7 +
5 files changed, 384 insertions(+), 7 deletions(-)
---
base-commit: 296d53d8f84ce50ffaee7d575487058c8d437335
change-id: 20230703-topic-8250_qup_icc-61768a34c7ec
Best regards,
--
Konrad Dybcio <konrad.dybcio@linaro.org>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v2 1/4] dt-bindings: interconnect: qcom,rpmh: Add SM8250 QUP virt
2023-07-03 20:15 [PATCH v2 0/4] Add interconnects to QUPs on SM8250 Konrad Dybcio
@ 2023-07-03 20:15 ` Konrad Dybcio
2023-07-04 7:26 ` Krzysztof Kozlowski
2023-07-03 20:15 ` [PATCH v2 2/4] dt-bindings: interconnect: qcom,sm8250: Add " Konrad Dybcio
` (3 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Konrad Dybcio @ 2023-07-03 20:15 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Mark Brown, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Greg Kroah-Hartman,
Andi Shyti, Georgi Djakov, Odelu Kukatla, Jonathan Marek,
Sibi Sankar
Cc: Marijn Suijten, Krzysztof Kozlowski, linux-arm-msm, linux-spi,
devicetree, linux-kernel, linux-serial, linux-i2c, linux-pm,
Konrad Dybcio
Document the QUP virtual bus on SM8250.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
.../devicetree/bindings/interconnect/qcom,rpmh.yaml | 18 ++++++++++++++----
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
index 4d93ad415e0b..a46497af1fd8 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,rpmh.yaml
@@ -18,9 +18,6 @@ description: |
least one RPMh device child node pertaining to their RSC and each provider
can map to multiple RPMh resources.
-allOf:
- - $ref: qcom,rpmh-common.yaml#
-
properties:
reg:
maxItems: 1
@@ -91,6 +88,7 @@ properties:
- qcom,sm8250-mc-virt
- qcom,sm8250-mmss-noc
- qcom,sm8250-npu-noc
+ - qcom,sm8250-qup-virt
- qcom,sm8250-system-noc
- qcom,sm8350-aggre1-noc
- qcom,sm8350-aggre2-noc
@@ -107,7 +105,19 @@ properties:
required:
- compatible
- - reg
+
+allOf:
+ - $ref: qcom,rpmh-common.yaml#
+ - if:
+ not:
+ properties:
+ compatible:
+ enum:
+ - qcom,sm8250-qup-virt
+ then:
+ required:
+ - reg
+
unevaluatedProperties: false
--
2.41.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 2/4] dt-bindings: interconnect: qcom,sm8250: Add QUP virt
2023-07-03 20:15 [PATCH v2 0/4] Add interconnects to QUPs on SM8250 Konrad Dybcio
2023-07-03 20:15 ` [PATCH v2 1/4] dt-bindings: interconnect: qcom,rpmh: Add SM8250 QUP virt Konrad Dybcio
@ 2023-07-03 20:15 ` Konrad Dybcio
2023-07-04 7:26 ` Krzysztof Kozlowski
2023-07-03 20:15 ` [PATCH v2 3/4] interconnect: qcom: sm8250: Fix QUP0 nodes Konrad Dybcio
` (2 subsequent siblings)
4 siblings, 1 reply; 9+ messages in thread
From: Konrad Dybcio @ 2023-07-03 20:15 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Mark Brown, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Greg Kroah-Hartman,
Andi Shyti, Georgi Djakov, Odelu Kukatla, Jonathan Marek,
Sibi Sankar
Cc: Marijn Suijten, Krzysztof Kozlowski, linux-arm-msm, linux-spi,
devicetree, linux-kernel, linux-serial, linux-i2c, linux-pm,
Konrad Dybcio
Add the required defines for QUP_virt nodes.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
include/dt-bindings/interconnect/qcom,sm8250.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/include/dt-bindings/interconnect/qcom,sm8250.h b/include/dt-bindings/interconnect/qcom,sm8250.h
index a4af5cc19271..2a656c02df4b 100644
--- a/include/dt-bindings/interconnect/qcom,sm8250.h
+++ b/include/dt-bindings/interconnect/qcom,sm8250.h
@@ -166,4 +166,11 @@
#define SLAVE_QDSS_STM 17
#define SLAVE_TCU 18
+#define MASTER_QUP_CORE_0 0
+#define MASTER_QUP_CORE_1 1
+#define MASTER_QUP_CORE_2 2
+#define SLAVE_QUP_CORE_0 3
+#define SLAVE_QUP_CORE_1 4
+#define SLAVE_QUP_CORE_2 5
+
#endif
--
2.41.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 3/4] interconnect: qcom: sm8250: Fix QUP0 nodes
2023-07-03 20:15 [PATCH v2 0/4] Add interconnects to QUPs on SM8250 Konrad Dybcio
2023-07-03 20:15 ` [PATCH v2 1/4] dt-bindings: interconnect: qcom,rpmh: Add SM8250 QUP virt Konrad Dybcio
2023-07-03 20:15 ` [PATCH v2 2/4] dt-bindings: interconnect: qcom,sm8250: Add " Konrad Dybcio
@ 2023-07-03 20:15 ` Konrad Dybcio
2023-07-18 4:41 ` Bjorn Andersson
2023-07-03 20:15 ` [PATCH v2 4/4] arm64: dts: qcom: sm8250: Add interconnects and power-domains to QUPs Konrad Dybcio
2023-09-19 23:07 ` (subset) [PATCH v2 0/4] Add interconnects to QUPs on SM8250 Bjorn Andersson
4 siblings, 1 reply; 9+ messages in thread
From: Konrad Dybcio @ 2023-07-03 20:15 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Mark Brown, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Greg Kroah-Hartman,
Andi Shyti, Georgi Djakov, Odelu Kukatla, Jonathan Marek,
Sibi Sankar
Cc: Marijn Suijten, Krzysztof Kozlowski, linux-arm-msm, linux-spi,
devicetree, linux-kernel, linux-serial, linux-i2c, linux-pm,
Konrad Dybcio
The QUP0 BCM relates to some internal property of the QUPs, and should
be configured independently of the path to the QUP. In line with other
platforms expose QUP_CORE endpoints in order allow this configuration.
Fixes: 6df5b349491e ("interconnect: qcom: Add SM8250 interconnect provider driver")
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
drivers/interconnect/qcom/sm8250.c | 74 ++++++++++++++++++++++++++++++++++++--
drivers/interconnect/qcom/sm8250.h | 6 ++++
2 files changed, 77 insertions(+), 3 deletions(-)
diff --git a/drivers/interconnect/qcom/sm8250.c b/drivers/interconnect/qcom/sm8250.c
index e3bb008cb219..d3d0196902cd 100644
--- a/drivers/interconnect/qcom/sm8250.c
+++ b/drivers/interconnect/qcom/sm8250.c
@@ -164,6 +164,54 @@ DEFINE_QNODE(xs_pcie_modem, SM8250_SLAVE_PCIE_2, 1, 8);
DEFINE_QNODE(xs_qdss_stm, SM8250_SLAVE_QDSS_STM, 1, 4);
DEFINE_QNODE(xs_sys_tcu_cfg, SM8250_SLAVE_TCU, 1, 8);
+static struct qcom_icc_node qup0_core_master = {
+ .name = "qup0_core_master",
+ .id = SM8250_MASTER_QUP_CORE_0,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { SM8250_SLAVE_QUP_CORE_0 },
+};
+
+static struct qcom_icc_node qup1_core_master = {
+ .name = "qup1_core_master",
+ .id = SM8250_MASTER_QUP_CORE_1,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { SM8250_SLAVE_QUP_CORE_1 },
+};
+
+static struct qcom_icc_node qup2_core_master = {
+ .name = "qup2_core_master",
+ .id = SM8250_MASTER_QUP_CORE_2,
+ .channels = 1,
+ .buswidth = 4,
+ .num_links = 1,
+ .links = { SM8250_SLAVE_QUP_CORE_2 },
+};
+
+static struct qcom_icc_node qup0_core_slave = {
+ .name = "qup0_core_slave",
+ .id = SM8250_SLAVE_QUP_CORE_0,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qup1_core_slave = {
+ .name = "qup1_core_slave",
+ .id = SM8250_SLAVE_QUP_CORE_1,
+ .channels = 1,
+ .buswidth = 4,
+};
+
+static struct qcom_icc_node qup2_core_slave = {
+ .name = "qup2_core_slave",
+ .id = SM8250_SLAVE_QUP_CORE_2,
+ .channels = 1,
+ .buswidth = 4,
+};
+
DEFINE_QBCM(bcm_acv, "ACV", false, &ebi);
DEFINE_QBCM(bcm_mc0, "MC0", true, &ebi);
DEFINE_QBCM(bcm_sh0, "SH0", true, &qns_llcc);
@@ -172,7 +220,7 @@ DEFINE_QBCM(bcm_ce0, "CE0", false, &qxm_crypto);
DEFINE_QBCM(bcm_mm1, "MM1", false, &qnm_camnoc_hf, &qxm_mdp0, &qxm_mdp1);
DEFINE_QBCM(bcm_sh2, "SH2", false, &alm_gpu_tcu, &alm_sys_tcu);
DEFINE_QBCM(bcm_mm2, "MM2", false, &qns_mem_noc_sf);
-DEFINE_QBCM(bcm_qup0, "QUP0", false, &qhm_qup1, &qhm_qup2, &qhm_qup0);
+DEFINE_QBCM(bcm_qup0, "QUP0", false, &qup0_core_master, &qup1_core_master, &qup2_core_master);
DEFINE_QBCM(bcm_sh3, "SH3", false, &qnm_cmpnoc);
DEFINE_QBCM(bcm_mm3, "MM3", false, &qnm_camnoc_icp, &qnm_camnoc_sf, &qnm_video0, &qnm_video1, &qnm_video_cvp);
DEFINE_QBCM(bcm_sh4, "SH4", false, &chm_apps);
@@ -193,7 +241,6 @@ DEFINE_QBCM(bcm_sn11, "SN11", false, &qnm_gemnoc);
DEFINE_QBCM(bcm_sn12, "SN12", false, &qns_pcie_modem_mem_noc, &qns_pcie_mem_noc);
static struct qcom_icc_bcm * const aggre1_noc_bcms[] = {
- &bcm_qup0,
&bcm_sn12,
};
@@ -222,10 +269,29 @@ static const struct qcom_icc_desc sm8250_aggre1_noc = {
static struct qcom_icc_bcm * const aggre2_noc_bcms[] = {
&bcm_ce0,
- &bcm_qup0,
&bcm_sn12,
};
+static struct qcom_icc_bcm * const qup_virt_bcms[] = {
+ &bcm_qup0,
+};
+
+static struct qcom_icc_node *qup_virt_nodes[] = {
+ [MASTER_QUP_CORE_0] = &qup0_core_master,
+ [MASTER_QUP_CORE_1] = &qup1_core_master,
+ [MASTER_QUP_CORE_2] = &qup2_core_master,
+ [SLAVE_QUP_CORE_0] = &qup0_core_slave,
+ [SLAVE_QUP_CORE_1] = &qup1_core_slave,
+ [SLAVE_QUP_CORE_2] = &qup2_core_slave,
+};
+
+static const struct qcom_icc_desc sm8250_qup_virt = {
+ .nodes = qup_virt_nodes,
+ .num_nodes = ARRAY_SIZE(qup_virt_nodes),
+ .bcms = qup_virt_bcms,
+ .num_bcms = ARRAY_SIZE(qup_virt_bcms),
+};
+
static struct qcom_icc_node * const aggre2_noc_nodes[] = {
[MASTER_A2NOC_CFG] = &qhm_a2noc_cfg,
[MASTER_QDSS_BAM] = &qhm_qdss_bam,
@@ -518,6 +584,8 @@ static const struct of_device_id qnoc_of_match[] = {
.data = &sm8250_mmss_noc},
{ .compatible = "qcom,sm8250-npu-noc",
.data = &sm8250_npu_noc},
+ { .compatible = "qcom,sm8250-qup-virt",
+ .data = &sm8250_qup_virt },
{ .compatible = "qcom,sm8250-system-noc",
.data = &sm8250_system_noc},
{ }
diff --git a/drivers/interconnect/qcom/sm8250.h b/drivers/interconnect/qcom/sm8250.h
index 209ab195f21f..032665093c5b 100644
--- a/drivers/interconnect/qcom/sm8250.h
+++ b/drivers/interconnect/qcom/sm8250.h
@@ -158,5 +158,11 @@
#define SM8250_SLAVE_VSENSE_CTRL_CFG 147
#define SM8250_SNOC_CNOC_MAS 148
#define SM8250_SNOC_CNOC_SLV 149
+#define SM8250_MASTER_QUP_CORE_0 150
+#define SM8250_MASTER_QUP_CORE_1 151
+#define SM8250_MASTER_QUP_CORE_2 152
+#define SM8250_SLAVE_QUP_CORE_0 153
+#define SM8250_SLAVE_QUP_CORE_1 154
+#define SM8250_SLAVE_QUP_CORE_2 155
#endif
--
2.41.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v2 4/4] arm64: dts: qcom: sm8250: Add interconnects and power-domains to QUPs
2023-07-03 20:15 [PATCH v2 0/4] Add interconnects to QUPs on SM8250 Konrad Dybcio
` (2 preceding siblings ...)
2023-07-03 20:15 ` [PATCH v2 3/4] interconnect: qcom: sm8250: Fix QUP0 nodes Konrad Dybcio
@ 2023-07-03 20:15 ` Konrad Dybcio
2023-09-19 23:07 ` (subset) [PATCH v2 0/4] Add interconnects to QUPs on SM8250 Bjorn Andersson
4 siblings, 0 replies; 9+ messages in thread
From: Konrad Dybcio @ 2023-07-03 20:15 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Mark Brown, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Greg Kroah-Hartman,
Andi Shyti, Georgi Djakov, Odelu Kukatla, Jonathan Marek,
Sibi Sankar
Cc: Marijn Suijten, Krzysztof Kozlowski, linux-arm-msm, linux-spi,
devicetree, linux-kernel, linux-serial, linux-i2c, linux-pm,
Konrad Dybcio
Describe the interconnect paths related to QUPs and add the power-domains
powering them.
This is required for icc sync_state, as otherwise QUP access is gated.
Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
---
arch/arm64/boot/dts/qcom/sm8250.dtsi | 286 +++++++++++++++++++++++++++++++++++
1 file changed, 286 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/sm8250.dtsi b/arch/arm64/boot/dts/qcom/sm8250.dtsi
index 1efa07f2caff..5909f04c81de 100644
--- a/arch/arm64/boot/dts/qcom/sm8250.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8250.dtsi
@@ -370,6 +370,12 @@ CLUSTER_SLEEP_0: cluster-sleep-0 {
};
};
+ qup_virt: interconnect-qup-virt {
+ compatible = "qcom,sm8250-qup-virt";
+ #interconnect-cells = <2>;
+ qcom,bcm-voters = <&apps_bcm_voter>;
+ };
+
cpu0_opp_table: opp-table-cpu0 {
compatible = "operating-points-v2";
opp-shared;
@@ -1022,6 +1028,13 @@ i2c14: i2c@880000 {
dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>,
<&gpi_dma2 1 0 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ power-domains = <&rpmhpd SM8250_CX>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1038,6 +1051,12 @@ spi14: spi@880000 {
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1054,6 +1073,13 @@ i2c15: i2c@884000 {
dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>,
<&gpi_dma2 1 1 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ power-domains = <&rpmhpd SM8250_CX>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1070,6 +1096,12 @@ spi15: spi@884000 {
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1086,6 +1118,13 @@ i2c16: i2c@888000 {
dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>,
<&gpi_dma2 1 2 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ power-domains = <&rpmhpd SM8250_CX>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1102,6 +1141,12 @@ spi16: spi@888000 {
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1118,6 +1163,13 @@ i2c17: i2c@88c000 {
dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>,
<&gpi_dma2 1 3 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ power-domains = <&rpmhpd SM8250_CX>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1134,6 +1186,12 @@ spi17: spi@88c000 {
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1149,6 +1207,10 @@ uart17: serial@88c000 {
interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SM8250_CX>;
operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
+ interconnect-names = "qup-core",
+ "qup-config";
status = "disabled";
};
@@ -1163,6 +1225,13 @@ i2c18: i2c@890000 {
dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>,
<&gpi_dma2 1 4 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ power-domains = <&rpmhpd SM8250_CX>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1179,6 +1248,12 @@ spi18: spi@890000 {
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1194,6 +1269,10 @@ uart18: serial@890000 {
interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SM8250_CX>;
operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>;
+ interconnect-names = "qup-core",
+ "qup-config";
status = "disabled";
};
@@ -1208,6 +1287,13 @@ i2c19: i2c@894000 {
dmas = <&gpi_dma2 0 5 QCOM_GPI_I2C>,
<&gpi_dma2 1 5 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ power-domains = <&rpmhpd SM8250_CX>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1224,6 +1310,12 @@ spi19: spi@894000 {
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_2 0 &qup_virt SLAVE_QUP_CORE_2 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_2 0>,
+ <&aggre1_noc MASTER_QUP_2 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1276,6 +1368,13 @@ i2c0: i2c@980000 {
dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
<&gpi_dma0 1 0 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ power-domains = <&rpmhpd SM8250_CX>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1292,6 +1391,12 @@ spi0: spi@980000 {
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1308,6 +1413,13 @@ i2c1: i2c@984000 {
dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
<&gpi_dma0 1 1 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ power-domains = <&rpmhpd SM8250_CX>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1324,6 +1436,12 @@ spi1: spi@984000 {
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1340,6 +1458,13 @@ i2c2: i2c@988000 {
dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
<&gpi_dma0 1 2 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ power-domains = <&rpmhpd SM8250_CX>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1356,6 +1481,12 @@ spi2: spi@988000 {
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1371,6 +1502,10 @@ uart2: serial@988000 {
interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SM8250_CX>;
operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core",
+ "qup-config";
status = "disabled";
};
@@ -1385,6 +1520,13 @@ i2c3: i2c@98c000 {
dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
<&gpi_dma0 1 3 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ power-domains = <&rpmhpd SM8250_CX>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1401,6 +1543,12 @@ spi3: spi@98c000 {
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1417,6 +1565,13 @@ i2c4: i2c@990000 {
dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
<&gpi_dma0 1 4 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ power-domains = <&rpmhpd SM8250_CX>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1433,6 +1588,12 @@ spi4: spi@990000 {
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1449,6 +1610,13 @@ i2c5: i2c@994000 {
dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
<&gpi_dma0 1 5 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ power-domains = <&rpmhpd SM8250_CX>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1465,6 +1633,12 @@ spi5: spi@994000 {
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1481,6 +1655,13 @@ i2c6: i2c@998000 {
dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
<&gpi_dma0 1 6 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ power-domains = <&rpmhpd SM8250_CX>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1497,6 +1678,12 @@ spi6: spi@998000 {
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1512,6 +1699,10 @@ uart6: serial@998000 {
interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SM8250_CX>;
operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>;
+ interconnect-names = "qup-core",
+ "qup-config";
status = "disabled";
};
@@ -1526,6 +1717,13 @@ i2c7: i2c@99c000 {
dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
<&gpi_dma0 1 7 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ power-domains = <&rpmhpd SM8250_CX>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1542,6 +1740,12 @@ spi7: spi@99c000 {
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_0 0 &qup_virt SLAVE_QUP_CORE_0 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_0 0>,
+ <&aggre2_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1591,6 +1795,13 @@ i2c8: i2c@a80000 {
dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>,
<&gpi_dma1 1 0 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ power-domains = <&rpmhpd SM8250_CX>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1607,6 +1818,12 @@ spi8: spi@a80000 {
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1623,6 +1840,13 @@ i2c9: i2c@a84000 {
dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>,
<&gpi_dma1 1 1 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ power-domains = <&rpmhpd SM8250_CX>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1639,6 +1863,12 @@ spi9: spi@a84000 {
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1655,6 +1885,13 @@ i2c10: i2c@a88000 {
dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>,
<&gpi_dma1 1 2 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ power-domains = <&rpmhpd SM8250_CX>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1671,6 +1908,12 @@ spi10: spi@a88000 {
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1687,6 +1930,13 @@ i2c11: i2c@a8c000 {
dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>,
<&gpi_dma1 1 3 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ power-domains = <&rpmhpd SM8250_CX>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1703,6 +1953,12 @@ spi11: spi@a8c000 {
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1719,6 +1975,13 @@ i2c12: i2c@a90000 {
dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>,
<&gpi_dma1 1 4 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ power-domains = <&rpmhpd SM8250_CX>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1735,6 +1998,12 @@ spi12: spi@a90000 {
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1750,6 +2019,10 @@ uart12: serial@a90000 {
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
power-domains = <&rpmhpd SM8250_CX>;
operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>;
+ interconnect-names = "qup-core",
+ "qup-config";
status = "disabled";
};
@@ -1764,6 +2037,13 @@ i2c13: i2c@a94000 {
dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>,
<&gpi_dma1 1 5 QCOM_GPI_I2C>;
dma-names = "tx", "rx";
+ power-domains = <&rpmhpd SM8250_CX>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
@@ -1780,6 +2060,12 @@ spi13: spi@a94000 {
dma-names = "tx", "rx";
power-domains = <&rpmhpd SM8250_CX>;
operating-points-v2 = <&qup_opp_table>;
+ interconnects = <&qup_virt MASTER_QUP_CORE_1 0 &qup_virt SLAVE_QUP_CORE_1 0>,
+ <&gem_noc MASTER_AMPSS_M0 0 &config_noc SLAVE_QUP_1 0>,
+ <&aggre1_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI_CH0 0>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
--
2.41.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v2 1/4] dt-bindings: interconnect: qcom,rpmh: Add SM8250 QUP virt
2023-07-03 20:15 ` [PATCH v2 1/4] dt-bindings: interconnect: qcom,rpmh: Add SM8250 QUP virt Konrad Dybcio
@ 2023-07-04 7:26 ` Krzysztof Kozlowski
0 siblings, 0 replies; 9+ messages in thread
From: Krzysztof Kozlowski @ 2023-07-04 7:26 UTC (permalink / raw)
To: Konrad Dybcio, Andy Gross, Bjorn Andersson, Mark Brown,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Greg Kroah-Hartman, Andi Shyti, Georgi Djakov, Odelu Kukatla,
Jonathan Marek, Sibi Sankar
Cc: Marijn Suijten, linux-arm-msm, linux-spi, devicetree,
linux-kernel, linux-serial, linux-i2c, linux-pm
On 03/07/2023 22:15, Konrad Dybcio wrote:
> Document the QUP virtual bus on SM8250.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
> +
> +allOf:
> + - $ref: qcom,rpmh-common.yaml#
> + - if:
> + not:
> + properties:
> + compatible:
> + enum:
> + - qcom,sm8250-qup-virt
> + then:
> + required:
> + - reg
> +
>
If there is going to be new version - drop stray blank line here.
In any case:
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 2/4] dt-bindings: interconnect: qcom,sm8250: Add QUP virt
2023-07-03 20:15 ` [PATCH v2 2/4] dt-bindings: interconnect: qcom,sm8250: Add " Konrad Dybcio
@ 2023-07-04 7:26 ` Krzysztof Kozlowski
0 siblings, 0 replies; 9+ messages in thread
From: Krzysztof Kozlowski @ 2023-07-04 7:26 UTC (permalink / raw)
To: Konrad Dybcio, Andy Gross, Bjorn Andersson, Mark Brown,
Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Greg Kroah-Hartman, Andi Shyti, Georgi Djakov, Odelu Kukatla,
Jonathan Marek, Sibi Sankar
Cc: Marijn Suijten, linux-arm-msm, linux-spi, devicetree,
linux-kernel, linux-serial, linux-i2c, linux-pm
On 03/07/2023 22:15, Konrad Dybcio wrote:
> Add the required defines for QUP_virt nodes.
>
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
> ---
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v2 3/4] interconnect: qcom: sm8250: Fix QUP0 nodes
2023-07-03 20:15 ` [PATCH v2 3/4] interconnect: qcom: sm8250: Fix QUP0 nodes Konrad Dybcio
@ 2023-07-18 4:41 ` Bjorn Andersson
0 siblings, 0 replies; 9+ messages in thread
From: Bjorn Andersson @ 2023-07-18 4:41 UTC (permalink / raw)
To: Konrad Dybcio
Cc: Andy Gross, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Greg Kroah-Hartman, Andi Shyti, Georgi Djakov,
Odelu Kukatla, Jonathan Marek, Sibi Sankar, Marijn Suijten,
Krzysztof Kozlowski, linux-arm-msm, linux-spi, devicetree,
linux-kernel, linux-serial, linux-i2c, linux-pm
On Mon, Jul 03, 2023 at 10:15:27PM +0200, Konrad Dybcio wrote:
> The QUP0 BCM relates to some internal property of the QUPs, and should
> be configured independently of the path to the QUP. In line with other
> platforms expose QUP_CORE endpoints in order allow this configuration.
>
> Fixes: 6df5b349491e ("interconnect: qcom: Add SM8250 interconnect provider driver")
> Signed-off-by: Konrad Dybcio <konrad.dybcio@linaro.org>
Reviewed-by: Bjorn Andersson <andersson@kernel.org>
Regards,
Bjorn
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: (subset) [PATCH v2 0/4] Add interconnects to QUPs on SM8250
2023-07-03 20:15 [PATCH v2 0/4] Add interconnects to QUPs on SM8250 Konrad Dybcio
` (3 preceding siblings ...)
2023-07-03 20:15 ` [PATCH v2 4/4] arm64: dts: qcom: sm8250: Add interconnects and power-domains to QUPs Konrad Dybcio
@ 2023-09-19 23:07 ` Bjorn Andersson
4 siblings, 0 replies; 9+ messages in thread
From: Bjorn Andersson @ 2023-09-19 23:07 UTC (permalink / raw)
To: Andy Gross, Mark Brown, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Greg Kroah-Hartman, Andi Shyti, Georgi Djakov,
Jonathan Marek, Odelu Kukatla, Sibi Sankar, Konrad Dybcio
Cc: Marijn Suijten, Krzysztof Kozlowski, linux-arm-msm, linux-spi,
devicetree, linux-kernel, linux-serial, linux-i2c, linux-pm
On Mon, 03 Jul 2023 22:15:24 +0200, Konrad Dybcio wrote:
> SM8250 (like SM8150 but unlike all other QUP-equipped SoCs) doesn't
> provide a qup-core path. Adjust the bindings and drivers as necessary,
> and then describe the icc paths in the device tree. This makes it possible
> for interconnect sync_state succeed so long as you don't use UFS.
>
>
Applied, thanks!
[4/4] arm64: dts: qcom: sm8250: Add interconnects and power-domains to QUPs
commit: 86a9264b6c56c9eee6dd5c8733f92afd3f58ce98
Best regards,
--
Bjorn Andersson <andersson@kernel.org>
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2023-09-19 23:03 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2023-07-03 20:15 [PATCH v2 0/4] Add interconnects to QUPs on SM8250 Konrad Dybcio
2023-07-03 20:15 ` [PATCH v2 1/4] dt-bindings: interconnect: qcom,rpmh: Add SM8250 QUP virt Konrad Dybcio
2023-07-04 7:26 ` Krzysztof Kozlowski
2023-07-03 20:15 ` [PATCH v2 2/4] dt-bindings: interconnect: qcom,sm8250: Add " Konrad Dybcio
2023-07-04 7:26 ` Krzysztof Kozlowski
2023-07-03 20:15 ` [PATCH v2 3/4] interconnect: qcom: sm8250: Fix QUP0 nodes Konrad Dybcio
2023-07-18 4:41 ` Bjorn Andersson
2023-07-03 20:15 ` [PATCH v2 4/4] arm64: dts: qcom: sm8250: Add interconnects and power-domains to QUPs Konrad Dybcio
2023-09-19 23:07 ` (subset) [PATCH v2 0/4] Add interconnects to QUPs on SM8250 Bjorn Andersson
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