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* [PATCH 1/3] spi: add SPI_RX_CPHA_FLIP mode bit
@ 2022-04-11 18:45 Baruch Siach
  2022-04-11 18:45 ` [PATCH 2/3] spi: spidev: add SPI_RX_CPHA_FLIP Baruch Siach
                   ` (2 more replies)
  0 siblings, 3 replies; 4+ messages in thread
From: Baruch Siach @ 2022-04-11 18:45 UTC (permalink / raw)
  To: Mark Brown
  Cc: Baruch Siach, linux-spi, Shawn Guo, Sascha Hauer,
	Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
	linux-arm-kernel

From: Baruch Siach <baruch.siach@siklu.com>

Some SPI devices latch MOSI bits on one clock phase, but produce valid
MISO bits on the other phase. Add SPI_RX_CPHA_FLIP mode to instruct the
controller driver to flip CPHA for Rx (MISO) only transfers.

Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
---
 include/uapi/linux/spi/spi.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/include/uapi/linux/spi/spi.h b/include/uapi/linux/spi/spi.h
index 236a85f08ded..9d5f58059703 100644
--- a/include/uapi/linux/spi/spi.h
+++ b/include/uapi/linux/spi/spi.h
@@ -27,6 +27,7 @@
 #define	SPI_TX_OCTAL		_BITUL(13)	/* transmit with 8 wires */
 #define	SPI_RX_OCTAL		_BITUL(14)	/* receive with 8 wires */
 #define	SPI_3WIRE_HIZ		_BITUL(15)	/* high impedance turnaround */
+#define	SPI_RX_CPHA_FLIP	_BITUL(16)	/* flip CPHA on Rx only xfer */
 
 /*
  * All the bits defined above should be covered by SPI_MODE_USER_MASK.
@@ -36,6 +37,6 @@
  * These bits must not overlap. A static assert check should make sure of that.
  * If adding extra bits, make sure to increase the bit index below as well.
  */
-#define SPI_MODE_USER_MASK	(_BITUL(16) - 1)
+#define SPI_MODE_USER_MASK	(_BITUL(17) - 1)
 
 #endif /* _UAPI_SPI_H */
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 4+ messages in thread

* [PATCH 2/3] spi: spidev: add SPI_RX_CPHA_FLIP
  2022-04-11 18:45 [PATCH 1/3] spi: add SPI_RX_CPHA_FLIP mode bit Baruch Siach
@ 2022-04-11 18:45 ` Baruch Siach
  2022-04-11 18:45 ` [PATCH 3/3] spi: spi-imx: add support for SPI_RX_CPHA_FLIP Baruch Siach
  2022-04-19 22:45 ` [PATCH 1/3] spi: add SPI_RX_CPHA_FLIP mode bit Mark Brown
  2 siblings, 0 replies; 4+ messages in thread
From: Baruch Siach @ 2022-04-11 18:45 UTC (permalink / raw)
  To: Mark Brown
  Cc: Baruch Siach, linux-spi, Shawn Guo, Sascha Hauer,
	Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
	linux-arm-kernel

From: Baruch Siach <baruch.siach@siklu.com>

Allow userspace to set SPI_RX_CPHA_FLIP mode bit using the
SPI_IOC_WR_MODE32 ioctl.

Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
---
 drivers/spi/spidev.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/spidev.c b/drivers/spi/spidev.c
index 968dab2f5e3d..ff1a959fb30f 100644
--- a/drivers/spi/spidev.c
+++ b/drivers/spi/spidev.c
@@ -63,7 +63,8 @@ static DECLARE_BITMAP(minors, N_SPI_MINORS);
 				| SPI_LSB_FIRST | SPI_3WIRE | SPI_LOOP \
 				| SPI_NO_CS | SPI_READY | SPI_TX_DUAL \
 				| SPI_TX_QUAD | SPI_TX_OCTAL | SPI_RX_DUAL \
-				| SPI_RX_QUAD | SPI_RX_OCTAL)
+				| SPI_RX_QUAD | SPI_RX_OCTAL \
+				| SPI_RX_CPHA_FLIP)
 
 struct spidev_data {
 	dev_t			devt;
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 4+ messages in thread

* [PATCH 3/3] spi: spi-imx: add support for SPI_RX_CPHA_FLIP
  2022-04-11 18:45 [PATCH 1/3] spi: add SPI_RX_CPHA_FLIP mode bit Baruch Siach
  2022-04-11 18:45 ` [PATCH 2/3] spi: spidev: add SPI_RX_CPHA_FLIP Baruch Siach
@ 2022-04-11 18:45 ` Baruch Siach
  2022-04-19 22:45 ` [PATCH 1/3] spi: add SPI_RX_CPHA_FLIP mode bit Mark Brown
  2 siblings, 0 replies; 4+ messages in thread
From: Baruch Siach @ 2022-04-11 18:45 UTC (permalink / raw)
  To: Mark Brown
  Cc: Baruch Siach, linux-spi, Shawn Guo, Sascha Hauer,
	Pengutronix Kernel Team, Fabio Estevam, NXP Linux Team,
	linux-arm-kernel

From: Baruch Siach <baruch.siach@siklu.com>

When SPI_RX_CPHA_FLIP is set, flip CPHA on Rx only transfers. This is
useful to access devices that use inverted CPHA for MISO vs MOSI
signals.

Only support the mx51/mx53 variants for now.

Tested on i.MX6ULL based system.

Signed-off-by: Baruch Siach <baruch.siach@siklu.com>
---
 drivers/spi/spi-imx.c | 32 +++++++++++++++++++++++++++-----
 1 file changed, 27 insertions(+), 5 deletions(-)

diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index b2dd0a4d2446..4e1bfe2f043a 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -108,6 +108,7 @@ struct spi_imx_data {
 	const void *tx_buf;
 	unsigned int txfifo; /* number of words pushed in tx FIFO */
 	unsigned int dynamic_burst;
+	bool rx_only;
 
 	/* Slave mode */
 	bool slave_mode;
@@ -554,11 +555,6 @@ static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx,
 	else
 		cfg |= MX51_ECSPI_CONFIG_SBBCTRL(spi->chip_select);
 
-	if (spi->mode & SPI_CPHA)
-		cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
-	else
-		cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
-
 	if (spi->mode & SPI_CPOL) {
 		cfg |= MX51_ECSPI_CONFIG_SCLKPOL(spi->chip_select);
 		cfg |= MX51_ECSPI_CONFIG_SCLKCTL(spi->chip_select);
@@ -606,6 +602,24 @@ static int mx51_ecspi_prepare_message(struct spi_imx_data *spi_imx,
 	return 0;
 }
 
+static void mx51_configure_cpha(struct spi_imx_data *spi_imx,
+				struct spi_device *spi)
+{
+	bool cpha = (spi->mode & SPI_CPHA);
+	bool flip_cpha = (spi->mode & SPI_RX_CPHA_FLIP) && spi_imx->rx_only;
+	u32 cfg = readl(spi_imx->base + MX51_ECSPI_CONFIG);
+
+	/* Flip cpha logical value iff flip_cpha */
+	cpha ^= flip_cpha;
+
+	if (cpha)
+		cfg |= MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
+	else
+		cfg &= ~MX51_ECSPI_CONFIG_SCLKPHA(spi->chip_select);
+
+	writel(cfg, spi_imx->base + MX51_ECSPI_CONFIG);
+}
+
 static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
 				       struct spi_device *spi)
 {
@@ -627,6 +641,8 @@ static int mx51_ecspi_prepare_transfer(struct spi_imx_data *spi_imx,
 	ctrl |= mx51_ecspi_clkdiv(spi_imx, spi_imx->spi_bus_clk, &clk);
 	spi_imx->spi_bus_clk = clk;
 
+	mx51_configure_cpha(spi_imx, spi);
+
 	/*
 	 * ERR009165: work in XHC mode instead of SMC as PIO on the chips
 	 * before i.mx6ul.
@@ -1251,6 +1267,9 @@ static int spi_imx_setupxfer(struct spi_device *spi,
 	else
 		spi_imx->usedma = false;
 
+	spi_imx->rx_only = ((t->tx_buf == NULL)
+			|| (t->tx_buf == spi->controller->dummy_tx));
+
 	if (is_imx53_ecspi(spi_imx) && spi_imx->slave_mode) {
 		spi_imx->rx = mx53_ecspi_rx_slave;
 		spi_imx->tx = mx53_ecspi_tx_slave;
@@ -1655,6 +1674,9 @@ static int spi_imx_probe(struct platform_device *pdev)
 	    is_imx53_ecspi(spi_imx))
 		spi_imx->bitbang.master->mode_bits |= SPI_LOOP | SPI_READY;
 
+	if (is_imx51_ecspi(spi_imx) || is_imx53_ecspi(spi_imx))
+		spi_imx->bitbang.master->mode_bits |= SPI_RX_CPHA_FLIP;
+
 	if (is_imx51_ecspi(spi_imx) &&
 	    device_property_read_u32(&pdev->dev, "cs-gpios", NULL))
 		/*
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [PATCH 1/3] spi: add SPI_RX_CPHA_FLIP mode bit
  2022-04-11 18:45 [PATCH 1/3] spi: add SPI_RX_CPHA_FLIP mode bit Baruch Siach
  2022-04-11 18:45 ` [PATCH 2/3] spi: spidev: add SPI_RX_CPHA_FLIP Baruch Siach
  2022-04-11 18:45 ` [PATCH 3/3] spi: spi-imx: add support for SPI_RX_CPHA_FLIP Baruch Siach
@ 2022-04-19 22:45 ` Mark Brown
  2 siblings, 0 replies; 4+ messages in thread
From: Mark Brown @ 2022-04-19 22:45 UTC (permalink / raw)
  To: baruch
  Cc: linux-arm-kernel, festevam, Sascha Hauer, linux-spi, linux-imx,
	baruch.siach, shawnguo, kernel

On Mon, 11 Apr 2022 21:45:27 +0300, Baruch Siach wrote:
> From: Baruch Siach <baruch.siach@siklu.com>
> 
> Some SPI devices latch MOSI bits on one clock phase, but produce valid
> MISO bits on the other phase. Add SPI_RX_CPHA_FLIP mode to instruct the
> controller driver to flip CPHA for Rx (MISO) only transfers.
> 
> 
> [...]

Applied to

   https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-next

Thanks!

[1/3] spi: add SPI_RX_CPHA_FLIP mode bit
      commit: b617be33502d2bfefffef71924c7a7ba50264ff6
[2/3] spi: spidev: add SPI_RX_CPHA_FLIP
      commit: 178d0cbbfe8ec652083058968c7a27485eaa33d2
[3/3] spi: spi-imx: add support for SPI_RX_CPHA_FLIP
      commit: 79422ed9bd7fbd79f84d8a5abb0094c16221f55b

All being well this means that it will be integrated into the linux-next
tree (usually sometime in the next 24 hours) and sent to Linus during
the next merge window (or sooner if it is a bug fix), however if
problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing
and review of the tree, please engage with people reporting problems and
send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they
should be sent as incremental updates against current git, existing
patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying
to this mail.

Thanks,
Mark

^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2022-04-19 22:45 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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2022-04-11 18:45 [PATCH 1/3] spi: add SPI_RX_CPHA_FLIP mode bit Baruch Siach
2022-04-11 18:45 ` [PATCH 2/3] spi: spidev: add SPI_RX_CPHA_FLIP Baruch Siach
2022-04-11 18:45 ` [PATCH 3/3] spi: spi-imx: add support for SPI_RX_CPHA_FLIP Baruch Siach
2022-04-19 22:45 ` [PATCH 1/3] spi: add SPI_RX_CPHA_FLIP mode bit Mark Brown

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