* [PATCH] ARM: tegra: paz00: Add emc-tables for ram-code 1
@ 2024-02-22 20:21 Nicolas Chauvet
2024-04-26 15:16 ` Thierry Reding
0 siblings, 1 reply; 3+ messages in thread
From: Nicolas Chauvet @ 2024-02-22 20:21 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Marc Dietrich
Cc: linux-tegra, devicetree, Andre Przywara, Linus Walleij,
Geert Uytterhoeven, Nicolas Chauvet
The same table as ram-code 0 operates correctly on ram-code 1
v2: rebase on current kernel
Signed-off-by: Nicolas Chauvet <kwizart@gmail.com>
---
arch/arm/boot/dts/nvidia/tegra20-paz00.dts | 43 ++++++++++++++++++++++
1 file changed, 43 insertions(+)
diff --git a/arch/arm/boot/dts/nvidia/tegra20-paz00.dts b/arch/arm/boot/dts/nvidia/tegra20-paz00.dts
index afb922bd79a7..1408e1e00759 100644
--- a/arch/arm/boot/dts/nvidia/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/nvidia/tegra20-paz00.dts
@@ -533,6 +533,49 @@ emc-table@333000 {
0x00000000 0x00000000 0x00000000 0x00000000>;
};
};
+
+ emc-tables@1 {
+ nvidia,ram-code = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <1>;
+
+ emc-table@166500 {
+ reg = <166500>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <166500>;
+ nvidia,emc-registers = <0x0000000a 0x00000016
+ 0x00000008 0x00000003 0x00000004 0x00000004
+ 0x00000002 0x0000000c 0x00000003 0x00000003
+ 0x00000002 0x00000001 0x00000004 0x00000005
+ 0x00000004 0x00000009 0x0000000d 0x000004df
+ 0x00000000 0x00000003 0x00000003 0x00000003
+ 0x00000003 0x00000001 0x0000000a 0x000000c8
+ 0x00000003 0x00000006 0x00000004 0x00000008
+ 0x00000002 0x00000000 0x00000000 0x00000002
+ 0x00000000 0x00000000 0x00000083 0xe03b0323
+ 0x007fe010 0x00001414 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+
+ emc-table@333000 {
+ reg = <333000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <333000>;
+ nvidia,emc-registers = <0x00000018 0x00000033
+ 0x00000012 0x00000004 0x00000004 0x00000005
+ 0x00000003 0x0000000c 0x00000006 0x00000006
+ 0x00000003 0x00000001 0x00000004 0x00000005
+ 0x00000004 0x00000009 0x0000000d 0x00000bff
+ 0x00000000 0x00000003 0x00000003 0x00000006
+ 0x00000006 0x00000001 0x00000011 0x000000c8
+ 0x00000003 0x0000000e 0x00000007 0x00000008
+ 0x00000002 0x00000000 0x00000000 0x00000002
+ 0x00000000 0x00000000 0x00000083 0xf0440303
+ 0x007fe010 0x00001414 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+ };
};
usb@c5000000 {
--
2.42.0
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] ARM: tegra: paz00: Add emc-tables for ram-code 1
2024-02-22 20:21 [PATCH] ARM: tegra: paz00: Add emc-tables for ram-code 1 Nicolas Chauvet
@ 2024-04-26 15:16 ` Thierry Reding
0 siblings, 0 replies; 3+ messages in thread
From: Thierry Reding @ 2024-04-26 15:16 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter, Marc Dietrich, Nicolas Chauvet
Cc: linux-tegra, devicetree, Andre Przywara, Linus Walleij,
Geert Uytterhoeven
From: Thierry Reding <treding@nvidia.com>
On Thu, 22 Feb 2024 21:21:42 +0100, Nicolas Chauvet wrote:
> The same table as ram-code 0 operates correctly on ram-code 1
>
> v2: rebase on current kernel
>
>
Applied, thanks!
[1/1] ARM: tegra: paz00: Add emc-tables for ram-code 1
(no commit info)
Best regards,
--
Thierry Reding <treding@nvidia.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
* [PATCH] ARM: tegra: paz00: Add emc-tables for ram-code 1
@ 2021-03-18 8:30 Nicolas Chauvet
0 siblings, 0 replies; 3+ messages in thread
From: Nicolas Chauvet @ 2021-03-18 8:30 UTC (permalink / raw)
To: Thierry Reding, Jonathan Hunter; +Cc: linux-tegra, Nicolas Chauvet
This is the same tables as ram-code 0
Signed-off-by: Nicolas Chauvet <kwizart@gmail.com>
---
arch/arm/boot/dts/tegra20-paz00.dts | 42 +++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm/boot/dts/tegra20-paz00.dts b/arch/arm/boot/dts/tegra20-paz00.dts
index 9efb5f4f486a..da76ce070109 100644
--- a/arch/arm/boot/dts/tegra20-paz00.dts
+++ b/arch/arm/boot/dts/tegra20-paz00.dts
@@ -355,6 +355,48 @@ emc-table@333000 {
0x00000000 0x00000000 0x00000000 0x00000000>;
};
};
+
+ emc-tables@1 {
+ nvidia,ram-code = <0x1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ emc-table@166500 {
+ reg = <166500>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <166500>;
+ nvidia,emc-registers = <0x0000000a 0x00000016
+ 0x00000008 0x00000003 0x00000004 0x00000004
+ 0x00000002 0x0000000c 0x00000003 0x00000003
+ 0x00000002 0x00000001 0x00000004 0x00000005
+ 0x00000004 0x00000009 0x0000000d 0x000004df
+ 0x00000000 0x00000003 0x00000003 0x00000003
+ 0x00000003 0x00000001 0x0000000a 0x000000c8
+ 0x00000003 0x00000006 0x00000004 0x00000008
+ 0x00000002 0x00000000 0x00000000 0x00000002
+ 0x00000000 0x00000000 0x00000083 0xe03b0323
+ 0x007fe010 0x00001414 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+
+ emc-table@333000 {
+ reg = <333000>;
+ compatible = "nvidia,tegra20-emc-table";
+ clock-frequency = <333000>;
+ nvidia,emc-registers = <0x00000018 0x00000033
+ 0x00000012 0x00000004 0x00000004 0x00000005
+ 0x00000003 0x0000000c 0x00000006 0x00000006
+ 0x00000003 0x00000001 0x00000004 0x00000005
+ 0x00000004 0x00000009 0x0000000d 0x00000bff
+ 0x00000000 0x00000003 0x00000003 0x00000006
+ 0x00000006 0x00000001 0x00000011 0x000000c8
+ 0x00000003 0x0000000e 0x00000007 0x00000008
+ 0x00000002 0x00000000 0x00000000 0x00000002
+ 0x00000000 0x00000000 0x00000083 0xf0440303
+ 0x007fe010 0x00001414 0x00000000 0x00000000
+ 0x00000000 0x00000000 0x00000000 0x00000000>;
+ };
+ };
};
i2c@7000d000 {
--
2.30.2
^ permalink raw reply related [flat|nested] 3+ messages in thread
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2024-04-26 15:16 ` Thierry Reding
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