From: Paul Cercueil <paul@crapouillou.net>
To: Thomas Gleixner <tglx@linutronix.de>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Thierry Reding <thierry.reding@gmail.com>,
Mark Rutland <mark.rutland@arm.com>,
Ralf Baechle <ralf@linux-mips.org>,
Paul Burton <paul.burton@mips.com>,
Jonathan Corbet <corbet@lwn.net>
Cc: od@zcrc.me, Mathieu Malaterre <malat@debian.org>,
linux-pwm@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org,
linux-mips@linux-mips.org, linux-doc@vger.kernel.org,
linux-clk@vger.kernel.org, Paul Cercueil <paul@crapouillou.net>
Subject: [PATCH v7 03/24] doc: Add doc for the Ingenic TCU hardware
Date: Tue, 21 Aug 2018 19:16:14 +0200 [thread overview]
Message-ID: <20180821171635.22740-4-paul@crapouillou.net> (raw)
In-Reply-To: <20180821171635.22740-1-paul@crapouillou.net>
Add a documentation file about the Timer/Counter Unit (TCU) present in
the Ingenic JZ47xx SoCs.
The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
hardware block. It features up to to eight channels, that can be used as
counters, timers, or PWM.
- JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
have eight channels.
- JZ4725B introduced a separate channel, called Operating System Timer
(OST). It is a 32-bit programmable timer. On JZ4770 and above, it is
64-bit.
- Each one of the TCU channels has its own clock, which can be reparented
to three different clocks (pclk, ext, rtc), gated, and reclocked, through
their TCSR register.
* The watchdog and OST hardware blocks also feature a TCSR register with
the same format in their register space.
* The TCU registers used to gate/ungate can also gate/ungate the watchdog
and OST clocks.
- Each TCU channel works in one of two modes:
* mode TCU1: channels cannot work in sleep mode, but are easier to
operate.
* mode TCU2: channels can work in sleep mode, but the operation is a bit
more complicated than with TCU1 channels.
- The mode of each TCU channel depends on the SoC used:
* On the oldest SoCs (up to JZ4740), all of the eight channels operate in
TCU1 mode.
* On JZ4725B, channel 5 operates as TCU2, the others operate as TCU1.
* On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the
others operate as TCU1.
- Each channel can generate an interrupt. Some channels share an interrupt
line, some don't, and this changes between SoC versions:
* on older SoCs (JZ4740 and below), channel 0 and channel 1 have their
own interrupt line; channels 2-7 share the last interrupt line.
* On JZ4725B, channel 0 has its own interrupt; channels 1-5 share one
interrupt line; the OST uses the last interrupt line.
* on newer SoCs (JZ4750 and above), channel 5 has its own interrupt;
channels 0-4 and (if eight channels) 6-7 all share one interrupt line;
the OST uses the last interrupt line.
Signed-off-by: Paul Cercueil <paul@crapouillou.net>
---
Notes:
v4: New patch in this series
v5: Added information about number of channels, and improved
documentation about channel modes
v6: Add info about OST (can be 32-bit on older SoCs)
v7: No change
Documentation/mips/00-INDEX | 3 ++
Documentation/mips/ingenic-tcu.txt | 60 ++++++++++++++++++++++++++++++++++++++
2 files changed, 63 insertions(+)
create mode 100644 Documentation/mips/ingenic-tcu.txt
diff --git a/Documentation/mips/00-INDEX b/Documentation/mips/00-INDEX
index 8ae9cffc2262..8ab8c3f83771 100644
--- a/Documentation/mips/00-INDEX
+++ b/Documentation/mips/00-INDEX
@@ -2,3 +2,6 @@
- this file.
AU1xxx_IDE.README
- README for MIPS AU1XXX IDE driver.
+ingenic-tcu.txt
+ - Information file about the Timer/Counter Unit present
+ in Ingenic JZ47xx SoCs.
diff --git a/Documentation/mips/ingenic-tcu.txt b/Documentation/mips/ingenic-tcu.txt
new file mode 100644
index 000000000000..0ea35b2a46da
--- /dev/null
+++ b/Documentation/mips/ingenic-tcu.txt
@@ -0,0 +1,60 @@
+Ingenic JZ47xx SoCs Timer/Counter Unit hardware
+-----------------------------------------------
+
+The Timer/Counter Unit (TCU) in Ingenic JZ47xx SoCs is a multi-function
+hardware block. It features up to to eight channels, that can be used as
+counters, timers, or PWM.
+
+- JZ4725B, JZ4750, JZ4755 only have six TCU channels. The other SoCs all
+ have eight channels.
+
+- JZ4725B introduced a separate channel, called Operating System Timer
+ (OST). It is a 32-bit programmable timer. On JZ4770 and above, it is
+ 64-bit.
+
+- Each one of the TCU channels has its own clock, which can be reparented
+ to three different clocks (pclk, ext, rtc), gated, and reclocked, through
+ their TCSR register.
+ * The watchdog and OST hardware blocks also feature a TCSR register with
+ the same format in their register space.
+ * The TCU registers used to gate/ungate can also gate/ungate the watchdog
+ and OST clocks.
+
+- Each TCU channel works in one of two modes:
+ * mode TCU1: channels cannot work in sleep mode, but are easier to
+ operate.
+ * mode TCU2: channels can work in sleep mode, but the operation is a bit
+ more complicated than with TCU1 channels.
+
+- The mode of each TCU channel depends on the SoC used:
+ * On the oldest SoCs (up to JZ4740), all of the eight channels operate in
+ TCU1 mode.
+ * On JZ4725B, channel 5 operates as TCU2, the others operate as TCU1.
+ * On newest SoCs (JZ4750 and above), channels 1-2 operate as TCU2, the
+ others operate as TCU1.
+
+- Each channel can generate an interrupt. Some channels share an interrupt
+ line, some don't, and this changes between SoC versions:
+ * on older SoCs (JZ4740 and below), channel 0 and channel 1 have their
+ own interrupt line; channels 2-7 share the last interrupt line.
+ * On JZ4725B, channel 0 has its own interrupt; channels 1-5 share one
+ interrupt line; the OST uses the last interrupt line.
+ * on newer SoCs (JZ4750 and above), channel 5 has its own interrupt;
+ channels 0-4 and (if eight channels) 6-7 all share one interrupt line;
+ the OST uses the last interrupt line.
+
+Implementation
+--------------
+
+The functionalities of the TCU hardware are spread across multiple drivers:
+- clocks/irq/timer: drivers/clocksource/ingenic-timer.c
+- PWM: drivers/pwm/pwm-jz4740.c
+- watchdog: drivers/watchdog/jz4740_wdt.c
+- OST: drivers/clocksource/ingenic-ost.c
+
+Because various functionalities of the TCU that belong to different drivers
+and frameworks can be controlled from the same registers, all of these
+drivers access their registers through the same regmap.
+
+For more information regarding the devicetree bindings of the TCU drivers,
+have a look at Documentation/devicetree/bindings/mfd/ingenic,tcu.txt.
--
2.11.0
next prev parent reply other threads:[~2018-08-21 20:37 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-08-21 17:16 [PATCH v7 00/24] TCU patchset v7 Paul Cercueil
2018-08-21 17:16 ` [PATCH v7 01/24] mfd: Add ingenic-tcu.h header Paul Cercueil
2018-09-10 14:58 ` Lee Jones
2018-08-21 17:16 ` [PATCH v7 02/24] dt-bindings: ingenic: Add DT bindings for TCU clocks Paul Cercueil
2018-08-21 17:16 ` Paul Cercueil [this message]
2018-08-21 17:16 ` [PATCH v7 04/24] dt-bindings: Add doc for the Ingenic TCU drivers Paul Cercueil
2018-08-21 17:16 ` [PATCH v7 05/24] clocksource: Add a new timer-ingenic driver Paul Cercueil
2018-08-28 17:23 ` Paul Burton
2018-08-29 9:10 ` Daniel Lezcano
2018-08-29 17:43 ` Paul Burton
2018-09-24 3:12 ` Daniel Lezcano
2018-08-21 17:16 ` [PATCH v7 06/24] clocksource: Add driver for the Ingenic JZ47xx OST Paul Cercueil
2018-08-21 17:16 ` [PATCH v7 07/24] MAINTAINERS: Add myself as maintainer for Ingenic TCU drivers Paul Cercueil
2018-08-21 17:16 ` [PATCH v7 08/24] watchdog: jz4740: Use WDT clock provided by TCU driver Paul Cercueil
2018-08-21 17:16 ` [PATCH v7 09/24] watchdog: jz4740: Use regmap " Paul Cercueil
2018-08-21 17:16 ` [PATCH v7 10/24] watchdog: jz4740: Avoid starting watchdog in set_timeout Paul Cercueil
2018-08-21 17:16 ` [PATCH v7 11/24] watchdog: jz4740: Drop dependency on MACH_JZ47xx, use COMPILE_TEST Paul Cercueil
2018-08-21 17:16 ` [PATCH v7 12/24] pwm: jz4740: Use regmap and clocks from TCU driver Paul Cercueil
2018-08-28 17:30 ` Paul Burton
2018-10-12 10:39 ` Thierry Reding
2018-08-21 17:16 ` [PATCH v7 13/24] pwm: jz4740: Allow selection of PWM channels 0 and 1 Paul Cercueil
2018-10-12 10:40 ` Thierry Reding
2018-10-12 10:43 ` Thierry Reding
2018-08-21 17:16 ` [PATCH v7 14/24] pwm: jz4740: Drop dependency on MACH_INGENIC, use COMPILE_TEST Paul Cercueil
2018-10-12 10:41 ` Thierry Reding
2018-10-12 10:44 ` Thierry Reding
2018-08-21 17:16 ` [PATCH v7 15/24] pwm: jz4740: Remove unused devicetree compatible strings Paul Cercueil
2018-10-12 10:42 ` Thierry Reding
2018-08-21 17:16 ` [PATCH v7 16/24] pwm: jz4740: Add support for the JZ4725B Paul Cercueil
2018-10-12 10:43 ` Thierry Reding
2018-08-21 17:16 ` [PATCH v7 17/24] clk: jz4740: Add TCU clock Paul Cercueil
2018-08-21 17:16 ` [PATCH v7 18/24] MIPS: Kconfig: Select TCU timer driver when MACH_INGENIC is set Paul Cercueil
2018-08-21 17:16 ` [PATCH v7 19/24] MIPS: jz4740: Add DTS nodes for the TCU drivers Paul Cercueil
2018-08-21 17:16 ` [PATCH v7 20/24] MIPS: qi_lb60: Move PWM devices to devicetree Paul Cercueil
2018-08-21 17:18 ` [PATCH v7 21/24] MIPS: qi_lb60: Reduce system timer and clocksource to 750 kHz Paul Cercueil
2018-08-21 17:18 ` [PATCH v7 22/24] MIPS: CI20: Reduce system timer and clocksource to 3 MHz Paul Cercueil
2018-08-21 17:20 ` [PATCH v7 23/24] MIPS: CI20: defconfig: enable OST driver Paul Cercueil
2018-08-21 17:21 ` [PATCH v7 24/24] MIPS: jz4740: Drop obsolete code Paul Cercueil
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