From: Marc Zyngier <maz@kernel.org>
To: <cl@rock-chips.com>
Cc: heiko@sntech.de, robh+dt@kernel.org, jagan@amarulasolutions.com,
wens@csie.org, uwe@kleine-koenig.org, mail@david-bauer.net,
jbx6244@gmail.com, linux-arm-kernel@lists.infradead.org,
linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org,
jensenhuang@friendlyarm.com, michael@amarulasolutions.com,
cnsztl@gmail.com, devicetree@vger.kernel.org,
ulf.hansson@linaro.org, linux-mmc@vger.kernel.org,
gregkh@linuxfoundation.org, linux-serial@vger.kernel.org,
linux-i2c@vger.kernel.org, jay.xu@rock-chips.com,
shawn.lin@rock-chips.com, david.wu@rock-chips.com,
zhangqing@rock-chips.com, huangtao@rock-chips.com,
wim@linux-watchdog.org, linux@roeck-us.net, jamie@jamieiles.com,
linux-watchdog@vger.kernel.org
Subject: Re: [PATCH v2 6/7] arm64: dts: rockchip: add core dtsi for RK3568 SoC
Date: Sun, 25 Apr 2021 11:28:49 +0100 [thread overview]
Message-ID: <87mttmslni.wl-maz@kernel.org> (raw)
In-Reply-To: <20210425094439.25895-1-cl@rock-chips.com>
As I reviewed a previous version of this series, please have the
courtesy of cc'ing me on further revisions of this series.
On Sun, 25 Apr 2021 10:44:39 +0100,
<cl@rock-chips.com> wrote:
>
> From: Liang Chen <cl@rock-chips.com>
>
> RK3568 is a high-performance and low power quad-core application processor
> designed for personal mobile internet device and AIoT equipments. This patch
> add basic core dtsi file for it.
>
> We use scmi_clk for cortex-a55 instead of standard ARMCLK, so that
> kernel/uboot/rtos can change cpu clk with the same code in ATF, and we will
> enalbe a special high-performacne PLL when high frequency is required. The
> smci_clk code is in ATF, and clkid for cpu is 0, as below:
>
> cpu0: cpu@0 {
> device_type = "cpu";
> compatible = "arm,cortex-a55";
> reg = <0x0 0x0>;
> clocks = <&scmi_clk 0>;
> };
>
> Signed-off-by: Liang Chen <cl@rock-chips.com>
> ---
> .../boot/dts/rockchip/rk3568-pinctrl.dtsi | 3119 +++++++++++++++++
> arch/arm64/boot/dts/rockchip/rk3568.dtsi | 812 +++++
> 2 files changed, 3931 insertions(+)
> create mode 100644 arch/arm64/boot/dts/rockchip/rk3568-pinctrl.dtsi
> create mode 100644 arch/arm64/boot/dts/rockchip/rk3568.dtsi
[...]
> diff --git a/arch/arm64/boot/dts/rockchip/rk3568.dtsi b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> new file mode 100644
> index 000000000000..66cb50218ca1
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3568.dtsi
> @@ -0,0 +1,812 @@
[...]
> + timer {
> + compatible = "arm,armv8-timer";
> + interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
> + <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
> + arm,no-tick-in-suspend;
My questions on this property still stand [1].
> + };
> +
> + xin24m: xin24m {
> + compatible = "fixed-clock";
> + clock-frequency = <24000000>;
> + clock-output-names = "xin24m";
> + #clock-cells = <0>;
> + };
> +
> + xin32k: xin32k {
> + compatible = "fixed-clock";
> + clock-frequency = <32768>;
> + clock-output-names = "xin32k";
> + pinctrl-0 = <&clk32k_out0>;
> + pinctrl-names = "default";
> + #clock-cells = <0>;
> + };
> +
> + gic: interrupt-controller@fd400000 {
> + compatible = "arm,gic-v3";
> + reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
> + <0x0 0xfd460000 0 0xc0000>; /* GICR */
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
My request for a full description of the GICA region still stands [1].
Thanks,
M.
[1] https://lore.kernel.org/r/87o8e2sm1u.wl-maz@kernel.org
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2021-04-25 10:28 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-04-25 9:42 [PATCH v2 0/7] arm64: dts: rockchip: add basic dtsi/dts files for RK3568 SoC cl
2021-04-25 9:42 ` [PATCH v2 1/7] dt-bindings: i2c: i2c-rk3x: add description for rk3568 cl
2021-04-25 9:42 ` [PATCH v2 2/7] dt-bindings: serial: snps-dw-apb-uart: " cl
2021-04-25 9:42 ` [PATCH v2 3/7] dt-bindings: mmc: rockchip-dw-mshc: " cl
2021-04-25 9:42 ` [PATCH v2 4/7] dt-bindings: watchdog: dw-wdt: " cl
2021-04-25 9:44 ` [PATCH v2 5/7] arm64: dts: rockchip: add generic pinconfig settings used by most Rockchip socs cl
2021-04-25 9:44 ` [PATCH v2 6/7] arm64: dts: rockchip: add core dtsi for RK3568 SoC cl
2021-04-25 10:28 ` Marc Zyngier [this message]
2021-04-26 9:21 ` 陈亮
2021-04-26 12:16 ` Johan Jonker
2021-04-27 3:45 ` Kever Yang
2021-04-27 7:48 ` Heiko Stübner
2021-04-27 7:41 ` Johan Jonker
2021-04-27 8:07 ` Heiko Stübner
2021-04-28 3:51 ` 陈亮
2021-04-25 9:44 ` [PATCH v2 7/7] arm64: dts: rockchip: add basic dts for RK3568 EVB cl
2021-04-27 7:50 ` Heiko Stübner
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