From: Rob Herring <robh@kernel.org>
To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: Mark Rutland <mark.rutland@arm.com>,
Kumar Gala <kumar.gala@linaro.org>,
arm@kernel.org, Sean Hudson <darknighte@darknighte.com>,
Frank Rowand <frowand.list@gmail.com>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Grant Likely <grant.likely@arm.com>,
Thomas Gleixner <tglx@linutronix.de>,
linuxppc-dev@lists.ozlabs.org,
linux-arm-kernel@lists.infradead.org
Subject: [PATCH v2 06/34] dt-bindings: timer: Convert ARM timer bindings to json-schema
Date: Mon, 3 Dec 2018 15:31:55 -0600 [thread overview]
Message-ID: <20181203213223.16986-7-robh@kernel.org> (raw)
In-Reply-To: <20181203213223.16986-1-robh@kernel.org>
Convert ARM timers to DT schema format using json-schema.
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Rob Herring <robh@kernel.org>
---
.../bindings/timer/arm,arch_timer.txt | 112 ----------------
.../bindings/timer/arm,arch_timer.yaml | 103 +++++++++++++++
.../bindings/timer/arm,arch_timer_mmio.yaml | 120 ++++++++++++++++++
.../bindings/timer/arm,global_timer.txt | 27 ----
.../bindings/timer/arm,global_timer.yaml | 46 +++++++
5 files changed, 269 insertions(+), 139 deletions(-)
delete mode 100644 Documentation/devicetree/bindings/timer/arm,arch_timer.txt
create mode 100644 Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
create mode 100644 Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml
delete mode 100644 Documentation/devicetree/bindings/timer/arm,global_timer.txt
create mode 100644 Documentation/devicetree/bindings/timer/arm,global_timer.yaml
diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer.txt b/Documentation/devicetree/bindings/timer/arm,arch_timer.txt
deleted file mode 100644
index 68301b77e854..000000000000
--- a/Documentation/devicetree/bindings/timer/arm,arch_timer.txt
+++ /dev/null
@@ -1,112 +0,0 @@
-* ARM architected timer
-
-ARM cores may have a per-core architected timer, which provides per-cpu timers,
-or a memory mapped architected timer, which provides up to 8 frames with a
-physical and optional virtual timer per frame.
-
-The per-core architected timer is attached to a GIC to deliver its
-per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
-to deliver its interrupts via SPIs.
-
-** CP15 Timer node properties:
-
-- compatible : Should at least contain one of
- "arm,armv7-timer"
- "arm,armv8-timer"
-
-- interrupts : Interrupt list for secure, non-secure, virtual and
- hypervisor timers, in that order.
-
-- clock-frequency : The frequency of the main counter, in Hz. Should be present
- only where necessary to work around broken firmware which does not configure
- CNTFRQ on all CPUs to a uniform correct value. Use of this property is
- strongly discouraged; fix your firmware unless absolutely impossible.
-
-- always-on : a boolean property. If present, the timer is powered through an
- always-on power domain, therefore it never loses context.
-
-- fsl,erratum-a008585 : A boolean property. Indicates the presence of
- QorIQ erratum A-008585, which says that reading the counter is
- unreliable unless the same value is returned by back-to-back reads.
- This also affects writes to the tval register, due to the implicit
- counter read.
-
-- hisilicon,erratum-161010101 : A boolean property. Indicates the
- presence of Hisilicon erratum 161010101, which says that reading the
- counters is unreliable in some cases, and reads may return a value 32
- beyond the correct value. This also affects writes to the tval
- registers, due to the implicit counter read.
-
-** Optional properties:
-
-- arm,cpu-registers-not-fw-configured : Firmware does not initialize
- any of the generic timer CPU registers, which contain their
- architecturally-defined reset values. Only supported for 32-bit
- systems which follow the ARMv7 architected reset values.
-
-- arm,no-tick-in-suspend : The main counter does not tick when the system is in
- low-power system suspend on some SoCs. This behavior does not match the
- Architecture Reference Manual's specification that the system counter "must
- be implemented in an always-on power domain."
-
-
-Example:
-
- timer {
- compatible = "arm,cortex-a15-timer",
- "arm,armv7-timer";
- interrupts = <1 13 0xf08>,
- <1 14 0xf08>,
- <1 11 0xf08>,
- <1 10 0xf08>;
- clock-frequency = <100000000>;
- };
-
-** Memory mapped timer node properties:
-
-- compatible : Should at least contain "arm,armv7-timer-mem".
-
-- clock-frequency : The frequency of the main counter, in Hz. Should be present
- only when firmware has not configured the MMIO CNTFRQ registers.
-
-- reg : The control frame base address.
-
-Note that #address-cells, #size-cells, and ranges shall be present to ensure
-the CPU can address a frame's registers.
-
-A timer node has up to 8 frame sub-nodes, each with the following properties:
-
-- frame-number: 0 to 7.
-
-- interrupts : Interrupt list for physical and virtual timers in that order.
- The virtual timer interrupt is optional.
-
-- reg : The first and second view base addresses in that order. The second view
- base address is optional.
-
-- status : "disabled" indicates the frame is not available for use. Optional.
-
-Example:
-
- timer@f0000000 {
- compatible = "arm,armv7-timer-mem";
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- reg = <0xf0000000 0x1000>;
- clock-frequency = <50000000>;
-
- frame@f0001000 {
- frame-number = <0>
- interrupts = <0 13 0x8>,
- <0 14 0x8>;
- reg = <0xf0001000 0x1000>,
- <0xf0002000 0x1000>;
- };
-
- frame@f0003000 {
- frame-number = <1>
- interrupts = <0 15 0x8>;
- reg = <0xf0003000 0x1000>;
- };
- };
diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
new file mode 100644
index 000000000000..6deead07728e
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/arm,arch_timer.yaml
@@ -0,0 +1,103 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/arm,arch_timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM architected timer
+
+maintainers:
+ - Marc Zyngier <marc.zyngier@arm.com>
+ - Mark Rutland <mark.rutland@arm.com>
+description: |+
+ ARM cores may have a per-core architected timer, which provides per-cpu timers,
+ or a memory mapped architected timer, which provides up to 8 frames with a
+ physical and optional virtual timer per frame.
+
+ The per-core architected timer is attached to a GIC to deliver its
+ per-processor interrupts via PPIs. The memory mapped timer is attached to a GIC
+ to deliver its interrupts via SPIs.
+
+properties:
+ compatible:
+ oneOf:
+ - items:
+ - enum:
+ - arm,cortex-a15-timer
+ - enum:
+ - arm,armv7-timer
+ - items:
+ - enum:
+ - arm,armv7-timer
+ - items:
+ - enum:
+ - arm,armv8-timer
+
+ interrupts:
+ items:
+ - description: secure timer irq
+ - description: non-secure timer irq
+ - description: virtual timer irq
+ - description: hypervisor timer irq
+
+ clock-frequency:
+ description: The frequency of the main counter, in Hz. Should be present
+ only where necessary to work around broken firmware which does not configure
+ CNTFRQ on all CPUs to a uniform correct value. Use of this property is
+ strongly discouraged; fix your firmware unless absolutely impossible.
+
+ always-on:
+ type: boolean
+ description: If present, the timer is powered through an always-on power
+ domain, therefore it never loses context.
+
+ fsl,erratum-a008585:
+ type: boolean
+ description: Indicates the presence of QorIQ erratum A-008585, which says
+ that reading the counter is unreliable unless the same value is returned
+ by back-to-back reads. This also affects writes to the tval register, due
+ to the implicit counter read.
+
+ hisilicon,erratum-161010101:
+ type: boolean
+ description: Indicates the presence of Hisilicon erratum 161010101, which
+ says that reading the counters is unreliable in some cases, and reads may
+ return a value 32 beyond the correct value. This also affects writes to
+ the tval registers, due to the implicit counter read.
+
+ arm,cpu-registers-not-fw-configured:
+ type: boolean
+ description: Firmware does not initialize any of the generic timer CPU
+ registers, which contain their architecturally-defined reset values. Only
+ supported for 32-bit systems which follow the ARMv7 architected reset
+ values.
+
+ arm,no-tick-in-suspend:
+ type: boolean
+ description: The main counter does not tick when the system is in
+ low-power system suspend on some SoCs. This behavior does not match the
+ Architecture Reference Manual's specification that the system counter "must
+ be implemented in an always-on power domain."
+
+required:
+ - compatible
+
+oneOf:
+ - required:
+ - interrupts
+ - required:
+ - interrupts-extended
+
+examples:
+ - |
+ timer {
+ compatible = "arm,cortex-a15-timer",
+ "arm,armv7-timer";
+ interrupts = <1 13 0xf08>,
+ <1 14 0xf08>,
+ <1 11 0xf08>,
+ <1 10 0xf08>;
+ clock-frequency = <100000000>;
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml b/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml
new file mode 100644
index 000000000000..c4ab59550fc2
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/arm,arch_timer_mmio.yaml
@@ -0,0 +1,120 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/arm,arch_timer_mmio.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM memory mapped architected timer
+
+maintainers:
+ - Marc Zyngier <marc.zyngier@arm.com>
+ - Mark Rutland <mark.rutland@arm.com>
+
+description: |+
+ ARM cores may have a memory mapped architected timer, which provides up to 8
+ frames with a physical and optional virtual timer per frame.
+
+ The memory mapped timer is attached to a GIC to deliver its interrupts via SPIs.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - arm,armv7-timer-mem
+
+ reg:
+ maxItems: 1
+ description: The control frame base address
+
+ '#address-cells':
+ enum: [1, 2]
+
+ '#size-cells':
+ const: 1
+
+ clock-frequency:
+ description: The frequency of the main counter, in Hz. Should be present
+ only where necessary to work around broken firmware which does not configure
+ CNTFRQ on all CPUs to a uniform correct value. Use of this property is
+ strongly discouraged; fix your firmware unless absolutely impossible.
+
+ always-on:
+ type: boolean
+ description: If present, the timer is powered through an always-on power
+ domain, therefore it never loses context.
+
+ arm,cpu-registers-not-fw-configured:
+ type: boolean
+ description: Firmware does not initialize any of the generic timer CPU
+ registers, which contain their architecturally-defined reset values. Only
+ supported for 32-bit systems which follow the ARMv7 architected reset
+ values.
+
+ arm,no-tick-in-suspend:
+ type: boolean
+ description: The main counter does not tick when the system is in
+ low-power system suspend on some SoCs. This behavior does not match the
+ Architecture Reference Manual's specification that the system counter "must
+ be implemented in an always-on power domain."
+
+patternProperties:
+ '^frame@[0-9a-z]*$':
+ description: A timer node has up to 8 frame sub-nodes, each with the following properties.
+ properties:
+ frame-number:
+ allOf:
+ - $ref: "/schemas/types.yaml#/definitions/uint32"
+ - minimum: 0
+ maximum: 7
+
+ interrupts:
+ minItems: 1
+ maxItems: 2
+ items:
+ - description: physical timer irq
+ - description: virtual timer irq
+
+ reg :
+ minItems: 1
+ maxItems: 2
+ items:
+ - description: 1st view base address
+ - description: 2nd optional view base address
+
+ required:
+ - frame-number
+ - interrupts
+ - reg
+
+required:
+ - compatible
+ - reg
+ - '#address-cells'
+ - '#size-cells'
+
+examples:
+ - |
+ timer@f0000000 {
+ compatible = "arm,armv7-timer-mem";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges;
+ reg = <0xf0000000 0x1000>;
+ clock-frequency = <50000000>;
+
+ frame@f0001000 {
+ frame-number = <0>;
+ interrupts = <0 13 0x8>,
+ <0 14 0x8>;
+ reg = <0xf0001000 0x1000>,
+ <0xf0002000 0x1000>;
+ };
+
+ frame@f0003000 {
+ frame-number = <1>;
+ interrupts = <0 15 0x8>;
+ reg = <0xf0003000 0x1000>;
+ };
+ };
+
+...
diff --git a/Documentation/devicetree/bindings/timer/arm,global_timer.txt b/Documentation/devicetree/bindings/timer/arm,global_timer.txt
deleted file mode 100644
index bdae3a818793..000000000000
--- a/Documentation/devicetree/bindings/timer/arm,global_timer.txt
+++ /dev/null
@@ -1,27 +0,0 @@
-
-* ARM Global Timer
- Cortex-A9 are often associated with a per-core Global timer.
-
-** Timer node required properties:
-
-- compatible : should contain
- * "arm,cortex-a5-global-timer" for Cortex-A5 global timers.
- * "arm,cortex-a9-global-timer" for Cortex-A9 global
- timers or any compatible implementation. Note: driver
- supports versions r2p0 and above.
-
-- interrupts : One interrupt to each core
-
-- reg : Specify the base address and the size of the GT timer
- register window.
-
-- clocks : Should be phandle to a clock.
-
-Example:
-
- timer@2c000600 {
- compatible = "arm,cortex-a9-global-timer";
- reg = <0x2c000600 0x20>;
- interrupts = <1 13 0xf01>;
- clocks = <&arm_periph_clk>;
- };
diff --git a/Documentation/devicetree/bindings/timer/arm,global_timer.yaml b/Documentation/devicetree/bindings/timer/arm,global_timer.yaml
new file mode 100644
index 000000000000..21c24a8e28fd
--- /dev/null
+++ b/Documentation/devicetree/bindings/timer/arm,global_timer.yaml
@@ -0,0 +1,46 @@
+# SPDX-License-Identifier: GPL-2.0
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/timer/arm,global_timer.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: ARM Global Timer
+
+maintainers:
+ - Stuart Menefy <stuart.menefy@st.com>
+
+description:
+ Cortex-A9 are often associated with a per-core Global timer.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - arm,cortex-a5-global-timer
+ - arm,cortex-a9-global-timer
+
+ description: driver supports versions r2p0 and above.
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+required:
+ - compatible
+ - reg
+ - clocks
+
+examples:
+ - |
+ timer@2c000600 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x2c000600 0x20>;
+ interrupts = <1 13 0xf01>;
+ clocks = <&arm_periph_clk>;
+ };
+...
--
2.19.1
next prev parent reply other threads:[~2018-12-03 21:48 UTC|newest]
Thread overview: 84+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-12-03 21:31 [PATCH v2 00/34] Devicetree schema Rob Herring
2018-12-03 21:31 ` [PATCH v2 01/34] kbuild: Add support for DT binding schema checks Rob Herring
2018-12-08 4:47 ` Masahiro Yamada
2018-12-10 15:55 ` Rob Herring
2018-12-03 21:31 ` [PATCH v2 02/34] dt-bindings: Add a writing DT schemas how-to and annotated example Rob Herring
2018-12-03 21:31 ` [PATCH v2 03/34] dt-bindings: Convert trivial-devices.txt to json-schema Rob Herring
2018-12-03 21:31 ` [PATCH v2 04/34] dt-bindings: altera: Convert clkmgr binding " Rob Herring
2018-12-05 15:13 ` Dinh Nguyen
2018-12-03 21:31 ` [PATCH v2 05/34] dt-bindings: i2c: Convert i2c-gpio " Rob Herring
2018-12-03 21:31 ` Rob Herring [this message]
2018-12-03 21:31 ` [PATCH v2 07/34] dt-bindings: arm: Convert cpu " Rob Herring
2018-12-03 21:31 ` [PATCH v2 08/34] dt-bindings: arm: Convert PMU " Rob Herring
2018-12-05 10:08 ` Will Deacon
2018-12-05 15:42 ` Rob Herring
2018-12-06 14:37 ` Will Deacon
2018-12-03 21:31 ` [PATCH v2 09/34] dt-bindings: arm: Convert primecell " Rob Herring
2018-12-03 21:31 ` [PATCH v2 10/34] dt-bindings: arm: Convert Actions Semi bindings to jsonschema Rob Herring
2019-01-14 10:26 ` Manivannan Sadhasivam
2018-12-03 21:32 ` [PATCH v2 11/34] dt-bindings: arm: Convert Alpine board/soc bindings to json-schema Rob Herring
2018-12-04 7:53 ` Antoine Tenart
2018-12-03 21:32 ` [PATCH v2 12/34] dt-bindings: arm: Convert Altera " Rob Herring
2018-12-05 15:13 ` Dinh Nguyen
2018-12-03 21:32 ` [PATCH v2 13/34] dt-bindings: arm: amlogic: Move 'amlogic, meson-gx-ao-secure' binding to its own file Rob Herring
2018-12-04 8:31 ` Neil Armstrong
2018-12-05 1:01 ` Kevin Hilman
2018-12-05 4:18 ` [PATCH v2 13/34] dt-bindings: arm: amlogic: Move 'amlogic,meson-gx-ao-secure' " Rob Herring
2019-01-09 16:12 ` Rob Herring
2018-12-03 21:32 ` [PATCH v2 14/34] dt-bindings: arm: Convert Amlogic board/soc bindings to json-schema Rob Herring
2018-12-04 8:39 ` Neil Armstrong
2018-12-04 14:44 ` Rob Herring
2018-12-06 21:27 ` Rob Herring
2018-12-03 21:32 ` [PATCH v2 15/34] dt-bindings: arm: Convert Atmel " Rob Herring
2018-12-04 8:12 ` Nicolas.Ferre
2018-12-04 22:48 ` Rob Herring
2018-12-03 21:32 ` [PATCH v2 16/34] dt-bindings: arm: Convert Calxeda " Rob Herring
2018-12-03 21:32 ` [PATCH v2 17/34] dt-bindings: arm: Convert TI davinci " Rob Herring
2018-12-06 10:28 ` Sekhar Nori
2018-12-03 21:32 ` [PATCH v2 18/34] dt-bindings: arm: Convert FSL " Rob Herring
2018-12-06 2:31 ` Shawn Guo
2018-12-06 23:33 ` Rob Herring
2018-12-08 1:58 ` Shawn Guo
2019-01-10 6:42 ` Shawn Guo
2019-01-10 10:44 ` Vokáč Michal
2019-01-10 13:44 ` Shawn Guo
2018-12-03 21:32 ` [PATCH v2 19/34] dt-bindings: arm: Convert MediaTek " Rob Herring
2018-12-03 21:32 ` [PATCH v2 20/34] dt-bindings: arm: Convert TI nspire " Rob Herring
2018-12-03 21:32 ` [PATCH v2 21/34] dt-bindings: arm: Convert Oxford Semi " Rob Herring
2018-12-04 8:43 ` Neil Armstrong
2018-12-04 14:04 ` Rob Herring
2018-12-03 21:32 ` [PATCH v2 22/34] dt-bindings: arm: Convert QCom " Rob Herring
2018-12-05 18:31 ` Andy Gross
2018-12-03 21:32 ` [PATCH v2 23/34] dt-bindings: arm: Convert Realtek " Rob Herring
2018-12-03 21:32 ` [PATCH v2 24/34] dt-bindings: arm: Convert Rockchip " Rob Herring
2018-12-04 14:16 ` Heiko Stuebner
2018-12-04 15:04 ` Rob Herring
2018-12-09 22:14 ` [PATCH v2.1 " Heiko Stuebner
2018-12-10 9:54 ` Heiko Stuebner
2018-12-10 15:13 ` Rob Herring
2018-12-10 22:45 ` [PATCH v2.2 " Heiko Stuebner
2018-12-11 15:21 ` Rob Herring
2018-12-03 21:32 ` [PATCH v2 25/34] dt-bindings: arm: renesas: Move 'renesas, prr' binding to its own doc Rob Herring
2018-12-04 14:44 ` [PATCH v2 25/34] dt-bindings: arm: renesas: Move 'renesas,prr' " Simon Horman
2018-12-04 14:56 ` Geert Uytterhoeven
2018-12-03 21:32 ` [PATCH v2 26/34] dt-bindings: arm: Convert Renesas board/soc bindings to json-schema Rob Herring
2018-12-04 14:48 ` Simon Horman
2018-12-04 14:57 ` Geert Uytterhoeven
2018-12-04 15:08 ` Rob Herring
2018-12-05 19:44 ` Simon Horman
2018-12-06 19:38 ` Rob Herring
2018-12-10 11:12 ` Simon Horman
2018-12-03 21:32 ` [PATCH v2 27/34] dt-bindings: arm: Convert CSR SiRF " Rob Herring
2018-12-03 21:32 ` [PATCH v2 28/34] dt-bindings: arm: Convert SPEAr " Rob Herring
2018-12-04 4:50 ` Viresh Kumar
2018-12-03 21:32 ` [PATCH v2 29/34] dt-bindings: arm: Convert ST STi " Rob Herring
2018-12-04 8:10 ` Patrice CHOTARD
2018-12-03 21:32 ` [PATCH v2 30/34] dt-bindings: arm: Convert Tegra " Rob Herring
2018-12-04 8:50 ` Thierry Reding
2018-12-06 22:38 ` Rob Herring
2018-12-07 11:46 ` Thierry Reding
2018-12-03 21:32 ` [PATCH v2 31/34] dt-bindings: arm: Convert VIA " Rob Herring
2018-12-03 21:32 ` [PATCH v2 32/34] dt-bindings: arm: Convert Xilinx " Rob Herring
2018-12-03 21:32 ` [PATCH v2 33/34] dt-bindings: arm: Add missing Xilinx boards Rob Herring
2018-12-03 21:32 ` [PATCH v2 34/34] dt-bindings: arm: Convert ZTE board/soc bindings to json-schema Rob Herring
2018-12-06 2:33 ` Shawn Guo
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20181203213223.16986-7-robh@kernel.org \
--to=robh@kernel.org \
--cc=arm@kernel.org \
--cc=daniel.lezcano@linaro.org \
--cc=darknighte@darknighte.com \
--cc=devicetree@vger.kernel.org \
--cc=frowand.list@gmail.com \
--cc=grant.likely@arm.com \
--cc=kumar.gala@linaro.org \
--cc=linux-arm-kernel@lists.infradead.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linuxppc-dev@lists.ozlabs.org \
--cc=mark.rutland@arm.com \
--cc=tglx@linutronix.de \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).