From: Michael Ellerman <patch-notifications@ellerman.id.au>
To: Michael Neuling <mikey@neuling.org>
Cc: mikey@neuling.org, linuxppc-dev@lists.ozlabs.org,
kvm-ppc@vger.kernel.org, sjitindarsingh@gmail.com
Subject: Re: [PATCH] KVM: PPC: Book3S HV: Fix CR0 setting in TM emulation
Date: Mon, 8 Jul 2019 11:19:42 +1000 (AEST) [thread overview]
Message-ID: <45hng26v5bz9sP6@ozlabs.org> (raw)
In-Reply-To: <20190620060040.26945-1-mikey@neuling.org>
On Thu, 2019-06-20 at 06:00:40 UTC, Michael Neuling wrote:
> When emulating tsr, treclaim and trechkpt, we incorrectly set CR0. The
> code currently sets:
> CR0 <- 00 || MSR[TS]
> but according to the ISA it should be:
> CR0 <- 0 || MSR[TS] || 0
>
> This fixes the bit shift to put the bits in the correct location.
>
> Tested-by: Suraj Jitindar Singh <sjitindarsingh@gmail.com>
> Signed-off-by: Michael Neuling <mikey@neuling.org>
Applied to powerpc next, thanks.
https://git.kernel.org/powerpc/c/3fefd1cd95df04da67c83c1cb93b663f04b3324f
cheers
prev parent reply other threads:[~2019-07-08 1:56 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-06-20 6:00 [PATCH] KVM: PPC: Book3S HV: Fix CR0 setting in TM emulation Michael Neuling
2019-06-24 11:48 ` Michael Ellerman
2019-06-25 4:11 ` Michael Neuling
2019-07-08 1:19 ` Michael Ellerman [this message]
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