* [PATCH V7 1/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings
@ 2015-11-20 2:10 Chen Feng
2015-11-20 2:10 ` [PATCH V7 2/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC Chen Feng
` (2 more replies)
0 siblings, 3 replies; 5+ messages in thread
From: Chen Feng @ 2015-11-20 2:10 UTC (permalink / raw)
To: puck.chen, p.zabel, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, devicetree, linux-kernel, xuwei5
Cc: puck.chen, w.f
Add DT bindings documentation for hi6220 SoC reset controller.
Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
---
.../bindings/reset/hisilicon,hi6220-reset.txt | 34 +++++++++++
include/dt-bindings/reset/hisi,hi6220-resets.h | 67 ++++++++++++++++++++++
2 files changed, 101 insertions(+)
create mode 100644 Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
create mode 100644 include/dt-bindings/reset/hisi,hi6220-resets.h
diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
new file mode 100644
index 0000000..e0b185a
--- /dev/null
+++ b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
@@ -0,0 +1,34 @@
+Hisilicon System Reset Controller
+======================================
+
+Please also refer to reset.txt in this directory for common reset
+controller binding usage.
+
+The reset controller registers are part of the system-ctl block on
+hi6220 SoC.
+
+Required properties:
+- compatible: may be "hisilicon,hi6220-sysctrl"
+- reg: should be register base and length as documented in the
+ datasheet
+- #reset-cells: 1, see below
+
+Example:
+sys_ctrl: sys_ctrl@f7030000 {
+ compatible = "hisilicon,hi6220-sysctrl", "syscon";
+ reg = <0x0 0xf7030000 0x0 0x2000>;
+ #clock-cells = <1>;
+ #reset-cells = <1>;
+};
+
+Specifying reset lines connected to IP modules
+==============================================
+example:
+
+ uart1: serial@..... {
+ ...
+ resets = <&sys_ctrl PERIPH_RSTEN3_UART1>;
+ ...
+ };
+
+The index could be found in <dt-bindings/reset/hisi,hi6220-resets.h>.
diff --git a/include/dt-bindings/reset/hisi,hi6220-resets.h b/include/dt-bindings/reset/hisi,hi6220-resets.h
new file mode 100644
index 0000000..ca08a7e
--- /dev/null
+++ b/include/dt-bindings/reset/hisi,hi6220-resets.h
@@ -0,0 +1,67 @@
+/**
+ * This header provides index for the reset controller
+ * based on hi6220 SoC.
+ */
+#ifndef _DT_BINDINGS_RESET_CONTROLLER_HI6220
+#define _DT_BINDINGS_RESET_CONTROLLER_HI6220
+
+#define PERIPH_RSTDIS0_MMC0 0x000
+#define PERIPH_RSTDIS0_MMC1 0x001
+#define PERIPH_RSTDIS0_MMC2 0x002
+#define PERIPH_RSTDIS0_NANDC 0x003
+#define PERIPH_RSTDIS0_USBOTG_BUS 0x004
+#define PERIPH_RSTDIS0_POR_PICOPHY 0x005
+#define PERIPH_RSTDIS0_USBOTG 0x006
+#define PERIPH_RSTDIS0_USBOTG_32K 0x007
+#define PERIPH_RSTDIS1_HIFI 0x100
+#define PERIPH_RSTDIS1_DIGACODEC 0x105
+#define PERIPH_RSTEN2_IPF 0x200
+#define PERIPH_RSTEN2_SOCP 0x201
+#define PERIPH_RSTEN2_DMAC 0x202
+#define PERIPH_RSTEN2_SECENG 0x203
+#define PERIPH_RSTEN2_ABB 0x204
+#define PERIPH_RSTEN2_HPM0 0x205
+#define PERIPH_RSTEN2_HPM1 0x206
+#define PERIPH_RSTEN2_HPM2 0x207
+#define PERIPH_RSTEN2_HPM3 0x208
+#define PERIPH_RSTEN3_CSSYS 0x300
+#define PERIPH_RSTEN3_I2C0 0x301
+#define PERIPH_RSTEN3_I2C1 0x302
+#define PERIPH_RSTEN3_I2C2 0x303
+#define PERIPH_RSTEN3_I2C3 0x304
+#define PERIPH_RSTEN3_UART1 0x305
+#define PERIPH_RSTEN3_UART2 0x306
+#define PERIPH_RSTEN3_UART3 0x307
+#define PERIPH_RSTEN3_UART4 0x308
+#define PERIPH_RSTEN3_SSP 0x309
+#define PERIPH_RSTEN3_PWM 0x30a
+#define PERIPH_RSTEN3_BLPWM 0x30b
+#define PERIPH_RSTEN3_TSENSOR 0x30c
+#define PERIPH_RSTEN3_DAPB 0x312
+#define PERIPH_RSTEN3_HKADC 0x313
+#define PERIPH_RSTEN3_CODEC_SSI 0x314
+#define PERIPH_RSTEN3_PMUSSI1 0x316
+#define PERIPH_RSTEN8_RS0 0x400
+#define PERIPH_RSTEN8_RS2 0x401
+#define PERIPH_RSTEN8_RS3 0x402
+#define PERIPH_RSTEN8_MS0 0x403
+#define PERIPH_RSTEN8_MS2 0x405
+#define PERIPH_RSTEN8_XG2RAM0 0x406
+#define PERIPH_RSTEN8_X2SRAM_TZMA 0x407
+#define PERIPH_RSTEN8_SRAM 0x408
+#define PERIPH_RSTEN8_HARQ 0x40a
+#define PERIPH_RSTEN8_DDRC 0x40c
+#define PERIPH_RSTEN8_DDRC_APB 0x40d
+#define PERIPH_RSTEN8_DDRPACK_APB 0x40e
+#define PERIPH_RSTEN8_DDRT 0x411
+#define PERIPH_RSDIST9_CARM_DAP 0x500
+#define PERIPH_RSDIST9_CARM_ATB 0x501
+#define PERIPH_RSDIST9_CARM_LBUS 0x502
+#define PERIPH_RSDIST9_CARM_POR 0x503
+#define PERIPH_RSDIST9_CARM_CORE 0x504
+#define PERIPH_RSDIST9_CARM_DBG 0x505
+#define PERIPH_RSDIST9_CARM_L2 0x506
+#define PERIPH_RSDIST9_CARM_SOCDBG 0x507
+#define PERIPH_RSDIST9_CARM_ETM 0x508
+
+#endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH V7 2/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC
2015-11-20 2:10 [PATCH V7 1/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings Chen Feng
@ 2015-11-20 2:10 ` Chen Feng
2015-11-20 8:40 ` Philipp Zabel
2015-11-20 2:10 ` [PATCH V7 3/3] arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC Chen Feng
2015-11-20 14:15 ` [PATCH V7 1/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings Rob Herring
2 siblings, 1 reply; 5+ messages in thread
From: Chen Feng @ 2015-11-20 2:10 UTC (permalink / raw)
To: puck.chen, p.zabel, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, devicetree, linux-kernel, xuwei5
Cc: puck.chen, w.f
Add reset driver for hi6220-hikey board,this driver supply deassert
of IP on hi6220 SoC.
Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
---
drivers/reset/Kconfig | 1 +
drivers/reset/Makefile | 1 +
drivers/reset/hisilicon/Kconfig | 5 ++
drivers/reset/hisilicon/Makefile | 1 +
drivers/reset/hisilicon/hi6220_reset.c | 108 +++++++++++++++++++++++++++++++++
5 files changed, 116 insertions(+)
create mode 100644 drivers/reset/hisilicon/Kconfig
create mode 100644 drivers/reset/hisilicon/Makefile
create mode 100644 drivers/reset/hisilicon/hi6220_reset.c
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 0615f50..df37212 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -13,3 +13,4 @@ menuconfig RESET_CONTROLLER
If unsure, say no.
source "drivers/reset/sti/Kconfig"
+source "drivers/reset/hisilicon/Kconfig"
diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index 85d5904..99e18c8 100644
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -4,5 +4,6 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o
obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o
obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o
obj-$(CONFIG_ARCH_STI) += sti/
+obj-$(CONFIG_ARCH_HISI) += hisilicon/
obj-$(CONFIG_ARCH_ZYNQ) += reset-zynq.o
obj-$(CONFIG_ATH79) += reset-ath79.o
diff --git a/drivers/reset/hisilicon/Kconfig b/drivers/reset/hisilicon/Kconfig
new file mode 100644
index 0000000..26bf95a
--- /dev/null
+++ b/drivers/reset/hisilicon/Kconfig
@@ -0,0 +1,5 @@
+config COMMON_RESET_HI6220
+ tristate "Hi6220 Reset Driver"
+ depends on (ARCH_HISI && RESET_CONTROLLER)
+ help
+ Build the Hisilicon Hi6220 reset driver.
diff --git a/drivers/reset/hisilicon/Makefile b/drivers/reset/hisilicon/Makefile
new file mode 100644
index 0000000..c932f86
--- /dev/null
+++ b/drivers/reset/hisilicon/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_COMMON_RESET_HI6220) += hi6220_reset.o
diff --git a/drivers/reset/hisilicon/hi6220_reset.c b/drivers/reset/hisilicon/hi6220_reset.c
new file mode 100644
index 0000000..d17c910
--- /dev/null
+++ b/drivers/reset/hisilicon/hi6220_reset.c
@@ -0,0 +1,108 @@
+/*
+ * Hisilicon Hi6220 reset controller driver
+ *
+ * Copyright (c) 2015 Hisilicon Limited.
+ *
+ * Author: Feng Chen <puck.chen@hisilicon.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
+#include <linux/io.h>
+#include <linux/init.h>
+#include <linux/bitops.h>
+#include <linux/of.h>
+#include <linux/reset-controller.h>
+#include <linux/reset.h>
+#include <linux/platform_device.h>
+
+#define ASSERT_OFFSET 0x300
+#define DEASSERT_OFFSET 0x304
+#define MAX_INDEX 0x509
+
+#define to_reset_data(x) container_of(x, struct hi6220_reset_data, rc_dev)
+
+struct hi6220_reset_data {
+ void __iomem *assert_base;
+ void __iomem *deassert_base;
+ struct reset_controller_dev rc_dev;
+};
+
+static int hi6220_reset_assert(struct reset_controller_dev *rc_dev,
+ unsigned long idx)
+{
+ struct hi6220_reset_data *data = to_reset_data(rc_dev);
+
+ int bank = idx >> 8;
+ int offset = idx & 0xff;
+
+ writel(BIT(offset), data->assert_base + (bank * 0x10));
+
+ return 0;
+}
+
+static int hi6220_reset_deassert(struct reset_controller_dev *rc_dev,
+ unsigned long idx)
+{
+ struct hi6220_reset_data *data = to_reset_data(rc_dev);
+
+ int bank = idx >> 8;
+ int offset = idx & 0xff;
+
+ writel(BIT(offset), data->deassert_base + (bank * 0x10));
+
+ return 0;
+}
+
+static struct reset_control_ops hi6220_reset_ops = {
+ .assert = hi6220_reset_assert,
+ .deassert = hi6220_reset_deassert,
+};
+
+static int hi6220_reset_probe(struct platform_device *pdev)
+{
+ struct hi6220_reset_data *data;
+ struct resource *res;
+ void __iomem *src_base;
+
+ data = devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return -ENOMEM;
+
+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+ src_base = devm_ioremap_resource(&pdev->dev, res);
+ if (IS_ERR(src_base))
+ return PTR_ERR(src_base);
+
+ data->assert_base = src_base + ASSERT_OFFSET;
+ data->deassert_base = src_base + DEASSERT_OFFSET;
+ data->rc_dev.nr_resets = MAX_INDEX;
+ data->rc_dev.ops = &hi6220_reset_ops;
+ data->rc_dev.of_node = pdev->dev.of_node;
+
+ reset_controller_register(&data->rc_dev);
+
+ return 0;
+}
+
+static const struct of_device_id hi6220_reset_match[] = {
+ { .compatible = "hisilicon,hi6220-sysctrl" },
+ { },
+};
+
+static struct platform_driver hi6220_reset_driver = {
+ .probe = hi6220_reset_probe,
+ .driver = {
+ .name = "reset-hi6220",
+ .of_match_table = hi6220_reset_match,
+ },
+};
+
+static int __init hi6220_reset_init(void)
+{
+ return platform_driver_register(&hi6220_reset_driver);
+}
+
+postcore_initcall(hi6220_reset_init);
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH V7 3/3] arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC
2015-11-20 2:10 [PATCH V7 1/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings Chen Feng
2015-11-20 2:10 ` [PATCH V7 2/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC Chen Feng
@ 2015-11-20 2:10 ` Chen Feng
2015-11-20 14:15 ` [PATCH V7 1/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings Rob Herring
2 siblings, 0 replies; 5+ messages in thread
From: Chen Feng @ 2015-11-20 2:10 UTC (permalink / raw)
To: puck.chen, p.zabel, robh+dt, pawel.moll, mark.rutland,
ijc+devicetree, galak, devicetree, linux-kernel, xuwei5
Cc: puck.chen, w.f
Add reset controller for hi6220 hikey-board.
Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
---
arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
index 82d2488..ad1f1eb 100644
--- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
+++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi
@@ -147,6 +147,7 @@
compatible = "hisilicon,hi6220-sysctrl", "syscon";
reg = <0x0 0xf7030000 0x0 0x2000>;
#clock-cells = <1>;
+ #reset-cells = <1>;
};
media_ctrl: media_ctrl@f4410000 {
--
1.9.1
^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH V7 2/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC
2015-11-20 2:10 ` [PATCH V7 2/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC Chen Feng
@ 2015-11-20 8:40 ` Philipp Zabel
0 siblings, 0 replies; 5+ messages in thread
From: Philipp Zabel @ 2015-11-20 8:40 UTC (permalink / raw)
To: Chen Feng
Cc: robh+dt, pawel.moll, mark.rutland, ijc+devicetree, galak,
devicetree, linux-kernel, xuwei5, puck.chen, w.f
Am Freitag, den 20.11.2015, 10:10 +0800 schrieb Chen Feng:
> Add reset driver for hi6220-hikey board,this driver supply deassert
> of IP on hi6220 SoC.
>
> Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
Applied all three, thank you.
regards
Philipp
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH V7 1/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings
2015-11-20 2:10 [PATCH V7 1/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings Chen Feng
2015-11-20 2:10 ` [PATCH V7 2/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC Chen Feng
2015-11-20 2:10 ` [PATCH V7 3/3] arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC Chen Feng
@ 2015-11-20 14:15 ` Rob Herring
2 siblings, 0 replies; 5+ messages in thread
From: Rob Herring @ 2015-11-20 14:15 UTC (permalink / raw)
To: Chen Feng
Cc: p.zabel, pawel.moll, mark.rutland, ijc+devicetree, galak,
devicetree, linux-kernel, xuwei5, puck.chen, w.f
On Fri, Nov 20, 2015 at 10:10:04AM +0800, Chen Feng wrote:
> Add DT bindings documentation for hi6220 SoC reset controller.
>
> Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
Acked-by: Rob Herring <robh@kernel.org>
> ---
> .../bindings/reset/hisilicon,hi6220-reset.txt | 34 +++++++++++
> include/dt-bindings/reset/hisi,hi6220-resets.h | 67 ++++++++++++++++++++++
> 2 files changed, 101 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
> create mode 100644 include/dt-bindings/reset/hisi,hi6220-resets.h
>
> diff --git a/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
> new file mode 100644
> index 0000000..e0b185a
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/reset/hisilicon,hi6220-reset.txt
> @@ -0,0 +1,34 @@
> +Hisilicon System Reset Controller
> +======================================
> +
> +Please also refer to reset.txt in this directory for common reset
> +controller binding usage.
> +
> +The reset controller registers are part of the system-ctl block on
> +hi6220 SoC.
> +
> +Required properties:
> +- compatible: may be "hisilicon,hi6220-sysctrl"
> +- reg: should be register base and length as documented in the
> + datasheet
> +- #reset-cells: 1, see below
> +
> +Example:
> +sys_ctrl: sys_ctrl@f7030000 {
> + compatible = "hisilicon,hi6220-sysctrl", "syscon";
> + reg = <0x0 0xf7030000 0x0 0x2000>;
> + #clock-cells = <1>;
> + #reset-cells = <1>;
> +};
> +
> +Specifying reset lines connected to IP modules
> +==============================================
> +example:
> +
> + uart1: serial@..... {
> + ...
> + resets = <&sys_ctrl PERIPH_RSTEN3_UART1>;
> + ...
> + };
> +
> +The index could be found in <dt-bindings/reset/hisi,hi6220-resets.h>.
> diff --git a/include/dt-bindings/reset/hisi,hi6220-resets.h b/include/dt-bindings/reset/hisi,hi6220-resets.h
> new file mode 100644
> index 0000000..ca08a7e
> --- /dev/null
> +++ b/include/dt-bindings/reset/hisi,hi6220-resets.h
> @@ -0,0 +1,67 @@
> +/**
> + * This header provides index for the reset controller
> + * based on hi6220 SoC.
> + */
> +#ifndef _DT_BINDINGS_RESET_CONTROLLER_HI6220
> +#define _DT_BINDINGS_RESET_CONTROLLER_HI6220
> +
> +#define PERIPH_RSTDIS0_MMC0 0x000
> +#define PERIPH_RSTDIS0_MMC1 0x001
> +#define PERIPH_RSTDIS0_MMC2 0x002
> +#define PERIPH_RSTDIS0_NANDC 0x003
> +#define PERIPH_RSTDIS0_USBOTG_BUS 0x004
> +#define PERIPH_RSTDIS0_POR_PICOPHY 0x005
> +#define PERIPH_RSTDIS0_USBOTG 0x006
> +#define PERIPH_RSTDIS0_USBOTG_32K 0x007
> +#define PERIPH_RSTDIS1_HIFI 0x100
> +#define PERIPH_RSTDIS1_DIGACODEC 0x105
> +#define PERIPH_RSTEN2_IPF 0x200
> +#define PERIPH_RSTEN2_SOCP 0x201
> +#define PERIPH_RSTEN2_DMAC 0x202
> +#define PERIPH_RSTEN2_SECENG 0x203
> +#define PERIPH_RSTEN2_ABB 0x204
> +#define PERIPH_RSTEN2_HPM0 0x205
> +#define PERIPH_RSTEN2_HPM1 0x206
> +#define PERIPH_RSTEN2_HPM2 0x207
> +#define PERIPH_RSTEN2_HPM3 0x208
> +#define PERIPH_RSTEN3_CSSYS 0x300
> +#define PERIPH_RSTEN3_I2C0 0x301
> +#define PERIPH_RSTEN3_I2C1 0x302
> +#define PERIPH_RSTEN3_I2C2 0x303
> +#define PERIPH_RSTEN3_I2C3 0x304
> +#define PERIPH_RSTEN3_UART1 0x305
> +#define PERIPH_RSTEN3_UART2 0x306
> +#define PERIPH_RSTEN3_UART3 0x307
> +#define PERIPH_RSTEN3_UART4 0x308
> +#define PERIPH_RSTEN3_SSP 0x309
> +#define PERIPH_RSTEN3_PWM 0x30a
> +#define PERIPH_RSTEN3_BLPWM 0x30b
> +#define PERIPH_RSTEN3_TSENSOR 0x30c
> +#define PERIPH_RSTEN3_DAPB 0x312
> +#define PERIPH_RSTEN3_HKADC 0x313
> +#define PERIPH_RSTEN3_CODEC_SSI 0x314
> +#define PERIPH_RSTEN3_PMUSSI1 0x316
> +#define PERIPH_RSTEN8_RS0 0x400
> +#define PERIPH_RSTEN8_RS2 0x401
> +#define PERIPH_RSTEN8_RS3 0x402
> +#define PERIPH_RSTEN8_MS0 0x403
> +#define PERIPH_RSTEN8_MS2 0x405
> +#define PERIPH_RSTEN8_XG2RAM0 0x406
> +#define PERIPH_RSTEN8_X2SRAM_TZMA 0x407
> +#define PERIPH_RSTEN8_SRAM 0x408
> +#define PERIPH_RSTEN8_HARQ 0x40a
> +#define PERIPH_RSTEN8_DDRC 0x40c
> +#define PERIPH_RSTEN8_DDRC_APB 0x40d
> +#define PERIPH_RSTEN8_DDRPACK_APB 0x40e
> +#define PERIPH_RSTEN8_DDRT 0x411
> +#define PERIPH_RSDIST9_CARM_DAP 0x500
> +#define PERIPH_RSDIST9_CARM_ATB 0x501
> +#define PERIPH_RSDIST9_CARM_LBUS 0x502
> +#define PERIPH_RSDIST9_CARM_POR 0x503
> +#define PERIPH_RSDIST9_CARM_CORE 0x504
> +#define PERIPH_RSDIST9_CARM_DBG 0x505
> +#define PERIPH_RSDIST9_CARM_L2 0x506
> +#define PERIPH_RSDIST9_CARM_SOCDBG 0x507
> +#define PERIPH_RSDIST9_CARM_ETM 0x508
> +
> +#endif /*_DT_BINDINGS_RESET_CONTROLLER_HI6220*/
> --
> 1.9.1
>
> --
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> More majordomo info at http://vger.kernel.org/majordomo-info.html
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2015-11-20 14:15 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2015-11-20 2:10 [PATCH V7 1/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings Chen Feng
2015-11-20 2:10 ` [PATCH V7 2/3] reset: hi6220: Reset driver for hisilicon hi6220 SoC Chen Feng
2015-11-20 8:40 ` Philipp Zabel
2015-11-20 2:10 ` [PATCH V7 3/3] arm64: dts: Add reset dts config for Hisilicon Hi6220 SoC Chen Feng
2015-11-20 14:15 ` [PATCH V7 1/3] reset: hisilicon: document hisi-hi6220 reset controllers bindings Rob Herring
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