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From: Rajendra Nayak <rnayak@codeaurora.org>
To: sboyd@codeaurora.org, mturquette@baylibre.com
Cc: linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org,
	linux-kernel@vger.kernel.org, tdas@codeaurora.org,
	Rajendra Nayak <rnayak@codeaurora.org>
Subject: [PATCH 4/7] clk: qcom: Add freq tables for a few rcgs
Date: Wed, 19 Oct 2016 16:58:40 +0530	[thread overview]
Message-ID: <1476876523-27378-5-git-send-email-rnayak@codeaurora.org> (raw)
In-Reply-To: <1476876523-27378-1-git-send-email-rnayak@codeaurora.org>

Add frequency tables for a few RCG clocks in msm8996

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
 drivers/clk/qcom/gcc-msm8996.c | 25 +++++++++++++++++++++++++
 1 file changed, 25 insertions(+)

diff --git a/drivers/clk/qcom/gcc-msm8996.c b/drivers/clk/qcom/gcc-msm8996.c
index 3c85e05..f6124cf 100644
--- a/drivers/clk/qcom/gcc-msm8996.c
+++ b/drivers/clk/qcom/gcc-msm8996.c
@@ -464,10 +464,18 @@ enum {
 	},
 };
 
+static struct freq_tbl ftbl_sdcc1_ice_core_clk_src[] = {
+	F(19200000, P_XO, 1, 0, 0),
+	F(150000000, P_GPLL0, 4, 0, 0),
+	F(300000000, P_GPLL0, 2, 0, 0),
+	{ }
+};
+
 static struct clk_rcg2 sdcc1_ice_core_clk_src = {
 	.cmd_rcgr = 0x13024,
 	.hid_width = 5,
 	.parent_map = gcc_xo_gpll0_gpll4_gpll0_early_div_map,
+	.freq_tbl = ftbl_sdcc1_ice_core_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "sdcc1_ice_core_clk_src",
 		.parent_names = gcc_xo_gpll0_gpll4_gpll0_early_div,
@@ -1230,10 +1238,18 @@ enum {
 	},
 };
 
+static const struct freq_tbl ftbl_ufs_ice_core_clk_src[] = {
+	F(19200000, P_XO, 1, 0, 0),
+	F(150000000, P_GPLL0, 4, 0, 0),
+	F(300000000, P_GPLL0, 2, 0, 0),
+	{ }
+};
+
 static struct clk_rcg2 ufs_ice_core_clk_src = {
 	.cmd_rcgr = 0x76014,
 	.hid_width = 5,
 	.parent_map = gcc_xo_gpll0_map,
+	.freq_tbl = ftbl_ufs_ice_core_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "ufs_ice_core_clk_src",
 		.parent_names = gcc_xo_gpll0,
@@ -1242,10 +1258,19 @@ enum {
 	},
 };
 
+static const struct freq_tbl ftbl_qspi_ser_clk_src[] = {
+	F(75000000, P_GPLL0, 8, 0, 0),
+	F(150000000, P_GPLL0, 4, 0, 0),
+	F(256000000, P_GPLL4, 1.5, 0, 0),
+	F(300000000, P_GPLL0, 2, 0, 0),
+	{ }
+};
+
 static struct clk_rcg2 qspi_ser_clk_src = {
 	.cmd_rcgr = 0x8b00c,
 	.hid_width = 5,
 	.parent_map = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div_map,
+	.freq_tbl = ftbl_qspi_ser_clk_src,
 	.clkr.hw.init = &(struct clk_init_data){
 		.name = "qspi_ser_clk_src",
 		.parent_names = gcc_xo_gpll0_gpll1_early_div_gpll1_gpll4_gpll0_early_div,
-- 
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation

  parent reply	other threads:[~2016-10-19 15:07 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-10-19 11:28 [PATCH 0/7] clk: qcom: Misc gcc/mmcc msm8996 fixes Rajendra Nayak
2016-10-19 11:28 ` [PATCH 1/7] clk: qcom: Mark a few branch clocks with BRANCH_HALT_DELAY Rajendra Nayak
2016-11-02 20:39   ` Stephen Boyd
2016-11-03  8:26     ` Rajendra Nayak
2016-10-19 11:28 ` [PATCH 2/7] clk: qcom: Add a custom udelay needed for some branch clocks Rajendra Nayak
2017-02-24 13:20   ` Bjorn Andersson
2016-10-19 11:28 ` [PATCH 3/7] clk: qcom: Add custom udelays for clks in msm8996 Rajendra Nayak
2016-10-19 11:28 ` Rajendra Nayak [this message]
2016-11-02 21:50   ` [PATCH 4/7] clk: qcom: Add freq tables for a few rcgs Stephen Boyd
2016-10-19 11:28 ` [PATCH 5/7] clk: qcom: Mark a few clocks as BRANCH_VOTED Rajendra Nayak
2016-10-19 11:28 ` [PATCH 6/7] clk: qcom: Add force enable/disable needed for gfx3d rcg on msm8996 Rajendra Nayak
2016-10-19 11:28 ` [PATCH 7/7] clk: qcom: Add some missing gcc clks for msm8996 Rajendra Nayak

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