From: Rajendra Nayak <rnayak@codeaurora.org>
To: sboyd@codeaurora.org, mturquette@baylibre.com
Cc: linux-clk@vger.kernel.org, linux-arm-msm@vger.kernel.org,
linux-kernel@vger.kernel.org, tdas@codeaurora.org,
Rajendra Nayak <rnayak@codeaurora.org>
Subject: [PATCH 6/7] clk: qcom: Add force enable/disable needed for gfx3d rcg on msm8996
Date: Wed, 19 Oct 2016 16:58:42 +0530 [thread overview]
Message-ID: <1476876523-27378-7-git-send-email-rnayak@codeaurora.org> (raw)
In-Reply-To: <1476876523-27378-1-git-send-email-rnayak@codeaurora.org>
The gfx3d RCG on msm8996 needs to be force enabled/disabled by
toggling the CMD_ROOT_EN bit. Add enable/disable ops to clk_gfx3d_ops
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
---
drivers/clk/qcom/clk-rcg2.c | 31 ++++++++++++++++++++++++++-----
1 file changed, 26 insertions(+), 5 deletions(-)
diff --git a/drivers/clk/qcom/clk-rcg2.c b/drivers/clk/qcom/clk-rcg2.c
index a071bba..6c79cca 100644
--- a/drivers/clk/qcom/clk-rcg2.c
+++ b/drivers/clk/qcom/clk-rcg2.c
@@ -300,7 +300,7 @@ static int clk_rcg2_set_rate_and_parent(struct clk_hw *hw,
};
EXPORT_SYMBOL_GPL(clk_rcg2_ops);
-static int clk_rcg2_shared_force_enable(struct clk_hw *hw, unsigned long rate)
+static int clk_rcg2_force_enable(struct clk_hw *hw)
{
struct clk_rcg2 *rcg = to_clk_rcg2(hw);
const char *name = clk_hw_get_name(hw);
@@ -316,20 +316,39 @@ static int clk_rcg2_shared_force_enable(struct clk_hw *hw, unsigned long rate)
for (count = 500; count > 0; count--) {
ret = clk_rcg2_is_enabled(hw);
if (ret)
- break;
+ return 0;
udelay(1);
}
if (!count)
pr_err("%s: RCG did not turn on\n", name);
+ return -ETIMEDOUT;
+}
+
+static void clk_rcg2_force_disable(struct clk_hw *hw)
+{
+ struct clk_rcg2 *rcg = to_clk_rcg2(hw);
+
+ /* clear force enable RCG */
+ regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
+ CMD_ROOT_EN, 0);
+}
+
+static int clk_rcg2_shared_force_enable(struct clk_hw *hw, unsigned long rate)
+{
+ int ret;
+
+ ret = clk_rcg2_force_enable(hw);
+ if (ret)
+ return ret;
+
/* set clock rate */
ret = __clk_rcg2_set_rate(hw, rate);
if (ret)
return ret;
- /* clear force enable RCG */
- return regmap_update_bits(rcg->clkr.regmap, rcg->cmd_rcgr + CMD_REG,
- CMD_ROOT_EN, 0);
+ clk_rcg2_force_disable(hw);
+ return 0;
}
static int clk_rcg2_shared_set_rate(struct clk_hw *hw, unsigned long rate,
@@ -801,6 +820,8 @@ static int clk_gfx3d_set_rate(struct clk_hw *hw, unsigned long rate,
}
const struct clk_ops clk_gfx3d_ops = {
+ .enable = clk_rcg2_force_enable,
+ .disable = clk_rcg2_force_disable,
.is_enabled = clk_rcg2_is_enabled,
.get_parent = clk_rcg2_get_parent,
.set_parent = clk_rcg2_set_parent,
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
next prev parent reply other threads:[~2016-10-19 15:09 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-10-19 11:28 [PATCH 0/7] clk: qcom: Misc gcc/mmcc msm8996 fixes Rajendra Nayak
2016-10-19 11:28 ` [PATCH 1/7] clk: qcom: Mark a few branch clocks with BRANCH_HALT_DELAY Rajendra Nayak
2016-11-02 20:39 ` Stephen Boyd
2016-11-03 8:26 ` Rajendra Nayak
2016-10-19 11:28 ` [PATCH 2/7] clk: qcom: Add a custom udelay needed for some branch clocks Rajendra Nayak
2017-02-24 13:20 ` Bjorn Andersson
2016-10-19 11:28 ` [PATCH 3/7] clk: qcom: Add custom udelays for clks in msm8996 Rajendra Nayak
2016-10-19 11:28 ` [PATCH 4/7] clk: qcom: Add freq tables for a few rcgs Rajendra Nayak
2016-11-02 21:50 ` Stephen Boyd
2016-10-19 11:28 ` [PATCH 5/7] clk: qcom: Mark a few clocks as BRANCH_VOTED Rajendra Nayak
2016-10-19 11:28 ` Rajendra Nayak [this message]
2016-10-19 11:28 ` [PATCH 7/7] clk: qcom: Add some missing gcc clks for msm8996 Rajendra Nayak
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