[PATCH v8: 4/4] x86/cpufeatures: Handle RING3MWAIT on Xeon Phi models

[Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>]

Unfortunately presence of this feature cannot be detected
automatically (by reading some other MSR) therefore it is required
to do explicit check for the family and model of the cpu.

If processor is Intel Xeon Phi x200 RING3MWAIT feature is enabled
by setting cpu cap X86_FEATURE_PHIR3MWAIT and elf HWCAP2_RING3MWAIT.

Signed-off-by: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
---
 Documentation/kernel-parameters.txt       |  5 ++++
 Documentation/x86/x86_64/boot-options.txt |  5 ++++
 arch/x86/kernel/cpu/intel.c               | 39 +++++++++++++++++++++++++++++++
 3 files changed, 49 insertions(+)

diff --git a/Documentation/kernel-parameters.txt b/Documentation/kernel-parameters.txt
index a4f4d69..7754310 100644
--- a/Documentation/kernel-parameters.txt
+++ b/Documentation/kernel-parameters.txt
@@ -3120,6 +3120,11 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
 	pg.		[PARIDE]
 			See Documentation/blockdev/paride.txt.
 
+	phir3mwait=	[X86-64] Do not enable Intel Xeon Phi x200 ring 3 MONITOR/MWAIT
+			feature for all cpus.
+			Format: { disable }
+			See Documentation/x86/x86_64/boot-options.txt
+
 	pirq=		[SMP,APIC] Manual mp-table setup
 			See Documentation/x86/i386/IO-APIC.txt.
 
diff --git a/Documentation/x86/x86_64/boot-options.txt b/Documentation/x86/x86_64/boot-options.txt
index 0965a71..1a515e8 100644
--- a/Documentation/x86/x86_64/boot-options.txt
+++ b/Documentation/x86/x86_64/boot-options.txt
@@ -281,6 +281,11 @@ Debugging
 
   kstack=N	Print N words from the kernel stack in oops dumps.
 
+  phir3mwait=disable
+  Disables unconditional setting bit 1 of the MSR_MISC_FEATURE_ENABLES
+  for Intel Xeon Phi, this way administrator can switch off ring 3 mwait
+  feature.
+
 Miscellaneous
 
 	nogbpages
diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index fcd484d..670dd98 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -14,6 +14,8 @@
 #include <asm/bugs.h>
 #include <asm/cpu.h>
 #include <asm/intel-family.h>
+#include <asm/hwcap2.h>
+#include <asm/elf.h>
 
 #ifdef CONFIG_X86_64
 #include <linux/topology.h>
@@ -61,6 +63,41 @@ void check_mpx_erratum(struct cpuinfo_x86 *c)
 	}
 }
 
+#ifdef CONFIG_X86_64
+static int phi_r3mwait_disabled __read_mostly;
+
+static int __init phir3mwait_disable(char *__unused)
+{
+	phi_r3mwait_disabled = 1;
+	return 1;
+}
+__setup("phir3mwait=disable", phir3mwait_disable);
+
+static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *c)
+{
+	/*
+	 * Rign 3 MWAIT feature cannot be detected without
+	 * ugly model and family comparison.
+	 */
+	if (c->x86 != 6 || c->x86_model != INTEL_FAM6_XEON_PHI_KNL)
+		return;
+
+	if (phi_r3mwait_disabled) {
+		msr_clear_bit(MSR_MISC_FEATURE_ENABLES,
+			      MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT);
+		return;
+	}
+
+	msr_set_bit(MSR_MISC_FEATURE_ENABLES,
+		    MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT);
+	set_cpu_cap(c, X86_FEATURE_PHIR3MWAIT);
+	ELF_HWCAP2 |= HWCAP2_RING3MWAIT;
+}
+
+#else
+static void probe_xeon_phi_r3mwait(struct cpuinfo_x86 *__unused) {}
+#endif
+
 static void early_init_intel(struct cpuinfo_x86 *c)
 {
 	u64 misc_enable;
@@ -565,6 +602,8 @@ static void init_intel(struct cpuinfo_x86 *c)
 		detect_vmx_virtcap(c);
 
 	init_intel_energy_perf(c);
+
+	probe_xeon_phi_r3mwait(c);
 }
 
 #ifdef CONFIG_X86_32
-- 
2.5.1