From: Thomas Gleixner <tglx@linutronix.de>
To: Grzegorz Andrejczuk <grzegorz.andrejczuk@intel.com>
Cc: mingo@redhat.com, hpa@zytor.com, x86@kernel.org, bp@suse.de,
dave.hansen@linux.intel.com, lukasz.daniluk@intel.com,
james.h.cownie@intel.com, jacob.jun.pan@intel.com,
Piotr.Luc@intel.com, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit
Date: Thu, 3 Nov 2016 11:00:30 -0600 (MDT) [thread overview]
Message-ID: <alpine.DEB.2.20.1611031052190.5885@nanos> (raw)
In-Reply-To: <1477995290-25079-2-git-send-email-grzegorz.andrejczuk@intel.com>
On Tue, 1 Nov 2016, Grzegorz Andrejczuk wrote:
>
> +/* Intel Xeon Phi x200 ring 3 MONITOR/MWAIT */
Oh well. I asked you to make that whole PHI thing go away.
This is a feature which has nothing to do with PHI. It just happens to be
implemented on PHI. The FEATURES_ENABLES MSR is not at all PHI specific.
It's all about a feature which enables ring 3 mwait/monitor.
> +#define MSR_MISC_FEATURE_ENABLES 0x00000140
> +#define MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT 1
> +#define MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT (1ULL << MSR_MISC_FEATURE_ENABLES_PHIR3MWAIT_BIT)
> +
You really try hard to get your crap behind me. Stop sending out half baken
shit every other day without addressing my review comments.
Your trust level approaches negative space.
Thanks,
tglx
next prev parent reply other threads:[~2016-11-03 17:03 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-01 10:14 [PATCH v8: 0/4] Enabling Ring 3 MONITOR/MWAIT feature for Knights Landing Grzegorz Andrejczuk
2016-11-01 10:14 ` [PATCH v8: 1/4] x86/msr: Add MSR_MISC_FEATURE_ENABLES and PHIR3MWAIT bit Grzegorz Andrejczuk
2016-11-03 14:54 ` Borislav Petkov
2016-11-03 17:00 ` Thomas Gleixner [this message]
2016-11-04 6:47 ` Andrejczuk, Grzegorz
2016-11-07 20:48 ` Thomas Gleixner
2016-11-01 10:14 ` [PATCH v8: 2/4] x86/elf: Use HWCAP2 to expose ring 3 MWAIT Grzegorz Andrejczuk
2016-11-01 10:14 ` [PATCH v8: 3/4] x86/cpufeature: Add PHIR3MWAIT to CPU features Grzegorz Andrejczuk
2016-11-03 14:56 ` Borislav Petkov
2016-11-03 16:01 ` [PATCH v8 " Grzegorz Andrejczuk
2016-11-01 10:14 ` [PATCH v8: 4/4] x86/cpufeatures: Handle RING3MWAIT on Xeon Phi models Grzegorz Andrejczuk
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=alpine.DEB.2.20.1611031052190.5885@nanos \
--to=tglx@linutronix.de \
--cc=Piotr.Luc@intel.com \
--cc=bp@suse.de \
--cc=dave.hansen@linux.intel.com \
--cc=grzegorz.andrejczuk@intel.com \
--cc=hpa@zytor.com \
--cc=jacob.jun.pan@intel.com \
--cc=james.h.cownie@intel.com \
--cc=linux-kernel@vger.kernel.org \
--cc=lukasz.daniluk@intel.com \
--cc=mingo@redhat.com \
--cc=x86@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).