From: <yongqiang.niu@mediatek.com>
To: CK Hu <ck.hu@mediatek.com>,
Philipp Zabel <p.zabel@pengutronix.de>,
Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>
Cc: David Airlie <airlied@linux.ie>, Daniel Vetter <daniel@ffwll.ch>,
Mark Rutland <mark.rutland@arm.com>,
<dri-devel@lists.freedesktop.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
Yongqiang Niu <yongqiang.niu@mediatek.com>
Subject: [PATCH v5, 13/32] drm/mediatek: move rdma sout from mtk_ddp_mout_en into mtk_ddp_sout_sel
Date: Thu, 29 Aug 2019 22:50:35 +0800 [thread overview]
Message-ID: <1567090254-15566-14-git-send-email-yongqiang.niu@mediatek.com> (raw)
In-Reply-To: <1567090254-15566-1-git-send-email-yongqiang.niu@mediatek.com>
From: Yongqiang Niu <yongqiang.niu@mediatek.com>
This patch move rdma sout from mtk_ddp_mout_en into mtk_ddp_sout_sel
rdma only has single output, but no multi output,
all these rdma->dsi/dpi usecase should move to mtk_ddp_sout_sel
Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com>
---
drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 90 +++++++++++++++++-----------------
1 file changed, 45 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
index 338cc2f..a5a6689 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c
@@ -299,51 +299,6 @@ static unsigned int mtk_ddp_mout_en(const struct mtk_mmsys_reg_data *data,
} else if (cur == DDP_COMPONENT_OD1 && next == DDP_COMPONENT_RDMA1) {
*addr = DISP_REG_CONFIG_DISP_OD_MOUT_EN;
value = OD1_MOUT_EN_RDMA1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DPI0;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
- value = RDMA0_SOUT_DSI3;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DSI3;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
- *addr = data->rdma1_sout_sel_in;
- value = data->rdma1_sout_dpi0;
- } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
- value = RDMA1_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DPI0;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DPI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI1;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI2;
- } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
- *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
- value = RDMA2_SOUT_DSI3;
} else {
value = 0;
}
@@ -423,6 +378,51 @@ static unsigned int mtk_ddp_sout_sel(const struct mtk_mmsys_reg_data *data,
} else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) {
*addr = DISP_REG_CONFIG_OUT_SEL;
value = BLS_TO_DPI_RDMA1_TO_DSI;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI0) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DPI0;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DPI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI2) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI2;
+ } else if (cur == DDP_COMPONENT_RDMA0 && next == DDP_COMPONENT_DSI3) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA0_SOUT_EN;
+ value = RDMA0_SOUT_DSI3;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI2) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DSI2;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI3) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DSI3;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI0) {
+ *addr = data->rdma1_sout_sel_in;
+ value = data->rdma1_sout_dpi0;
+ } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DPI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA1_SOUT_EN;
+ value = RDMA1_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI0) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DPI0;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DPI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DPI1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI1) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DSI1;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI2) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DSI2;
+ } else if (cur == DDP_COMPONENT_RDMA2 && next == DDP_COMPONENT_DSI3) {
+ *addr = DISP_REG_CONFIG_DISP_RDMA2_SOUT;
+ value = RDMA2_SOUT_DSI3;
} else {
value = 0;
}
--
1.8.1.1.dirty
next prev parent reply other threads:[~2019-08-29 14:52 UTC|newest]
Thread overview: 72+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-29 14:50 [PATCH v5, 00/32] add drm support for MT8183 yongqiang.niu
2019-08-29 14:50 ` [PATCH v5, 01/32] dt-bindings: mediatek: add binding for mt8183 display yongqiang.niu
2019-08-30 5:15 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 02/32] dt-bindings: mediatek: add ovl_2l description " yongqiang.niu
2019-09-04 1:44 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 03/32] dt-bindings: mediatek: add ccorr " yongqiang.niu
2019-09-04 1:44 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 04/32] dt-bindings: mediatek: add dither " yongqiang.niu
2019-09-04 1:45 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 05/32] dt-bindings: mediatek: add mutex " yongqiang.niu
2019-09-02 13:38 ` Rob Herring
2019-09-04 1:45 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 06/32] arm64: dts: add display nodes for mt8183 yongqiang.niu
2019-08-29 14:50 ` [PATCH v5, 07/32] drm/mediatek: add mutex mod into ddp private data yongqiang.niu
2019-10-09 9:31 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 08/32] drm/mediatek: add mutex mod register offset " yongqiang.niu
2019-10-09 9:32 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 09/32] drm/mediatek: add mutex sof " yongqiang.niu
2019-10-09 9:33 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 10/32] drm/mediatek: add mutex sof register offset " yongqiang.niu
2019-10-09 9:33 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 11/32] drm/mediatek: split DISP_REG_CONFIG_DSI_SEL setting into another use case yongqiang.niu
2019-08-30 5:21 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 12/32] drm/mediatek: add mmsys private data for ddp path config yongqiang.niu
2019-08-30 5:27 ` CK Hu
2019-08-30 5:40 ` CK Hu
2019-08-29 14:50 ` yongqiang.niu [this message]
2019-08-30 5:41 ` [PATCH v5, 13/32] drm/mediatek: move rdma sout from mtk_ddp_mout_en into mtk_ddp_sout_sel CK Hu
2019-08-29 14:50 ` [PATCH v5, 14/32] drm/mediatek: add ddp component CCORR yongqiang.niu
2019-10-09 9:10 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 15/32] drm/mediatek: add commponent OVL_2L0 yongqiang.niu
2019-10-09 9:17 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 16/32] drm/mediatek: add component OVL_2L1 yongqiang.niu
2019-10-09 9:18 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 17/32] drm/mediatek: add component DITHER yongqiang.niu
2019-10-09 9:11 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 18/32] drm/mediatek: add gmc_bits for ovl private data yongqiang.niu
2019-10-09 9:19 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 19/32] drm/medaitek: add layer_nr " yongqiang.niu
2019-10-09 9:20 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 20/32] drm/mediatek: add function to background color input select for ovl/ovl_2l direct link yongqiang.niu
2019-10-09 9:24 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 21/32] drm/mediatek: add background color input select function for ovl/ovl_2l yongqiang.niu
2019-10-09 9:24 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 22/32] drm/mediatek: add ovl0/ovl_2l0 usecase yongqiang.niu
2019-08-30 5:58 ` CK Hu
2019-09-02 8:11 ` CK Hu
2019-10-09 9:29 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 23/32] drm/mediatek: distinguish ovl and ovl_2l by layer_nr yongqiang.niu
2019-10-09 9:28 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 24/32] drm/mediatek: add clock property check before get it yongqiang.niu
2019-08-30 6:11 ` CK Hu
2019-10-09 9:36 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 25/32] drm/mediatek: add connection from OVL0 to OVL_2L0 yongqiang.niu
2019-08-30 6:20 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 26/32] drm/mediatek: add connection from RDMA0 to COLOR0 yongqiang.niu
2019-08-30 6:23 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 27/32] drm/mediatek: add connection from RDMA1 to DSI0 yongqiang.niu
2019-08-30 6:25 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 28/32] drm/mediatek: add connection from OVL_2L0 to RDMA0 yongqiang.niu
2019-08-30 6:30 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 29/32] drm/mediatek: add connection from OVL_2L1 to RDMA1 yongqiang.niu
2019-08-30 6:33 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 30/32] drm/mediatek: add connection from DITHER0 to DSI0 yongqiang.niu
2019-08-30 6:34 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 31/32] drm/mediatek: add connection from RDMA0 " yongqiang.niu
2019-08-30 6:36 ` CK Hu
2019-08-29 14:50 ` [PATCH v5, 32/32] drm/mediatek: add support for mediatek SOC MT8183 yongqiang.niu
2019-08-30 6:38 ` CK Hu
2019-09-05 7:17 ` CK Hu
2020-05-21 10:52 ` Matthias Brugger
2019-10-09 9:47 ` [PATCH v5, 00/32] add drm support for MT8183 CK Hu
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