From: Manish Narani <manish.narani@xilinx.com>
To: ulf.hansson@linaro.org, robh+dt@kernel.org, mark.rutland@arm.com,
adrian.hunter@intel.com, michal.simek@xilinx.com,
jolly.shah@xilinx.com, nava.manne@xilinx.com,
rajan.vaja@xilinx.com, manish.narani@xilinx.com
Cc: linux-mmc@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, git@xilinx.com
Subject: [PATCH v4 4/8] dt-bindings: mmc: arasan: Add optional properties for Arasan SDHCI
Date: Tue, 29 Oct 2019 16:00:38 +0530 [thread overview]
Message-ID: <1572345042-101207-4-git-send-email-manish.narani@xilinx.com> (raw)
In-Reply-To: <1572345042-101207-1-git-send-email-manish.narani@xilinx.com>
Add optional properties for Arasan SDHCI which are used to set clk delays
for different speed modes in the controller.
Signed-off-by: Manish Narani <manish.narani@xilinx.com>
---
.../devicetree/bindings/mmc/arasan,sdhci.txt | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
index b51e40b2e0c5..c0f505b6cab5 100644
--- a/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
+++ b/Documentation/devicetree/bindings/mmc/arasan,sdhci.txt
@@ -46,6 +46,22 @@ Optional Properties:
properly. Test mode can be used to force the controller to function.
- xlnx,int-clock-stable-broken: when present, the controller always reports
that the internal clock is stable even when it is not.
+ - arasan-clk-phase-legacy: Input/Output Clock Delay pair in degrees for Legacy Mode.
+ - arasan-clk-phase-mmc-hs: Input/Output Clock Delay pair degrees for MMC HS.
+ - arasan-clk-phase-sd-hs: Input/Output Clock Delay pair in degrees for SD HS.
+ - arasan-clk-phase-uhs-sdr12: Input/Output Clock Delay pair in degrees for SDR12.
+ - arasan-clk-phase-uhs-sdr25: Input/Output Clock Delay pair in degrees for SDR25.
+ - arasan-clk-phase-uhs-sdr50: Input/Output Clock Delay pair in degrees for SDR50.
+ - arasan-clk-phase-uhs-sdr104: Input/Output Clock Delay pair in degrees for SDR104.
+ - arasan-clk-phase-uhs-ddr50: Input/Output Clock Delay pair in degrees for SD DDR50.
+ - arasan-clk-phase-mmc-ddr52: Input/Output Clock Delay pair in degrees for MMC DDR52.
+ - arasan-clk-phase-mmc-hs200: Input/Output Clock Delay pair in degrees for MMC HS200.
+ - arasan-clk-phase-mmc-hs400: Input/Output Clock Delay pair in degrees for MMC HS400.
+
+ Above mentioned are the clock (phase) delays which are to be configured in the
+ controller while switching to particular speed mode. The range of values are
+ 0 to 359 degrees. If not specified, driver will configure the default value
+ defined for particular mode in it.
Example:
sdhci@e0100000 {
--
2.17.1
next prev parent reply other threads:[~2019-10-29 10:31 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-29 10:30 [PATCH v4 1/8] mmc: sdhci-of-arasan: Separate out clk related data to another structure Manish Narani
2019-10-29 10:30 ` [PATCH v4 2/8] dt-bindings: mmc: arasan: Update Documentation for the input clock Manish Narani
2019-10-29 18:40 ` Rob Herring
2019-10-31 8:52 ` Manish Narani
2019-10-29 10:30 ` [PATCH v4 3/8] mmc: sdhci-of-arasan: Add sampling clock for a phy to use Manish Narani
2019-10-29 10:30 ` Manish Narani [this message]
2019-10-30 14:57 ` [PATCH v4 4/8] dt-bindings: mmc: arasan: Add optional properties for Arasan SDHCI Ulf Hansson
2019-10-31 8:54 ` Manish Narani
2019-10-29 10:30 ` [PATCH v4 5/8] mmc: sdhci-of-arasan: Add support to set clock phase delays for SD Manish Narani
2019-10-29 10:30 ` [PATCH v4 6/8] firmware: xilinx: Add SDIO Tap Delay nodes Manish Narani
2019-10-29 10:30 ` [PATCH v4 7/8] dt-bindings: mmc: arasan: Document 'xlnx,zynqmp-8.9a' controller Manish Narani
2019-10-29 10:30 ` [PATCH v4 8/8] mmc: sdhci-of-arasan: Add support for ZynqMP Platform Tap Delays Setup Manish Narani
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