* [PATCH v7 0/4] Add QMP V3 USB3 PHY support for SC7180
@ 2020-05-15 2:39 Sandeep Maheswaram
2020-05-15 2:39 ` [PATCH v7 1/4] dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml Sandeep Maheswaram
` (4 more replies)
0 siblings, 5 replies; 10+ messages in thread
From: Sandeep Maheswaram @ 2020-05-15 2:39 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring,
Mark Rutland, Stephen Boyd, Doug Anderson, Matthias Kaehlcke
Cc: linux-arm-msm, linux-kernel, devicetree, Manu Gautam, Sandeep Maheswaram
Add QMP V3 USB3 PHY entries for SC7180 in phy driver and
device tree bindings.
changes in v7:
*As per Matthias comments conversion to yaml and splitting out DP PHY bindings
patches are separated.
*PATCH v7 1/4 is for coversion to yaml.
*PATCH v7 2/4 has splitting out DP PHY bindings and adding as separate yaml
for DP PHY bindings.
*No changes in PATCH v7 3/4 and 4/4.
changes in v6:
*Added separate yaml file for USB3 DP PHY bindings.
changes in v5:
*Addressed comments from Matthias in yaml file.
*Dropped PATCH 4/4 as it is landed in linux-next.
changes in v4:
*Addressed comments from Matthias and Rob in yaml file.
changes in v3:
*Addressed Rob's comments in yaml file.
*Sepearated the SC7180 support in yaml patch.
*corrected the phy reset entries in device tree.
changes in v2:
*Remove global phy reset in QMP PHY.
*Convert QMP PHY bindings to yaml.
Sandeep Maheswaram (4):
dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml
dt-bindings: phy: qcom,qmp-usb3-dp: Add dt bindings for USB3 DP PHY
dt-bindings: phy: qcom,qmp-usb3-dp: Add support for SC7180
phy: qcom-qmp: Add QMP V3 USB3 PHY support for SC7180
.../devicetree/bindings/phy/qcom,qmp-phy.yaml | 313 +++++++++++++++++++++
.../bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 136 +++++++++
.../devicetree/bindings/phy/qcom-qmp-phy.txt | 247 ----------------
drivers/phy/qualcomm/phy-qcom-qmp.c | 38 +++
4 files changed, 487 insertions(+), 247 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v7 1/4] dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml
2020-05-15 2:39 [PATCH v7 0/4] Add QMP V3 USB3 PHY support for SC7180 Sandeep Maheswaram
@ 2020-05-15 2:39 ` Sandeep Maheswaram
2020-05-15 18:18 ` Matthias Kaehlcke
2020-05-15 2:39 ` [PATCH v7 2/4] dt-bindings: phy: qcom,qmp-usb3-dp: Add dt bindings for USB3 DP PHY Sandeep Maheswaram
` (3 subsequent siblings)
4 siblings, 1 reply; 10+ messages in thread
From: Sandeep Maheswaram @ 2020-05-15 2:39 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring,
Mark Rutland, Stephen Boyd, Doug Anderson, Matthias Kaehlcke
Cc: linux-arm-msm, linux-kernel, devicetree, Manu Gautam, Sandeep Maheswaram
Convert QMP PHY bindings to DT schema format using json-schema.
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
---
.../devicetree/bindings/phy/qcom,qmp-phy.yaml | 334 +++++++++++++++++++++
.../devicetree/bindings/phy/qcom-qmp-phy.txt | 247 ---------------
2 files changed, 334 insertions(+), 247 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
delete mode 100644 Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
new file mode 100644
index 0000000..dcdb014
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
@@ -0,0 +1,334 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/qcom,qmp-phy.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm QMP PHY controller
+
+maintainers:
+ - Manu Gautam <mgautam@codeaurora.org>
+
+description:
+ QMP phy controller supports physical layer functionality for a number of
+ controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
+
+properties:
+ compatible:
+ enum:
+ - qcom,ipq8074-qmp-pcie-phy
+ - qcom,msm8996-qmp-pcie-phy
+ - qcom,msm8996-qmp-ufs-phy
+ - qcom,msm8996-qmp-usb3-phy
+ - qcom,msm8998-qmp-pcie-phy
+ - qcom,msm8998-qmp-ufs-phy
+ - qcom,msm8998-qmp-usb3-phy
+ - qcom,sdm845-qhp-pcie-phy
+ - qcom,sdm845-qmp-pcie-phy
+ - qcom,sdm845-qmp-ufs-phy
+ - qcom,sdm845-qmp-usb3-phy
+ - qcom,sdm845-qmp-usb3-uni-phy
+ - qcom,sm8150-qmp-ufs-phy
+ - qcom,sm8250-qmp-ufs-phy
+
+ reg:
+ minItems: 1
+ items:
+ - description: Address and length of PHY's common serdes block.
+ - description: Address and length of the DP_COM control block.
+
+ reg-names:
+ items:
+ - const: reg-base
+ - const: dp_com
+
+ "#clock-cells":
+ enum: [ 1, 2 ]
+
+ "#address-cells":
+ enum: [ 1, 2 ]
+
+ "#size-cells":
+ enum: [ 1, 2 ]
+
+ clocks:
+ minItems: 1
+ maxItems: 4
+
+ clock-names:
+ minItems: 1
+ maxItems: 4
+
+ resets:
+ minItems: 1
+ maxItems: 3
+
+ reset-names:
+ minItems: 1
+ maxItems: 3
+
+ vdda-phy-supply:
+ description:
+ Phandle to a regulator supply to PHY core block.
+
+ vdda-pll-supply:
+ description:
+ Phandle to 1.8V regulator supply to PHY refclk pll block.
+
+ vddp-ref-clk-supply:
+ description:
+ Phandle to a regulator supply to any specific refclk
+ pll block.
+
+#Required nodes:
+patternProperties:
+ "^phy@[0-9a-f]+$":
+ type: object
+ description:
+ Each device node of QMP phy is required to have as many child nodes as
+ the number of lanes the PHY has.
+
+required:
+ - compatible
+ - reg
+ - "#clock-cells"
+ - "#address-cells"
+ - "#size-cells"
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - vdda-phy-supply
+ - vdda-pll-supply
+
+additionalProperties: false
+
+allOf:
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sdm845-qmp-usb3-phy
+ - qcom,sdm845-qmp-usb3-uni-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Phy aux clock.
+ - description: Phy config clock.
+ - description: 19.2 MHz ref clk.
+ - description: Phy common block aux clock.
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ - const: com_aux
+ resets:
+ items:
+ - description: reset of phy block.
+ - description: phy common block reset.
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8996-qmp-pcie-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Phy aux clock.
+ - description: Phy config clock.
+ - description: 19.2 MHz ref clk.
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ resets:
+ items:
+ - description: reset of phy block.
+ - description: phy common block reset.
+ - description: phy's ahb cfg block reset.
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+ - const: cfg
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8996-qmp-usb3-phy
+ - qcom,msm8998-qmp-pcie-phy
+ - qcom,msm8998-qmp-usb3-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Phy aux clock.
+ - description: Phy config clock.
+ - description: 19.2 MHz ref clk.
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ resets:
+ items:
+ - description: reset of phy block.
+ - description: phy common block reset.
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8996-qmp-ufs-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: 19.2 MHz ref clk.
+ clock-names:
+ items:
+ - const: ref
+ resets:
+ items:
+ - description: PHY reset in the UFS controller.
+ reset-names:
+ items:
+ - const: ufsphy
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,msm8998-qmp-ufs-phy
+ - qcom,sdm845-qmp-ufs-phy
+ - qcom,sm8150-qmp-ufs-phy
+ - qcom,sm8250-qmp-ufs-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: 19.2 MHz ref clk.
+ - description: Phy reference aux clock.
+ clock-names:
+ items:
+ - const: ref
+ - const: ref_aux
+ resets:
+ items:
+ - description: PHY reset in the UFS controller.
+ reset-names:
+ items:
+ - const: ufsphy
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,ipq8074-qmp-pcie-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: pipe clk.
+ clock-names:
+ items:
+ - const: pipe_clk
+ resets:
+ items:
+ - description: reset of phy block.
+ - description: phy common block reset.
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+ - if:
+ properties:
+ compatible:
+ contains:
+ enum:
+ - qcom,sdm845-qhp-pcie-phy
+ - qcom,sdm845-qmp-pcie-phy
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Phy aux clock.
+ - description: Phy config clock.
+ - description: 19.2 MHz ref clk.
+ - description: Phy refgen clk.
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ - const: refgen
+ resets:
+ items:
+ - description: reset of phy block.
+ reset-names:
+ items:
+ - const: phy
+ - if:
+ properties:
+ compatible:
+ contains:
+ const: qcom,sdm845-qmp-usb3-phy
+ then:
+ required:
+ - reg-names
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+ usb_1_qmpphy: phy-wrapper@88e9000 {
+ compatible = "qcom,sdm845-qmp-usb3-phy";
+ reg = <0 0x088e9000 0 0x18c>,
+ <0 0x088e8000 0 0x10>;
+ reg-names = "reg-base", "dp_com";
+ #clock-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref", "com_aux";
+
+ resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+ <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
+ reset-names = "phy", "common";
+
+ vdda-phy-supply = <&vdda_usb2_ss_1p2>;
+ vdda-pll-supply = <&vdda_usb2_ss_core>;
+
+ usb_1_ssphy: phy@88e9200 {
+ reg = <0 0x088e9200 0 0x128>,
+ <0 0x088e9400 0 0x200>,
+ <0 0x088e9c00 0 0x218>,
+ <0 0x088e9600 0 0x128>,
+ <0 0x088e9800 0 0x200>,
+ <0 0x088e9a00 0 0x100>;
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "usb3_phy_pipe_clk_src";
+ };
+ };
diff --git a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt b/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
deleted file mode 100644
index 5ff9e7a..0000000
--- a/Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt
+++ /dev/null
@@ -1,247 +0,0 @@
-Qualcomm QMP PHY controller
-===========================
-
-QMP phy controller supports physical layer functionality for a number of
-controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
-
-Required properties:
- - compatible: compatible list, contains:
- "qcom,ipq8074-qmp-pcie-phy" for PCIe phy on IPQ8074
- "qcom,msm8996-qmp-pcie-phy" for 14nm PCIe phy on msm8996,
- "qcom,msm8996-qmp-ufs-phy" for 14nm UFS phy on msm8996,
- "qcom,msm8996-qmp-usb3-phy" for 14nm USB3 phy on msm8996,
- "qcom,msm8998-qmp-usb3-phy" for USB3 QMP V3 phy on msm8998,
- "qcom,msm8998-qmp-ufs-phy" for UFS QMP phy on msm8998,
- "qcom,msm8998-qmp-pcie-phy" for PCIe QMP phy on msm8998,
- "qcom,sdm845-qhp-pcie-phy" for QHP PCIe phy on sdm845,
- "qcom,sdm845-qmp-pcie-phy" for QMP PCIe phy on sdm845,
- "qcom,sdm845-qmp-usb3-phy" for USB3 QMP V3 phy on sdm845,
- "qcom,sdm845-qmp-usb3-uni-phy" for USB3 QMP V3 UNI phy on sdm845,
- "qcom,sdm845-qmp-ufs-phy" for UFS QMP phy on sdm845,
- "qcom,sm8150-qmp-ufs-phy" for UFS QMP phy on sm8150.
- "qcom,sm8250-qmp-ufs-phy" for UFS QMP phy on sm8250.
-
-- reg:
- - index 0: address and length of register set for PHY's common
- serdes block.
- - index 1: address and length of the DP_COM control block (for
- "qcom,sdm845-qmp-usb3-phy" only).
-
-- reg-names:
- - For "qcom,sdm845-qmp-usb3-phy":
- - Should be: "reg-base", "dp_com"
- - For all others:
- - The reg-names property shouldn't be defined.
-
- - #address-cells: must be 1
- - #size-cells: must be 1
- - ranges: must be present
-
- - clocks: a list of phandles and clock-specifier pairs,
- one for each entry in clock-names.
- - clock-names: "cfg_ahb" for phy config clock,
- "aux" for phy aux clock,
- "ref" for 19.2 MHz ref clk,
- "com_aux" for phy common block aux clock,
- "ref_aux" for phy reference aux clock,
-
- For "qcom,ipq8074-qmp-pcie-phy": no clocks are listed.
- For "qcom,msm8996-qmp-pcie-phy" must contain:
- "aux", "cfg_ahb", "ref".
- For "qcom,msm8996-qmp-ufs-phy" must contain:
- "ref".
- For "qcom,msm8996-qmp-usb3-phy" must contain:
- "aux", "cfg_ahb", "ref".
- For "qcom,msm8998-qmp-usb3-phy" must contain:
- "aux", "cfg_ahb", "ref".
- For "qcom,msm8998-qmp-ufs-phy" must contain:
- "ref", "ref_aux".
- For "qcom,msm8998-qmp-pcie-phy" must contain:
- "aux", "cfg_ahb", "ref".
- For "qcom,sdm845-qhp-pcie-phy" must contain:
- "aux", "cfg_ahb", "ref", "refgen".
- For "qcom,sdm845-qmp-pcie-phy" must contain:
- "aux", "cfg_ahb", "ref", "refgen".
- For "qcom,sdm845-qmp-usb3-phy" must contain:
- "aux", "cfg_ahb", "ref", "com_aux".
- For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
- "aux", "cfg_ahb", "ref", "com_aux".
- For "qcom,sdm845-qmp-ufs-phy" must contain:
- "ref", "ref_aux".
- For "qcom,sm8150-qmp-ufs-phy" must contain:
- "ref", "ref_aux".
- For "qcom,sm8250-qmp-ufs-phy" must contain:
- "ref", "ref_aux".
-
- - resets: a list of phandles and reset controller specifier pairs,
- one for each entry in reset-names.
- - reset-names: "phy" for reset of phy block,
- "common" for phy common block reset,
- "cfg" for phy's ahb cfg block reset,
- "ufsphy" for the PHY reset in the UFS controller.
-
- For "qcom,ipq8074-qmp-pcie-phy" must contain:
- "phy", "common".
- For "qcom,msm8996-qmp-pcie-phy" must contain:
- "phy", "common", "cfg".
- For "qcom,msm8996-qmp-ufs-phy": must contain:
- "ufsphy".
- For "qcom,msm8996-qmp-usb3-phy" must contain
- "phy", "common".
- For "qcom,msm8998-qmp-usb3-phy" must contain
- "phy", "common".
- For "qcom,msm8998-qmp-ufs-phy": must contain:
- "ufsphy".
- For "qcom,msm8998-qmp-pcie-phy" must contain:
- "phy", "common".
- For "qcom,sdm845-qhp-pcie-phy" must contain:
- "phy".
- For "qcom,sdm845-qmp-pcie-phy" must contain:
- "phy".
- For "qcom,sdm845-qmp-usb3-phy" must contain:
- "phy", "common".
- For "qcom,sdm845-qmp-usb3-uni-phy" must contain:
- "phy", "common".
- For "qcom,sdm845-qmp-ufs-phy": must contain:
- "ufsphy".
- For "qcom,sm8150-qmp-ufs-phy": must contain:
- "ufsphy".
- For "qcom,sm8250-qmp-ufs-phy": must contain:
- "ufsphy".
-
- - vdda-phy-supply: Phandle to a regulator supply to PHY core block.
- - vdda-pll-supply: Phandle to 1.8V regulator supply to PHY refclk pll block.
-
-Optional properties:
- - vddp-ref-clk-supply: Phandle to a regulator supply to any specific refclk
- pll block.
-
-Required nodes:
- - Each device node of QMP phy is required to have as many child nodes as
- the number of lanes the PHY has.
-
-Required properties for child nodes of PCIe PHYs (one child per lane):
- - reg: list of offset and length pairs of register sets for PHY blocks -
- tx, rx, pcs, and pcs_misc (optional).
- - #phy-cells: must be 0
-
-Required properties for a single "lanes" child node of non-PCIe PHYs:
- - reg: list of offset and length pairs of register sets for PHY blocks
- For 1-lane devices:
- tx, rx, pcs, and (optionally) pcs_misc
- For 2-lane devices:
- tx0, rx0, pcs, tx1, rx1, and (optionally) pcs_misc
- - #phy-cells: must be 0
-
-Required properties for child node of PCIe and USB3 qmp phys:
- - clocks: a list of phandles and clock-specifier pairs,
- one for each entry in clock-names.
- - clock-names: Must contain following:
- "pipe<lane-number>" for pipe clock specific to each lane.
- - clock-output-names: Name of the PHY clock that will be the parent for
- the above pipe clock.
- For "qcom,ipq8074-qmp-pcie-phy":
- - "pcie20_phy0_pipe_clk" Pipe Clock parent
- (or)
- "pcie20_phy1_pipe_clk"
- - #clock-cells: must be 0
- - Phy pll outputs pipe clocks for pipe based PHYs. These clocks are then
- gate-controlled by the gcc.
-
-Required properties for child node of PHYs with lane reset, AKA:
- "qcom,msm8996-qmp-pcie-phy"
- - resets: a list of phandles and reset controller specifier pairs,
- one for each entry in reset-names.
- - reset-names: Must contain following:
- "lane<lane-number>" for reset specific to each lane.
-
-Example:
- phy@34000 {
- compatible = "qcom,msm8996-qmp-pcie-phy";
- reg = <0x34000 0x488>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
- <&gcc GCC_PCIE_PHY_CFG_AHB_CLK>,
- <&gcc GCC_PCIE_CLKREF_CLK>;
- clock-names = "aux", "cfg_ahb", "ref";
-
- vdda-phy-supply = <&pm8994_l28>;
- vdda-pll-supply = <&pm8994_l12>;
-
- resets = <&gcc GCC_PCIE_PHY_BCR>,
- <&gcc GCC_PCIE_PHY_COM_BCR>,
- <&gcc GCC_PCIE_PHY_COM_NOCSR_BCR>;
- reset-names = "phy", "common", "cfg";
-
- pciephy_0: lane@35000 {
- reg = <0x35000 0x130>,
- <0x35200 0x200>,
- <0x35400 0x1dc>;
- #clock-cells = <0>;
- #phy-cells = <0>;
-
- clocks = <&gcc GCC_PCIE_0_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "pcie_0_pipe_clk_src";
- resets = <&gcc GCC_PCIE_0_PHY_BCR>;
- reset-names = "lane0";
- };
-
- pciephy_1: lane@36000 {
- ...
- ...
- };
-
- phy@88eb000 {
- compatible = "qcom,sdm845-qmp-usb3-uni-phy";
- reg = <0x88eb000 0x18c>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
-
- clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK>,
- <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
- <&gcc GCC_USB3_SEC_CLKREF_CLK>,
- <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
- clock-names = "aux", "cfg_ahb", "ref", "com_aux";
-
- resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
- <&gcc GCC_USB3_PHY_SEC_BCR>;
- reset-names = "phy", "common";
-
- lane@88eb200 {
- reg = <0x88eb200 0x128>,
- <0x88eb400 0x1fc>,
- <0x88eb800 0x218>,
- <0x88eb600 0x70>;
- #clock-cells = <0>;
- #phy-cells = <0>;
- clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
- clock-names = "pipe0";
- clock-output-names = "usb3_uni_phy_pipe_clk_src";
- };
- };
-
- phy@1d87000 {
- compatible = "qcom,sdm845-qmp-ufs-phy";
- reg = <0x1d87000 0x18c>;
- #address-cells = <1>;
- #size-cells = <1>;
- ranges;
- clock-names = "ref",
- "ref_aux";
- clocks = <&gcc GCC_UFS_MEM_CLKREF_CLK>,
- <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
-
- lanes@1d87400 {
- reg = <0x1d87400 0x108>,
- <0x1d87600 0x1e0>,
- <0x1d87c00 0x1dc>,
- <0x1d87800 0x108>,
- <0x1d87a00 0x1e0>;
- #phy-cells = <0>;
- };
- };
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v7 2/4] dt-bindings: phy: qcom,qmp-usb3-dp: Add dt bindings for USB3 DP PHY
2020-05-15 2:39 [PATCH v7 0/4] Add QMP V3 USB3 PHY support for SC7180 Sandeep Maheswaram
2020-05-15 2:39 ` [PATCH v7 1/4] dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml Sandeep Maheswaram
@ 2020-05-15 2:39 ` Sandeep Maheswaram
2020-05-15 18:39 ` Matthias Kaehlcke
2020-05-26 21:25 ` Rob Herring
2020-05-15 2:39 ` [PATCH v7 3/4] dt-bindings: phy: qcom,qmp-usb3-dp: Add support for SC7180 Sandeep Maheswaram
` (2 subsequent siblings)
4 siblings, 2 replies; 10+ messages in thread
From: Sandeep Maheswaram @ 2020-05-15 2:39 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring,
Mark Rutland, Stephen Boyd, Doug Anderson, Matthias Kaehlcke
Cc: linux-arm-msm, linux-kernel, devicetree, Manu Gautam, Sandeep Maheswaram
Split out the dt bindings for USB3 DP PHY from qcom,qmp bindings
for modularity.
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
---
.../devicetree/bindings/phy/qcom,qmp-phy.yaml | 51 +++-----
.../bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 135 +++++++++++++++++++++
2 files changed, 150 insertions(+), 36 deletions(-)
create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
index dcdb014..973b2d1 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
@@ -27,21 +27,13 @@ properties:
- qcom,sdm845-qhp-pcie-phy
- qcom,sdm845-qmp-pcie-phy
- qcom,sdm845-qmp-ufs-phy
- - qcom,sdm845-qmp-usb3-phy
- qcom,sdm845-qmp-usb3-uni-phy
- qcom,sm8150-qmp-ufs-phy
- qcom,sm8250-qmp-ufs-phy
reg:
- minItems: 1
items:
- description: Address and length of PHY's common serdes block.
- - description: Address and length of the DP_COM control block.
-
- reg-names:
- items:
- - const: reg-base
- - const: dp_com
"#clock-cells":
enum: [ 1, 2 ]
@@ -110,7 +102,6 @@ allOf:
compatible:
contains:
enum:
- - qcom,sdm845-qmp-usb3-phy
- qcom,sdm845-qmp-usb3-uni-phy
then:
properties:
@@ -284,51 +275,39 @@ allOf:
reset-names:
items:
- const: phy
- - if:
- properties:
- compatible:
- contains:
- const: qcom,sdm845-qmp-usb3-phy
- then:
- required:
- - reg-names
examples:
- |
#include <dt-bindings/clock/qcom,gcc-sdm845.h>
- usb_1_qmpphy: phy-wrapper@88e9000 {
- compatible = "qcom,sdm845-qmp-usb3-phy";
- reg = <0 0x088e9000 0 0x18c>,
- <0 0x088e8000 0 0x10>;
- reg-names = "reg-base", "dp_com";
+ usb_2_qmpphy: phy-wrapper@88eb000 {
+ compatible = "qcom,sdm845-qmp-usb3-uni-phy";
+ reg = <0 0x088eb000 0 0x18c>;
#clock-cells = <1>;
#address-cells = <2>;
#size-cells = <2>;
- clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >,
<&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
- <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
- <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
+ <&gcc GCC_USB3_SEC_CLKREF_CLK>,
+ <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
clock-names = "aux", "cfg_ahb", "ref", "com_aux";
- resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
- <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
+ resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
+ <&gcc GCC_USB3_PHY_SEC_BCR>;
reset-names = "phy", "common";
vdda-phy-supply = <&vdda_usb2_ss_1p2>;
vdda-pll-supply = <&vdda_usb2_ss_core>;
- usb_1_ssphy: phy@88e9200 {
- reg = <0 0x088e9200 0 0x128>,
- <0 0x088e9400 0 0x200>,
- <0 0x088e9c00 0 0x218>,
- <0 0x088e9600 0 0x128>,
- <0 0x088e9800 0 0x200>,
- <0 0x088e9a00 0 0x100>;
+ usb_2_ssphy: phy@88eb200 {
+ reg = <0 0x088eb200 0 0x128>,
+ <0 0x088eb400 0 0x1fc>,
+ <0 0x088eb800 0 0x218>,
+ <0 0x088eb600 0 0x70>;
#clock-cells = <0>;
#phy-cells = <0>;
- clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
clock-names = "pipe0";
- clock-output-names = "usb3_phy_pipe_clk_src";
+ clock-output-names = "usb3_uni_phy_pipe_clk_src";
};
};
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
new file mode 100644
index 0000000..6055786
--- /dev/null
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
@@ -0,0 +1,135 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+
+%YAML 1.2
+---
+$id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#"
+$schema: "http://devicetree.org/meta-schemas/core.yaml#"
+
+title: Qualcomm QMP USB3 DP PHY controller
+
+maintainers:
+ - Manu Gautam <mgautam@codeaurora.org>
+
+properties:
+ compatible:
+ const:
+ qcom,sdm845-qmp-usb3-phy
+ reg:
+ items:
+ - description: Address and length of PHY's common serdes block.
+ - description: Address and length of the DP_COM control block.
+
+ reg-names:
+ items:
+ - const: reg-base
+ - const: dp_com
+
+ "#clock-cells":
+ enum: [ 1, 2 ]
+
+ "#address-cells":
+ enum: [ 1, 2 ]
+
+ "#size-cells":
+ enum: [ 1, 2 ]
+
+ clocks:
+ items:
+ - description: Phy aux clock.
+ - description: Phy config clock.
+ - description: 19.2 MHz ref clk.
+ - description: Phy common block aux clock.
+
+ clock-names:
+ items:
+ - const: aux
+ - const: cfg_ahb
+ - const: ref
+ - const: com_aux
+
+ resets:
+ items:
+ - description: reset of phy block.
+ - description: phy common block reset.
+
+ reset-names:
+ items:
+ - const: phy
+ - const: common
+
+ vdda-phy-supply:
+ description:
+ Phandle to a regulator supply to PHY core block.
+
+ vdda-pll-supply:
+ description:
+ Phandle to 1.8V regulator supply to PHY refclk pll block.
+
+ vddp-ref-clk-supply:
+ description:
+ Phandle to a regulator supply to any specific refclk
+ pll block.
+
+#Required nodes:
+patternProperties:
+ "^phy@[0-9a-f]+$":
+ type: object
+ description:
+ Each device node of QMP phy is required to have as many child nodes as
+ the number of lanes the PHY has.
+
+required:
+ - compatible
+ - reg
+ - reg-names
+ - "#clock-cells"
+ - "#address-cells"
+ - "#size-cells"
+ - clocks
+ - clock-names
+ - resets
+ - reset-names
+ - vdda-phy-supply
+ - vdda-pll-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/qcom,gcc-sdm845.h>
+ usb_1_qmpphy: phy-wrapper@88e9000 {
+ compatible = "qcom,sdm845-qmp-usb3-phy";
+ reg = <0 0x088e9000 0 0x18c>,
+ <0 0x088e8000 0 0x10>;
+ reg-names = "reg-base", "dp_com";
+ #clock-cells = <1>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
+ <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
+ <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
+ <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
+ clock-names = "aux", "cfg_ahb", "ref", "com_aux";
+
+ resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
+ <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
+ reset-names = "phy", "common";
+
+ vdda-phy-supply = <&vdda_usb2_ss_1p2>;
+ vdda-pll-supply = <&vdda_usb2_ss_core>;
+
+ usb_1_ssphy: phy@88e9200 {
+ reg = <0 0x088e9200 0 0x128>,
+ <0 0x088e9400 0 0x200>,
+ <0 0x088e9c00 0 0x218>,
+ <0 0x088e9600 0 0x128>,
+ <0 0x088e9800 0 0x200>,
+ <0 0x088e9a00 0 0x100>;
+ #clock-cells = <0>;
+ #phy-cells = <0>;
+ clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
+ clock-names = "pipe0";
+ clock-output-names = "usb3_phy_pipe_clk_src";
+ };
+ };
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v7 3/4] dt-bindings: phy: qcom,qmp-usb3-dp: Add support for SC7180
2020-05-15 2:39 [PATCH v7 0/4] Add QMP V3 USB3 PHY support for SC7180 Sandeep Maheswaram
2020-05-15 2:39 ` [PATCH v7 1/4] dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml Sandeep Maheswaram
2020-05-15 2:39 ` [PATCH v7 2/4] dt-bindings: phy: qcom,qmp-usb3-dp: Add dt bindings for USB3 DP PHY Sandeep Maheswaram
@ 2020-05-15 2:39 ` Sandeep Maheswaram
2020-05-26 21:25 ` Rob Herring
2020-05-15 2:39 ` [PATCH v7 4/4] phy: qcom-qmp: Add QMP V3 USB3 PHY " Sandeep Maheswaram
2020-05-19 6:23 ` [PATCH v7 0/4] " Vinod Koul
4 siblings, 1 reply; 10+ messages in thread
From: Sandeep Maheswaram @ 2020-05-15 2:39 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring,
Mark Rutland, Stephen Boyd, Doug Anderson, Matthias Kaehlcke
Cc: linux-arm-msm, linux-kernel, devicetree, Manu Gautam, Sandeep Maheswaram
Add compatible for SC7180 in QMP USB3 DP PHY bindings.
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
---
Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
index 6055786..b770e63 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
@@ -12,8 +12,9 @@ maintainers:
properties:
compatible:
- const:
- qcom,sdm845-qmp-usb3-phy
+ enum:
+ - qcom,sc7180-qmp-usb3-phy
+ - qcom,sdm845-qmp-usb3-phy
reg:
items:
- description: Address and length of PHY's common serdes block.
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v7 4/4] phy: qcom-qmp: Add QMP V3 USB3 PHY support for SC7180
2020-05-15 2:39 [PATCH v7 0/4] Add QMP V3 USB3 PHY support for SC7180 Sandeep Maheswaram
` (2 preceding siblings ...)
2020-05-15 2:39 ` [PATCH v7 3/4] dt-bindings: phy: qcom,qmp-usb3-dp: Add support for SC7180 Sandeep Maheswaram
@ 2020-05-15 2:39 ` Sandeep Maheswaram
2020-05-19 6:23 ` [PATCH v7 0/4] " Vinod Koul
4 siblings, 0 replies; 10+ messages in thread
From: Sandeep Maheswaram @ 2020-05-15 2:39 UTC (permalink / raw)
To: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring,
Mark Rutland, Stephen Boyd, Doug Anderson, Matthias Kaehlcke
Cc: linux-arm-msm, linux-kernel, devicetree, Manu Gautam, Sandeep Maheswaram
Adding QMP v3 USB3 PHY support for SC7180.
Adding only usb phy reset in the list to avoid
reset of DP block.
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Reviewed-by: Matthias Kaehlcke <mka@chromium.org>
Reviewed-by: Stephen Boyd <swboyd@chromium.org>
---
drivers/phy/qualcomm/phy-qcom-qmp.c | 38 +++++++++++++++++++++++++++++++++++++
1 file changed, 38 insertions(+)
diff --git a/drivers/phy/qualcomm/phy-qcom-qmp.c b/drivers/phy/qualcomm/phy-qcom-qmp.c
index 5942167..3504931 100644
--- a/drivers/phy/qualcomm/phy-qcom-qmp.c
+++ b/drivers/phy/qualcomm/phy-qcom-qmp.c
@@ -1578,6 +1578,10 @@ static const char * const msm8996_usb3phy_reset_l[] = {
"phy", "common",
};
+static const char * const sc7180_usb3phy_reset_l[] = {
+ "phy",
+};
+
static const char * const sdm845_pciephy_reset_l[] = {
"phy",
};
@@ -1791,6 +1795,37 @@ static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = {
.is_dual_lane_phy = true,
};
+static const struct qmp_phy_cfg sc7180_usb3phy_cfg = {
+ .type = PHY_TYPE_USB3,
+ .nlanes = 1,
+
+ .serdes_tbl = qmp_v3_usb3_serdes_tbl,
+ .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl),
+ .tx_tbl = qmp_v3_usb3_tx_tbl,
+ .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl),
+ .rx_tbl = qmp_v3_usb3_rx_tbl,
+ .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl),
+ .pcs_tbl = qmp_v3_usb3_pcs_tbl,
+ .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl),
+ .clk_list = qmp_v3_phy_clk_l,
+ .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l),
+ .reset_list = sc7180_usb3phy_reset_l,
+ .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l),
+ .vreg_list = qmp_phy_vreg_l,
+ .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l),
+ .regs = qmp_v3_usb3phy_regs_layout,
+
+ .start_ctrl = SERDES_START | PCS_START,
+ .pwrdn_ctrl = SW_PWRDN,
+
+ .has_pwrdn_delay = true,
+ .pwrdn_delay_min = POWER_DOWN_DELAY_US_MIN,
+ .pwrdn_delay_max = POWER_DOWN_DELAY_US_MAX,
+
+ .has_phy_dp_com_ctrl = true,
+ .is_dual_lane_phy = true,
+};
+
static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
.type = PHY_TYPE_USB3,
.nlanes = 1,
@@ -2680,6 +2715,9 @@ static const struct of_device_id qcom_qmp_phy_of_match_table[] = {
.compatible = "qcom,ipq8074-qmp-pcie-phy",
.data = &ipq8074_pciephy_cfg,
}, {
+ .compatible = "qcom,sc7180-qmp-usb3-phy",
+ .data = &sc7180_usb3phy_cfg,
+ }, {
.compatible = "qcom,sdm845-qhp-pcie-phy",
.data = &sdm845_qhp_pciephy_cfg,
}, {
--
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
of Code Aurora Forum, hosted by The Linux Foundation
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v7 1/4] dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml
2020-05-15 2:39 ` [PATCH v7 1/4] dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml Sandeep Maheswaram
@ 2020-05-15 18:18 ` Matthias Kaehlcke
0 siblings, 0 replies; 10+ messages in thread
From: Matthias Kaehlcke @ 2020-05-15 18:18 UTC (permalink / raw)
To: Sandeep Maheswaram
Cc: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring,
Mark Rutland, Stephen Boyd, Doug Anderson, linux-arm-msm,
linux-kernel, devicetree, Manu Gautam
On Fri, May 15, 2020 at 08:09:15AM +0530, Sandeep Maheswaram wrote:
> Convert QMP PHY bindings to DT schema format using json-schema.
>
> Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
This is essentially the same as v5, for which got a 'Reviewed-by' tag
from Rob:
diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
index 18a8985e54d5..dcdb014d6d4d 100644
--- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
+++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
@@ -30,6 +30,7 @@ properties:
- qcom,sdm845-qmp-usb3-phy
- qcom,sdm845-qmp-usb3-uni-phy
- qcom,sm8150-qmp-ufs-phy
+ - qcom,sm8250-qmp-ufs-phy
reg:
minItems: 1
@@ -217,6 +218,7 @@ allOf:
- qcom,msm8998-qmp-ufs-phy
- qcom,sdm845-qmp-ufs-phy
- qcom,sm8150-qmp-ufs-phy
+ - qcom,sm8250-qmp-ufs-phy
then:
properties:
clocks:
I think it would have been ok to add Rob's 'Reviewed-by' tag and save
him the time to look at this again.
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v7 2/4] dt-bindings: phy: qcom,qmp-usb3-dp: Add dt bindings for USB3 DP PHY
2020-05-15 2:39 ` [PATCH v7 2/4] dt-bindings: phy: qcom,qmp-usb3-dp: Add dt bindings for USB3 DP PHY Sandeep Maheswaram
@ 2020-05-15 18:39 ` Matthias Kaehlcke
2020-05-26 21:25 ` Rob Herring
1 sibling, 0 replies; 10+ messages in thread
From: Matthias Kaehlcke @ 2020-05-15 18:39 UTC (permalink / raw)
To: Sandeep Maheswaram
Cc: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring,
Mark Rutland, Stephen Boyd, Doug Anderson, linux-arm-msm,
linux-kernel, devicetree, Manu Gautam
On Fri, May 15, 2020 at 08:09:16AM +0530, Sandeep Maheswaram wrote:
> Subject: dt-bindings: phy: qcom,qmp-usb3-dp: Add dt bindings for USB3 DP PHY
The subject is misleading, this patch doesn't add the binding for the USB3 DP
PHY, but factors it out.
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v7 0/4] Add QMP V3 USB3 PHY support for SC7180
2020-05-15 2:39 [PATCH v7 0/4] Add QMP V3 USB3 PHY support for SC7180 Sandeep Maheswaram
` (3 preceding siblings ...)
2020-05-15 2:39 ` [PATCH v7 4/4] phy: qcom-qmp: Add QMP V3 USB3 PHY " Sandeep Maheswaram
@ 2020-05-19 6:23 ` Vinod Koul
4 siblings, 0 replies; 10+ messages in thread
From: Vinod Koul @ 2020-05-19 6:23 UTC (permalink / raw)
To: Sandeep Maheswaram
Cc: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I, Rob Herring,
Mark Rutland, Stephen Boyd, Doug Anderson, Matthias Kaehlcke,
linux-arm-msm, linux-kernel, devicetree, Manu Gautam
On 15-05-20, 08:09, Sandeep Maheswaram wrote:
> Add QMP V3 USB3 PHY entries for SC7180 in phy driver and
> device tree bindings.
Applied all, thanks
--
~Vinod
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v7 2/4] dt-bindings: phy: qcom,qmp-usb3-dp: Add dt bindings for USB3 DP PHY
2020-05-15 2:39 ` [PATCH v7 2/4] dt-bindings: phy: qcom,qmp-usb3-dp: Add dt bindings for USB3 DP PHY Sandeep Maheswaram
2020-05-15 18:39 ` Matthias Kaehlcke
@ 2020-05-26 21:25 ` Rob Herring
1 sibling, 0 replies; 10+ messages in thread
From: Rob Herring @ 2020-05-26 21:25 UTC (permalink / raw)
To: Sandeep Maheswaram
Cc: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I,
Mark Rutland, Stephen Boyd, Doug Anderson, Matthias Kaehlcke,
linux-arm-msm, linux-kernel, devicetree, Manu Gautam
On Fri, May 15, 2020 at 08:09:16AM +0530, Sandeep Maheswaram wrote:
> Split out the dt bindings for USB3 DP PHY from qcom,qmp bindings
> for modularity.
>
> Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
> ---
> .../devicetree/bindings/phy/qcom,qmp-phy.yaml | 51 +++-----
> .../bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 135 +++++++++++++++++++++
> 2 files changed, 150 insertions(+), 36 deletions(-)
> create mode 100644 Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
> index dcdb014..973b2d1 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-phy.yaml
> @@ -27,21 +27,13 @@ properties:
> - qcom,sdm845-qhp-pcie-phy
> - qcom,sdm845-qmp-pcie-phy
> - qcom,sdm845-qmp-ufs-phy
> - - qcom,sdm845-qmp-usb3-phy
> - qcom,sdm845-qmp-usb3-uni-phy
> - qcom,sm8150-qmp-ufs-phy
> - qcom,sm8250-qmp-ufs-phy
>
> reg:
> - minItems: 1
> items:
> - description: Address and length of PHY's common serdes block.
> - - description: Address and length of the DP_COM control block.
> -
> - reg-names:
> - items:
> - - const: reg-base
> - - const: dp_com
>
> "#clock-cells":
> enum: [ 1, 2 ]
> @@ -110,7 +102,6 @@ allOf:
> compatible:
> contains:
> enum:
> - - qcom,sdm845-qmp-usb3-phy
> - qcom,sdm845-qmp-usb3-uni-phy
> then:
> properties:
> @@ -284,51 +275,39 @@ allOf:
> reset-names:
> items:
> - const: phy
> - - if:
> - properties:
> - compatible:
> - contains:
> - const: qcom,sdm845-qmp-usb3-phy
> - then:
> - required:
> - - reg-names
>
> examples:
> - |
> #include <dt-bindings/clock/qcom,gcc-sdm845.h>
> - usb_1_qmpphy: phy-wrapper@88e9000 {
> - compatible = "qcom,sdm845-qmp-usb3-phy";
> - reg = <0 0x088e9000 0 0x18c>,
> - <0 0x088e8000 0 0x10>;
> - reg-names = "reg-base", "dp_com";
> + usb_2_qmpphy: phy-wrapper@88eb000 {
> + compatible = "qcom,sdm845-qmp-usb3-uni-phy";
> + reg = <0 0x088eb000 0 0x18c>;
> #clock-cells = <1>;
> #address-cells = <2>;
> #size-cells = <2>;
>
> - clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
> + clocks = <&gcc GCC_USB3_SEC_PHY_AUX_CLK >,
> <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
> - <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
> - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
> + <&gcc GCC_USB3_SEC_CLKREF_CLK>,
> + <&gcc GCC_USB3_SEC_PHY_COM_AUX_CLK>;
> clock-names = "aux", "cfg_ahb", "ref", "com_aux";
>
> - resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
> - <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
> + resets = <&gcc GCC_USB3PHY_PHY_SEC_BCR>,
> + <&gcc GCC_USB3_PHY_SEC_BCR>;
> reset-names = "phy", "common";
>
> vdda-phy-supply = <&vdda_usb2_ss_1p2>;
> vdda-pll-supply = <&vdda_usb2_ss_core>;
>
> - usb_1_ssphy: phy@88e9200 {
> - reg = <0 0x088e9200 0 0x128>,
> - <0 0x088e9400 0 0x200>,
> - <0 0x088e9c00 0 0x218>,
> - <0 0x088e9600 0 0x128>,
> - <0 0x088e9800 0 0x200>,
> - <0 0x088e9a00 0 0x100>;
> + usb_2_ssphy: phy@88eb200 {
> + reg = <0 0x088eb200 0 0x128>,
> + <0 0x088eb400 0 0x1fc>,
> + <0 0x088eb800 0 0x218>,
> + <0 0x088eb600 0 0x70>;
> #clock-cells = <0>;
> #phy-cells = <0>;
> - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> + clocks = <&gcc GCC_USB3_SEC_PHY_PIPE_CLK>;
> clock-names = "pipe0";
> - clock-output-names = "usb3_phy_pipe_clk_src";
> + clock-output-names = "usb3_uni_phy_pipe_clk_src";
> };
> };
> diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
> new file mode 100644
> index 0000000..6055786
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
> @@ -0,0 +1,135 @@
> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
> +
> +%YAML 1.2
> +---
> +$id: "http://devicetree.org/schemas/phy/qcom,qmp-usb3-dp-phy.yaml#"
> +$schema: "http://devicetree.org/meta-schemas/core.yaml#"
> +
> +title: Qualcomm QMP USB3 DP PHY controller
> +
> +maintainers:
> + - Manu Gautam <mgautam@codeaurora.org>
> +
> +properties:
> + compatible:
> + const:
> + qcom,sdm845-qmp-usb3-phy
> + reg:
> + items:
> + - description: Address and length of PHY's common serdes block.
> + - description: Address and length of the DP_COM control block.
> +
> + reg-names:
> + items:
> + - const: reg-base
> + - const: dp_com
> +
> + "#clock-cells":
> + enum: [ 1, 2 ]
> +
> + "#address-cells":
> + enum: [ 1, 2 ]
> +
> + "#size-cells":
> + enum: [ 1, 2 ]
> +
> + clocks:
> + items:
> + - description: Phy aux clock.
> + - description: Phy config clock.
> + - description: 19.2 MHz ref clk.
> + - description: Phy common block aux clock.
> +
> + clock-names:
> + items:
> + - const: aux
> + - const: cfg_ahb
> + - const: ref
> + - const: com_aux
> +
> + resets:
> + items:
> + - description: reset of phy block.
> + - description: phy common block reset.
> +
> + reset-names:
> + items:
> + - const: phy
> + - const: common
> +
> + vdda-phy-supply:
> + description:
> + Phandle to a regulator supply to PHY core block.
> +
> + vdda-pll-supply:
> + description:
> + Phandle to 1.8V regulator supply to PHY refclk pll block.
> +
> + vddp-ref-clk-supply:
> + description:
> + Phandle to a regulator supply to any specific refclk
> + pll block.
> +
> +#Required nodes:
> +patternProperties:
> + "^phy@[0-9a-f]+$":
> + type: object
> + description:
> + Each device node of QMP phy is required to have as many child nodes as
> + the number of lanes the PHY has.
Probably not a new problem, but where are the child node properties
documented? They need to be added before you duplicate this problem.
> +
> +required:
> + - compatible
> + - reg
> + - reg-names
> + - "#clock-cells"
> + - "#address-cells"
> + - "#size-cells"
> + - clocks
> + - clock-names
> + - resets
> + - reset-names
> + - vdda-phy-supply
> + - vdda-pll-supply
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/qcom,gcc-sdm845.h>
> + usb_1_qmpphy: phy-wrapper@88e9000 {
> + compatible = "qcom,sdm845-qmp-usb3-phy";
> + reg = <0 0x088e9000 0 0x18c>,
> + <0 0x088e8000 0 0x10>;
> + reg-names = "reg-base", "dp_com";
> + #clock-cells = <1>;
> + #address-cells = <2>;
> + #size-cells = <2>;
You're missing 'ranges', so the child addresses are not translatable.
You could also reduce everything to 1 cell as they are contained within
the parent's range.
> +
> + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
> + <&gcc GCC_USB_PHY_CFG_AHB2PHY_CLK>,
> + <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
> + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
> + clock-names = "aux", "cfg_ahb", "ref", "com_aux";
> +
> + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
> + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
> + reset-names = "phy", "common";
> +
> + vdda-phy-supply = <&vdda_usb2_ss_1p2>;
> + vdda-pll-supply = <&vdda_usb2_ss_core>;
> +
> + usb_1_ssphy: phy@88e9200 {
> + reg = <0 0x088e9200 0 0x128>,
> + <0 0x088e9400 0 0x200>,
> + <0 0x088e9c00 0 0x218>,
> + <0 0x088e9600 0 0x128>,
> + <0 0x088e9800 0 0x200>,
> + <0 0x088e9a00 0 0x100>;
> + #clock-cells = <0>;
> + #phy-cells = <0>;
> + clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> + clock-names = "pipe0";
> + clock-output-names = "usb3_phy_pipe_clk_src";
> + };
> + };
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v7 3/4] dt-bindings: phy: qcom,qmp-usb3-dp: Add support for SC7180
2020-05-15 2:39 ` [PATCH v7 3/4] dt-bindings: phy: qcom,qmp-usb3-dp: Add support for SC7180 Sandeep Maheswaram
@ 2020-05-26 21:25 ` Rob Herring
0 siblings, 0 replies; 10+ messages in thread
From: Rob Herring @ 2020-05-26 21:25 UTC (permalink / raw)
To: Sandeep Maheswaram
Cc: Andy Gross, Bjorn Andersson, Kishon Vijay Abraham I,
Mark Rutland, Stephen Boyd, Doug Anderson, Matthias Kaehlcke,
linux-arm-msm, linux-kernel, devicetree, Manu Gautam
On Fri, May 15, 2020 at 08:09:17AM +0530, Sandeep Maheswaram wrote:
> Add compatible for SC7180 in QMP USB3 DP PHY bindings.
>
> Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
> ---
> Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml | 5 +++--
> 1 file changed, 3 insertions(+), 2 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
> index 6055786..b770e63 100644
> --- a/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
> +++ b/Documentation/devicetree/bindings/phy/qcom,qmp-usb3-dp-phy.yaml
> @@ -12,8 +12,9 @@ maintainers:
>
> properties:
> compatible:
> - const:
> - qcom,sdm845-qmp-usb3-phy
> + enum:
> + - qcom,sc7180-qmp-usb3-phy
> + - qcom,sdm845-qmp-usb3-phy
Use enum in the prior patch so this is a oneliner.
> reg:
> items:
> - description: Address and length of PHY's common serdes block.
> --
> QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member
> of Code Aurora Forum, hosted by The Linux Foundation
>
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2020-05-26 21:26 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-05-15 2:39 [PATCH v7 0/4] Add QMP V3 USB3 PHY support for SC7180 Sandeep Maheswaram
2020-05-15 2:39 ` [PATCH v7 1/4] dt-bindings: phy: qcom,qmp: Convert QMP PHY bindings to yaml Sandeep Maheswaram
2020-05-15 18:18 ` Matthias Kaehlcke
2020-05-15 2:39 ` [PATCH v7 2/4] dt-bindings: phy: qcom,qmp-usb3-dp: Add dt bindings for USB3 DP PHY Sandeep Maheswaram
2020-05-15 18:39 ` Matthias Kaehlcke
2020-05-26 21:25 ` Rob Herring
2020-05-15 2:39 ` [PATCH v7 3/4] dt-bindings: phy: qcom,qmp-usb3-dp: Add support for SC7180 Sandeep Maheswaram
2020-05-26 21:25 ` Rob Herring
2020-05-15 2:39 ` [PATCH v7 4/4] phy: qcom-qmp: Add QMP V3 USB3 PHY " Sandeep Maheswaram
2020-05-19 6:23 ` [PATCH v7 0/4] " Vinod Koul
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