From: Stephen Boyd <sboyd@kernel.org>
To: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Cc: heiko@sntech.de, knaerzche@gmail.com,
linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-rockchip@lists.infradead.org,
martin.blumenstingl@googlemail.com
Subject: Re: [PATCH] clk: composite: Also consider .determine_rate for rate + mux composites
Date: Fri, 15 Oct 2021 14:27:05 -0700 [thread overview]
Message-ID: <163433322577.1688384.5988903670868801272@swboyd.mtv.corp.google.com> (raw)
In-Reply-To: <20211015120559.3515645-1-martin.blumenstingl@googlemail.com>
Quoting Martin Blumenstingl (2021-10-15 05:05:59)
> Commit 69a00fb3d69706 ("clk: divider: Implement and wire up
> .determine_rate by default") switches clk_divider_ops to implement
> .determine_rate by default. This breaks composite clocks with multiple
> parents because clk-composite.c does not use the special handling for
> mux + divider combinations anymore (that was restricted to rate clocks
> which only implement .round_rate, but not .determine_rate).
>
> Alex reports:
> This breaks lot of clocks for Rockchip which intensively uses
> composites, i.e. those clocks will always stay at the initial parent,
> which in some cases is the XTAL clock and I strongly guess it is the
> same for other platforms, which use composite clocks having more than
> one parent (e.g. mediatek, ti ...)
>
> Example (RK3399)
> clk_sdio is set (initialized) with XTAL (24 MHz) as parent in u-boot.
> It will always stay at this parent, even if the mmc driver sets a rate
> of 200 MHz (fails, as the nature of things), which should switch it
> to any of its possible parent PLLs defined in
> mux_pll_src_cpll_gpll_npll_ppll_upll_24m_p (see clk-rk3399.c) - which
> never happens.
>
> Restore the original behavior by changing the priority of the conditions
> inside clk-composite.c. Now the special rate + mux case (with rate_ops
> having a .round_rate - which is still the case for the default
> clk_divider_ops) is preferred over rate_ops which have .determine_rate
> defined (and not further considering the mux).
>
> Fixes: 69a00fb3d69706 ("clk: divider: Implement and wire up .determine_rate by default")
> Reported-by: Alex Bee <knaerzche@gmail.com>
> Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
> ---
> Re-sending this as inline patch instead of attaching it.
>
> drivers/clk/clk-composite.c | 10 +++++-----
> 1 file changed, 5 insertions(+), 5 deletions(-)
>
> diff --git a/drivers/clk/clk-composite.c b/drivers/clk/clk-composite.c
> index 0506046a5f4b..510a9965633b 100644
> --- a/drivers/clk/clk-composite.c
> +++ b/drivers/clk/clk-composite.c
> @@ -58,11 +58,8 @@ static int clk_composite_determine_rate(struct clk_hw *hw,
> long rate;
> int i;
>
> - if (rate_hw && rate_ops && rate_ops->determine_rate) {
> - __clk_hw_set_clk(rate_hw, hw);
> - return rate_ops->determine_rate(rate_hw, req);
> - } else if (rate_hw && rate_ops && rate_ops->round_rate &&
> - mux_hw && mux_ops && mux_ops->set_parent) {
> + if (rate_hw && rate_ops && rate_ops->round_rate &&
> + mux_hw && mux_ops && mux_ops->set_parent) {
What do we do if rate_ops and mux_ops only implement determine_rate? It
will fail right? We can't mesh them together in function. We should
probably fail to let the composite clk be registered if that happens.
> req->best_parent_hw = NULL;
>
> if (clk_hw_get_flags(hw) & CLK_SET_RATE_NO_REPARENT) {
> @@ -107,6 +104,9 @@ static int clk_composite_determine_rate(struct clk_hw *hw,
>
> req->rate = best_rate;
> return 0;
> + } else if (rate_hw && rate_ops && rate_ops->determine_rate) {
> + __clk_hw_set_clk(rate_hw, hw);
> + return rate_ops->determine_rate(rate_hw, req);
> } else if (mux_hw && mux_ops && mux_ops->determine_rate) {
> __clk_hw_set_clk(mux_hw, hw);
> return mux_ops->determine_rate(mux_hw, req);
> --
> 2.33.0
>
next prev parent reply other threads:[~2021-10-15 21:27 UTC|newest]
Thread overview: 32+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-07-02 22:51 [PATCH v1 0/6] clk: switch dividers to .determine_rate Martin Blumenstingl
2021-07-02 22:51 ` [PATCH v1 1/6] clk: divider: Implement and wire up .determine_rate by default Martin Blumenstingl
2021-08-06 1:10 ` Stephen Boyd
2021-10-14 9:55 ` Alex Bee
2021-10-14 12:11 ` Martin Blumenstingl
2021-10-14 21:34 ` Martin Blumenstingl
2021-10-14 22:52 ` Stephen Boyd
2021-10-15 12:05 ` [PATCH] clk: composite: Also consider .determine_rate for rate + mux composites Martin Blumenstingl
2021-10-15 21:27 ` Stephen Boyd [this message]
2021-11-01 20:19 ` Guillaume Tucker
2021-11-01 20:58 ` Martin Blumenstingl
2021-11-01 21:59 ` Robin Murphy
2021-11-01 22:11 ` Robin Murphy
2021-11-01 22:41 ` Alex Bee
2021-11-02 7:58 ` Guillaume Tucker
2021-11-02 21:40 ` LABBE Corentin
2021-10-15 19:14 ` [PATCH v1 1/6] clk: divider: Implement and wire up .determine_rate by default Alex Bee
2021-10-15 21:31 ` Stephen Boyd
2021-07-02 22:51 ` [PATCH v1 2/6] clk: imx: clk-divider-gate: Switch to clk_divider.determine_rate Martin Blumenstingl
2021-07-19 10:43 ` Abel Vesa
2021-07-29 11:30 ` Abel Vesa
2021-07-02 22:51 ` [PATCH v1 3/6] clk: bcm2835: " Martin Blumenstingl
2021-07-05 6:57 ` Marek Szyprowski
2021-08-06 1:10 ` Stephen Boyd
2021-07-02 22:51 ` [PATCH v1 4/6] clk: stm32f4: " Martin Blumenstingl
2021-08-06 1:10 ` Stephen Boyd
2021-07-02 22:51 ` [PATCH v1 5/6] clk: stm32h7: " Martin Blumenstingl
2021-08-06 1:10 ` Stephen Boyd
2021-07-02 22:51 ` [PATCH v1 6/6] clk: stm32mp1: " Martin Blumenstingl
2021-08-06 1:10 ` Stephen Boyd
2021-08-03 19:32 ` [PATCH v1 0/6] clk: switch dividers to .determine_rate Martin Blumenstingl
2021-08-03 20:16 ` Stephen Boyd
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