From: "Radim Krčmář" <rkrcmar@redhat.com>
To: Paolo Bonzini <pbonzini@redhat.com>
Cc: linux-kernel@vger.kernel.org, kvm@vger.kernel.org
Subject: Re: [PATCH 5/6] KVM: x86: do not scan IRR twice on APICv vmentry
Date: Tue, 7 Feb 2017 21:19:55 +0100 [thread overview]
Message-ID: <20170207201955.GD31091@potion> (raw)
In-Reply-To: <1482164232-130035-6-git-send-email-pbonzini@redhat.com>
2016-12-19 17:17+0100, Paolo Bonzini:
> Calls to apic_find_highest_irr are scanning IRR twice, once
> in vmx_sync_pir_from_irr and once in apic_search_irr. Change
> sync_pir_from_irr to get the new maximum IRR from kvm_apic_update_irr;
> now that it does the computation, it can also do the RVI write.
>
> In order to avoid complications in svm.c, make the callback optional.
>
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
> diff --git a/arch/x86/kvm/vmx.c b/arch/x86/kvm/vmx.c
> @@ -8734,20 +8736,24 @@ static void vmx_hwapic_irr_update(struct kvm_vcpu *vcpu, int max_irr)
> }
> }
>
> -static void vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
> +static int vmx_sync_pir_to_irr(struct kvm_vcpu *vcpu)
> {
> struct vcpu_vmx *vmx = to_vmx(vcpu);
> + int max_irr;
>
> - if (!pi_test_on(&vmx->pi_desc))
> - return;
> -
> - pi_clear_on(&vmx->pi_desc);
> - /*
> - * IOMMU can write to PIR.ON, so the barrier matters even on UP.
> - * But on x86 this is just a compiler barrier anyway.
> - */
> - smp_mb__after_atomic();
> - kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
> + if (vcpu->arch.apicv_active && pi_test_on(&vmx->pi_desc)) {
> + pi_clear_on(&vmx->pi_desc);
> + /*
> + * IOMMU can write to PIR.ON, so the barrier matters even on UP.
> + * But on x86 this is just a compiler barrier anyway.
> + */
> + smp_mb__after_atomic();
> + max_irr = kvm_apic_update_irr(vcpu, vmx->pi_desc.pir);
> + } else {
> + max_irr = kvm_lapic_find_highest_irr(vcpu);
> + }
> + vmx_hwapic_irr_update(vcpu, max_irr);
Btw. a v1 discussion revolved about the need to have
vmx_hwapic_irr_update() here when the maximal IRR should always be in
RVI, and, uh, I didn't follow up (negligible attention span) ...
There is one place where that doesn't hold: we don't update RVI after a
EXTERNAL_INTERRUPT nested VM exit without VM_EXIT_ACK_INTR_ON_EXIT, but
IRR has likely changed. Isn't that the problem?
next prev parent reply other threads:[~2017-02-07 20:20 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-12-19 16:17 [PATCH v2 0/6] KVM: x86: cleanup and speedup for APICv Paolo Bonzini
2016-12-19 16:17 ` [PATCH 1/6] KVM: vmx: clear pending interrupts on KVM_SET_LAPIC Paolo Bonzini
2017-02-07 17:42 ` Radim Krčmář
2016-12-19 16:17 ` [PATCH 2/6] kvm: nVMX: move nested events check to kvm_vcpu_running Paolo Bonzini
2017-02-07 18:16 ` Radim Krčmář
2016-12-19 16:17 ` [PATCH 3/6] KVM: x86: preparatory changes for APICv cleanups Paolo Bonzini
2017-02-07 18:20 ` Radim Krčmář
2016-12-19 16:17 ` [PATCH 4/6] KVM: vmx: move sync_pir_to_irr from apic_find_highest_irr to callers Paolo Bonzini
2016-12-19 16:17 ` [PATCH 5/6] KVM: x86: do not scan IRR twice on APICv vmentry Paolo Bonzini
2017-02-07 20:19 ` Radim Krčmář [this message]
2017-02-07 21:49 ` Radim Krčmář
2017-02-08 14:10 ` Paolo Bonzini
2017-02-08 14:24 ` Radim Krčmář
2016-12-19 16:17 ` [PATCH 6/6] kvm: x86: do not use KVM_REQ_EVENT for APICv interrupt injection Paolo Bonzini
2017-02-07 19:58 ` Radim Krčmář
2017-02-08 16:23 ` Paolo Bonzini
2017-02-09 15:11 ` Radim Krčmář
2017-03-09 1:23 ` Wanpeng Li
2017-03-09 9:40 ` Wanpeng Li
2017-03-09 10:03 ` Paolo Bonzini
2017-02-07 17:23 ` [PATCH v2 0/6] KVM: x86: cleanup and speedup for APICv Paolo Bonzini
2017-02-07 21:52 ` Radim Krčmář
2017-02-08 10:04 ` Paolo Bonzini
2017-02-08 13:33 ` Radim Krčmář
2017-02-08 15:01 ` Paolo Bonzini
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