linux-kernel.vger.kernel.org archive mirror
 help / color / mirror / Atom feed
* [PATCH] NET: stmmac: align DMA stuff to largest cache line length
@ 2018-07-26 12:05 Eugeniy Paltsev
  2018-07-29 19:35 ` David Miller
  0 siblings, 1 reply; 2+ messages in thread
From: Eugeniy Paltsev @ 2018-07-26 12:05 UTC (permalink / raw)
  To: netdev
  Cc: linux-kernel, linux-snps-arc, David S . Miller, Jose Abreu,
	Alexandre Torgue, Giuseppe Cavallaro, Eugeniy Paltsev

As for today STMMAC_ALIGN macro (which is used to align DMA stuff)
relies on L1 line length (L1_CACHE_BYTES).
This isn't correct in case of system with several cache levels
which might have L1 cache line length smaller than L2 line. This
can lead to sharing one cache line between DMA buffer and other
data, so we can lose this data while invalidate DMA buffer before
DMA transaction.

Fix that by using SMP_CACHE_BYTES instead of L1_CACHE_BYTES for
aligning.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
---
 drivers/net/ethernet/stmicro/stmmac/stmmac_main.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
index 60f59abab009..ef6a8d39db2f 100644
--- a/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
+++ b/drivers/net/ethernet/stmicro/stmmac/stmmac_main.c
@@ -53,7 +53,7 @@
 #include "dwmac1000.h"
 #include "hwif.h"
 
-#define STMMAC_ALIGN(x)	L1_CACHE_ALIGN(x)
+#define	STMMAC_ALIGN(x)		__ALIGN_KERNEL(x, SMP_CACHE_BYTES)
 #define	TSO_MAX_BUFF_SIZE	(SZ_16K - 1)
 
 /* Module parameters */
-- 
2.14.4


^ permalink raw reply related	[flat|nested] 2+ messages in thread

* Re: [PATCH] NET: stmmac: align DMA stuff to largest cache line length
  2018-07-26 12:05 [PATCH] NET: stmmac: align DMA stuff to largest cache line length Eugeniy Paltsev
@ 2018-07-29 19:35 ` David Miller
  0 siblings, 0 replies; 2+ messages in thread
From: David Miller @ 2018-07-29 19:35 UTC (permalink / raw)
  To: Eugeniy.Paltsev
  Cc: netdev, linux-kernel, linux-snps-arc, Jose.Abreu,
	alexandre.torgue, peppe.cavallaro

From: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Date: Thu, 26 Jul 2018 15:05:37 +0300

> As for today STMMAC_ALIGN macro (which is used to align DMA stuff)
> relies on L1 line length (L1_CACHE_BYTES).
> This isn't correct in case of system with several cache levels
> which might have L1 cache line length smaller than L2 line. This
> can lead to sharing one cache line between DMA buffer and other
> data, so we can lose this data while invalidate DMA buffer before
> DMA transaction.
> 
> Fix that by using SMP_CACHE_BYTES instead of L1_CACHE_BYTES for
> aligning.
> 
> Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>

This is definitely an improvement, so applied and queued up for
-stable.

There is also dma_get_cache_alignment(), so maybe we can eventually
use that here instead.

^ permalink raw reply	[flat|nested] 2+ messages in thread

end of thread, other threads:[~2018-07-29 19:35 UTC | newest]

Thread overview: 2+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2018-07-26 12:05 [PATCH] NET: stmmac: align DMA stuff to largest cache line length Eugeniy Paltsev
2018-07-29 19:35 ` David Miller

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).