From: "Moger, Babu" <Babu.Moger@amd.com>
To: "tglx@linutronix.de" <tglx@linutronix.de>,
"mingo@redhat.com" <mingo@redhat.com>,
"hpa@zytor.com" <hpa@zytor.com>,
"fenghua.yu@intel.com" <fenghua.yu@intel.com>,
"reinette.chatre@intel.com" <reinette.chatre@intel.com>,
"vikas.shivappa@linux.intel.com" <vikas.shivappa@linux.intel.com>,
"tony.luck@intel.com" <tony.luck@intel.com>
Cc: "x86@kernel.org" <x86@kernel.org>,
"peterz@infradead.org" <peterz@infradead.org>,
"Moger, Babu" <Babu.Moger@amd.com>,
"pombredanne@nexb.com" <pombredanne@nexb.com>,
"gregkh@linuxfoundation.org" <gregkh@linuxfoundation.org>,
"kstewart@linuxfoundation.org" <kstewart@linuxfoundation.org>,
"bp@suse.de" <bp@suse.de>,
"rafael.j.wysocki@intel.com" <rafael.j.wysocki@intel.com>,
"ak@linux.intel.com" <ak@linux.intel.com>,
"kirill.shutemov@linux.intel.com"
<kirill.shutemov@linux.intel.com>,
"xiaochen.shen@intel.com" <xiaochen.shen@intel.com>,
"colin.king@canonical.com" <colin.king@canonical.com>,
"Hurwitz, Sherry" <sherry.hurwitz@amd.com>,
"Lendacky, Thomas" <Thomas.Lendacky@amd.com>,
"pbonzini@redhat.com" <pbonzini@redhat.com>,
"dwmw@amazon.co.uk" <dwmw@amazon.co.uk>,
"luto@kernel.org" <luto@kernel.org>,
"jroedel@suse.de" <jroedel@suse.de>,
"jannh@google.com" <jannh@google.com>,
"dima@arista.com" <dima@arista.com>,
"jpoimboe@redhat.com" <jpoimboe@redhat.com>,
"vkuznets@redhat.com" <vkuznets@redhat.com>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: [RFC PATCH 07/10] arch/x86: Bring few more functions into the resource structure
Date: Mon, 24 Sep 2018 19:19:09 +0000 [thread overview]
Message-ID: <20180924191841.29111-8-babu.moger@amd.com> (raw)
In-Reply-To: <20180924191841.29111-1-babu.moger@amd.com>
Bring all resource functions that are different between the vendors
into resource structure and initialize them dynamically.
Implement these functions separately for each vendors.
update_mba_bw : Feedback loop bandwidth update functionality is not
needed for AMD.
cbm_validate : Cache bitmask validate function. AMD allows
non-contiguous masks. So, use separate functions for
Intel and AMD.
Signed-off-by: Babu Moger <babu.moger@amd.com>
---
arch/x86/kernel/cpu/rdt.c | 17 +++++++++++++----
arch/x86/kernel/cpu/rdt.h | 19 +++++++++++++------
arch/x86/kernel/cpu/rdt_ctrlmondata.c | 4 ++--
arch/x86/kernel/cpu/rdt_monitor.c | 10 +++++++---
4 files changed, 35 insertions(+), 15 deletions(-)
diff --git a/arch/x86/kernel/cpu/rdt.c b/arch/x86/kernel/cpu/rdt.c
index 6dec45bf81d6..ae26b9b3fafa 100644
--- a/arch/x86/kernel/cpu/rdt.c
+++ b/arch/x86/kernel/cpu/rdt.c
@@ -867,10 +867,19 @@ static __init void rdt_init_res_defs_intel(void)
struct rdt_resource *r;
for_each_rdt_resource(r) {
- if (r->rid == RDT_RESOURCE_MBA) {
- r->msr_base = IA32_MBA_THRTL_BASE;
- r->msr_update = mba_wrmsr;
- r->parse_ctrlval = parse_bw;
+ if ((r->rid == RDT_RESOURCE_L3) ||
+ (r->rid == RDT_RESOURCE_L3DATA) ||
+ (r->rid == RDT_RESOURCE_L3CODE) ||
+ (r->rid == RDT_RESOURCE_L2) ||
+ (r->rid == RDT_RESOURCE_L2DATA) ||
+ (r->rid == RDT_RESOURCE_L2CODE))
+ r->cbm_validate = cbm_validate;
+
+ else if (r->rid == RDT_RESOURCE_MBA) {
+ r->msr_base = IA32_MBA_THRTL_BASE;
+ r->msr_update = mba_wrmsr;
+ r->parse_ctrlval = parse_bw;
+ r->update_mba_bw = update_mba_bw;
}
}
}
diff --git a/arch/x86/kernel/cpu/rdt.h b/arch/x86/kernel/cpu/rdt.h
index 2569c10c37f4..7205157d359b 100644
--- a/arch/x86/kernel/cpu/rdt.h
+++ b/arch/x86/kernel/cpu/rdt.h
@@ -386,9 +386,9 @@ static inline bool is_mbm_event(int e)
* struct rdt_resource - attributes of an RDT resource
* @rid: The index of the resource
* @alloc_enabled: Is allocation enabled on this machine
- * @mon_enabled: Is monitoring enabled for this feature
+ * @mon_enabled: Is monitoring enabled for this feature
* @alloc_capable: Is allocation available on this machine
- * @mon_capable: Is monitor feature available on this machine
+ * @mon_capable: Is monitor feature available on this machine
* @name: Name to use in "schemata" file
* @num_closid: Number of CLOSIDs available
* @cache_level: Which cache level defines scope of this resource
@@ -400,10 +400,12 @@ static inline bool is_mbm_event(int e)
* @cache: Cache allocation related data
* @format_str: Per resource format string to show domain value
* @parse_ctrlval: Per resource function pointer to parse control values
- * @evt_list: List of monitoring events
- * @num_rmid: Number of RMIDs available
- * @mon_scale: cqm counter * mon_scale = occupancy in bytes
- * @fflags: flags to choose base and info files
+ * @update_mba_bw: Feedback loop for MBA software controllerer function
+ * @cbm_validate Cache bitmask validate function
+ * @evt_list: List of monitoring events
+ * @num_rmid: Number of RMIDs available
+ * @mon_scale: cqm counter * mon_scale = occupancy in bytes
+ * @fflags: flags to choose base and info files
*/
struct rdt_resource {
int rid;
@@ -425,6 +427,9 @@ struct rdt_resource {
const char *format_str;
int (*parse_ctrlval) (void *data, struct rdt_resource *r,
struct rdt_domain *d);
+ void (*update_mba_bw) (struct rdtgroup *rgrp,
+ struct rdt_domain *dom_mbm);
+ bool (*cbm_validate) (char *buf, u32 *data, struct rdt_resource *r);
struct list_head evt_list;
int num_rmid;
unsigned int mon_scale;
@@ -562,5 +567,7 @@ void cqm_setup_limbo_handler(struct rdt_domain *dom, unsigned long delay_ms);
void cqm_handle_limbo(struct work_struct *work);
bool has_busy_rmid(struct rdt_resource *r, struct rdt_domain *d);
void __check_limbo(struct rdt_domain *d, bool force_free);
+void update_mba_bw(struct rdtgroup *rgrp, struct rdt_domain *dom_mbm);
+bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r);
#endif /* _ASM_X86_RDT_H */
diff --git a/arch/x86/kernel/cpu/rdt_ctrlmondata.c b/arch/x86/kernel/cpu/rdt_ctrlmondata.c
index 0565c564b297..5a282b6c4bd7 100644
--- a/arch/x86/kernel/cpu/rdt_ctrlmondata.c
+++ b/arch/x86/kernel/cpu/rdt_ctrlmondata.c
@@ -88,7 +88,7 @@ int parse_bw(void *_buf, struct rdt_resource *r, struct rdt_domain *d)
* are allowed (e.g. FFFFH, 0FF0H, 003CH, etc.).
* Additionally Haswell requires at least two bits set.
*/
-static bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r)
+bool cbm_validate(char *buf, u32 *data, struct rdt_resource *r)
{
unsigned long first_bit, zero_bit, val;
unsigned int cbm_len = r->cache.cbm_len;
@@ -153,7 +153,7 @@ int parse_cbm(void *_data, struct rdt_resource *r, struct rdt_domain *d)
return -EINVAL;
}
- if (!cbm_validate(data->buf, &cbm_val, r))
+ if ((r->cbm_validate) && !(r->cbm_validate(data->buf, &cbm_val, r)))
return -EINVAL;
if ((rdtgrp->mode == RDT_MODE_EXCLUSIVE ||
diff --git a/arch/x86/kernel/cpu/rdt_monitor.c b/arch/x86/kernel/cpu/rdt_monitor.c
index 577514cd4a71..0dc0260f10d9 100644
--- a/arch/x86/kernel/cpu/rdt_monitor.c
+++ b/arch/x86/kernel/cpu/rdt_monitor.c
@@ -361,7 +361,7 @@ void mon_event_count(void *info)
* throttle MSRs already have low percentage values. To avoid
* unnecessarily restricting such rdtgroups, we also increase the bandwidth.
*/
-static void update_mba_bw(struct rdtgroup *rgrp, struct rdt_domain *dom_mbm)
+void update_mba_bw(struct rdtgroup *rgrp, struct rdt_domain *dom_mbm)
{
u32 closid, rmid, cur_msr, cur_msr_val, new_msr_val;
struct mbm_state *pmbm_data, *cmbm_data;
@@ -520,6 +520,7 @@ void mbm_handle_overflow(struct work_struct *work)
unsigned long delay = msecs_to_jiffies(MBM_OVERFLOW_INTERVAL);
struct rdtgroup *prgrp, *crgrp;
int cpu = smp_processor_id();
+ struct rdt_resource *r_mba;
struct list_head *head;
struct rdt_domain *d;
@@ -539,8 +540,11 @@ void mbm_handle_overflow(struct work_struct *work)
list_for_each_entry(crgrp, head, mon.crdtgrp_list)
mbm_update(d, crgrp->mon.rmid);
- if (is_mba_sc(NULL))
- update_mba_bw(prgrp, d);
+ if (is_mba_sc(NULL)) {
+ r_mba = &rdt_resources_all[RDT_RESOURCE_MBA];
+ if (r_mba->update_mba_bw)
+ r_mba->update_mba_bw(prgrp, d);
+ }
}
schedule_delayed_work_on(cpu, &d->mbm_over, delay);
--
2.17.1
next prev parent reply other threads:[~2018-09-24 19:19 UTC|newest]
Thread overview: 37+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-24 19:18 [RFC PATCH 00/10] arch/x86: AMD QoS support Moger, Babu
2018-09-24 19:18 ` [RFC PATCH 01/10] arch/x86: Start renaming the rdt files to more generic names Moger, Babu
2018-09-24 19:18 ` [RFC PATCH 02/10] arch/x86: Rename the RDT functions and definitions Moger, Babu
2018-09-24 19:19 ` [RFC PATCH 03/10] arch/x86: Re-arrange RDT init code Moger, Babu
2018-10-02 19:21 ` Reinette Chatre
2018-10-02 23:41 ` Moger, Babu
2018-10-03 18:54 ` Reinette Chatre
2018-10-03 20:12 ` Moger, Babu
2018-09-24 19:19 ` [RFC PATCH 04/10] arch/x86: Introduce a new config parameter PLATFORM_QOS Moger, Babu
2018-09-24 19:19 ` [RFC PATCH 05/10] arch/x86: Use new config parameter PLATFORM_QOS for compilation Moger, Babu
2018-09-24 19:19 ` [RFC PATCH 06/10] arch/x86: Initialize the resource functions that are different Moger, Babu
2018-10-02 22:06 ` Reinette Chatre
2018-10-03 15:25 ` Moger, Babu
2018-09-24 19:19 ` Moger, Babu [this message]
2018-10-02 22:07 ` [RFC PATCH 07/10] arch/x86: Bring few more functions into the resource structure Reinette Chatre
2018-10-03 15:32 ` Moger, Babu
2018-09-24 19:19 ` [RFC PATCH 08/10] arch/x86: Introduce new config parameter AMD_QOS Moger, Babu
2018-09-24 19:19 ` [RFC PATCH 09/10] arch/x86: Add AMD feature bit X86_FEATURE_MBA in cpuid bits array Moger, Babu
2018-09-24 19:19 ` [RFC PATCH 10/10] arch/x86: Introduce QOS feature for AMD Moger, Babu
2018-10-02 18:27 ` Fenghua Yu
2018-10-03 15:56 ` Moger, Babu
2018-10-02 22:13 ` Reinette Chatre
2018-10-03 17:21 ` Moger, Babu
2018-10-05 16:20 ` James Morse
2018-10-05 17:18 ` Moger, Babu
2018-09-27 20:14 ` [RFC PATCH 00/10] arch/x86: AMD QoS support Thomas Gleixner
2018-09-28 1:57 ` Moger, Babu
2018-10-05 16:18 ` James Morse
2018-10-05 17:03 ` Moger, Babu
2018-10-02 17:06 ` Fenghua Yu
2018-10-02 17:44 ` Moger, Babu
2018-10-02 18:46 ` Fenghua Yu
2018-10-02 19:16 ` Moger, Babu
2018-10-03 18:52 ` Fenghua Yu
2018-10-03 19:48 ` Thomas Gleixner
2018-10-03 20:09 ` Moger, Babu
2018-10-05 16:19 ` James Morse
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=20180924191841.29111-8-babu.moger@amd.com \
--to=babu.moger@amd.com \
--cc=Thomas.Lendacky@amd.com \
--cc=ak@linux.intel.com \
--cc=bp@suse.de \
--cc=colin.king@canonical.com \
--cc=dima@arista.com \
--cc=dwmw@amazon.co.uk \
--cc=fenghua.yu@intel.com \
--cc=gregkh@linuxfoundation.org \
--cc=hpa@zytor.com \
--cc=jannh@google.com \
--cc=jpoimboe@redhat.com \
--cc=jroedel@suse.de \
--cc=kirill.shutemov@linux.intel.com \
--cc=kstewart@linuxfoundation.org \
--cc=linux-kernel@vger.kernel.org \
--cc=luto@kernel.org \
--cc=mingo@redhat.com \
--cc=pbonzini@redhat.com \
--cc=peterz@infradead.org \
--cc=pombredanne@nexb.com \
--cc=rafael.j.wysocki@intel.com \
--cc=reinette.chatre@intel.com \
--cc=sherry.hurwitz@amd.com \
--cc=tglx@linutronix.de \
--cc=tony.luck@intel.com \
--cc=vikas.shivappa@linux.intel.com \
--cc=vkuznets@redhat.com \
--cc=x86@kernel.org \
--cc=xiaochen.shen@intel.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).