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* [PATCH RESEND] perf/x86/intel: Bit 13 is valid for Icelake MSR_OFFCORE_RSP_x register
       [not found] <20190724073911.12177-1-yunying.sun@intel.com>
@ 2019-07-24  8:29 ` Yunying Sun
  2019-07-24 13:11   ` Liang, Kan
  2019-07-25 16:06   ` [tip:perf/urgent] perf/x86/intel: Fix invalid Bit 13 " tip-bot for Yunying Sun
  0 siblings, 2 replies; 4+ messages in thread
From: Yunying Sun @ 2019-07-24  8:29 UTC (permalink / raw)
  To: peterz, mingo, acme, alexander.shishkin, jolsa, namhyung, tglx,
	bp, hpa, ak, kan.liang
  Cc: x86, linux-kernel, Yunying Sun

From Intel SDM, bit 13 of Icelake MSR_OFFCORE_RSP_x register is valid for
counting hardware generated prefetches of L3 cache. But current bitmasks
in driver takes bit 13 as invalid. Here to fix it.

Before:
$ perf stat -e cpu/event=0xb7,umask=0x1,config1=0x1bfff/u sleep 3
 Performance counter stats for 'sleep 3':
   <not supported>      cpu/event=0xb7,umask=0x1,config1=0x1bfff/u

After:
$ perf stat -e cpu/event=0xb7,umask=0x1,config1=0x1bfff/u sleep 3
 Performance counter stats for 'sleep 3':
             9,293      cpu/event=0xb7,umask=0x1,config1=0x1bfff/u

Signed-off-by: Yunying Sun <yunying.sun@intel.com>
---
 arch/x86/events/intel/core.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 9e911a96972b..b35519cbc8b4 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -263,8 +263,8 @@ static struct event_constraint intel_icl_event_constraints[] = {
 };
 
 static struct extra_reg intel_icl_extra_regs[] __read_mostly = {
-	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff9fffull, RSP_0),
-	INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff9fffull, RSP_1),
+	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0),
+	INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1),
 	INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 	INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
 	EVENT_EXTRA_END
-- 
2.17.0


^ permalink raw reply related	[flat|nested] 4+ messages in thread
* Re: [PATCH RESEND] perf/x86/intel: Bit 13 is valid for Icelake MSR_OFFCORE_RSP_x register
  2019-07-24  8:29 ` [PATCH RESEND] perf/x86/intel: Bit 13 is valid for Icelake MSR_OFFCORE_RSP_x register Yunying Sun
@ 2019-07-24 13:11   ` Liang, Kan
  2019-07-25  7:50     ` Peter Zijlstra
  2019-07-25 16:06   ` [tip:perf/urgent] perf/x86/intel: Fix invalid Bit 13 " tip-bot for Yunying Sun
  1 sibling, 1 reply; 4+ messages in thread
From: Liang, Kan @ 2019-07-24 13:11 UTC (permalink / raw)
  To: Yunying Sun, peterz, mingo, acme, alexander.shishkin, jolsa,
	namhyung, tglx, bp, hpa, ak
  Cc: x86, linux-kernel



On 7/24/2019 4:29 AM, Yunying Sun wrote:
>  From Intel SDM, bit 13 of Icelake MSR_OFFCORE_RSP_x register is valid for
> counting hardware generated prefetches of L3 cache. But current bitmasks
> in driver takes bit 13 as invalid. Here to fix it.
> 
> Before:
> $ perf stat -e cpu/event=0xb7,umask=0x1,config1=0x1bfff/u sleep 3
>   Performance counter stats for 'sleep 3':
>     <not supported>      cpu/event=0xb7,umask=0x1,config1=0x1bfff/u
> 
> After:
> $ perf stat -e cpu/event=0xb7,umask=0x1,config1=0x1bfff/u sleep 3
>   Performance counter stats for 'sleep 3':
>               9,293      cpu/event=0xb7,umask=0x1,config1=0x1bfff/u
> 
> Signed-off-by: Yunying Sun <yunying.sun@intel.com>

Thanks Yunying.

Reviewed-by: Kan Liang <kan.liang@linux.intel.com>

Kan
> ---
>   arch/x86/events/intel/core.c | 4 ++--
>   1 file changed, 2 insertions(+), 2 deletions(-)
> 
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index 9e911a96972b..b35519cbc8b4 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -263,8 +263,8 @@ static struct event_constraint intel_icl_event_constraints[] = {
>   };
>   
>   static struct extra_reg intel_icl_extra_regs[] __read_mostly = {
> -	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff9fffull, RSP_0),
> -	INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff9fffull, RSP_1),
> +	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0),
> +	INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1),
>   	INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
>   	INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
>   	EVENT_EXTRA_END
> 

^ permalink raw reply	[flat|nested] 4+ messages in thread
* Re: [PATCH RESEND] perf/x86/intel: Bit 13 is valid for Icelake MSR_OFFCORE_RSP_x register
  2019-07-24 13:11   ` Liang, Kan
@ 2019-07-25  7:50     ` Peter Zijlstra
  0 siblings, 0 replies; 4+ messages in thread
From: Peter Zijlstra @ 2019-07-25  7:50 UTC (permalink / raw)
  To: Liang, Kan
  Cc: Yunying Sun, mingo, acme, alexander.shishkin, jolsa, namhyung,
	tglx, bp, hpa, ak, x86, linux-kernel

On Wed, Jul 24, 2019 at 09:11:01AM -0400, Liang, Kan wrote:
> 
> 
> On 7/24/2019 4:29 AM, Yunying Sun wrote:
> >  From Intel SDM, bit 13 of Icelake MSR_OFFCORE_RSP_x register is valid for
> > counting hardware generated prefetches of L3 cache. But current bitmasks
> > in driver takes bit 13 as invalid. Here to fix it.
> > 
> > Before:
> > $ perf stat -e cpu/event=0xb7,umask=0x1,config1=0x1bfff/u sleep 3
> >   Performance counter stats for 'sleep 3':
> >     <not supported>      cpu/event=0xb7,umask=0x1,config1=0x1bfff/u
> > 
> > After:
> > $ perf stat -e cpu/event=0xb7,umask=0x1,config1=0x1bfff/u sleep 3
> >   Performance counter stats for 'sleep 3':
> >               9,293      cpu/event=0xb7,umask=0x1,config1=0x1bfff/u
> > 
> > Signed-off-by: Yunying Sun <yunying.sun@intel.com>
> 
> Thanks Yunying.
> 
> Reviewed-by: Kan Liang <kan.liang@linux.intel.com>

Thanks!

^ permalink raw reply	[flat|nested] 4+ messages in thread
* [tip:perf/urgent] perf/x86/intel: Fix invalid Bit 13 for Icelake MSR_OFFCORE_RSP_x register
  2019-07-24  8:29 ` [PATCH RESEND] perf/x86/intel: Bit 13 is valid for Icelake MSR_OFFCORE_RSP_x register Yunying Sun
  2019-07-24 13:11   ` Liang, Kan
@ 2019-07-25 16:06   ` tip-bot for Yunying Sun
  1 sibling, 0 replies; 4+ messages in thread
From: tip-bot for Yunying Sun @ 2019-07-25 16:06 UTC (permalink / raw)
  To: linux-tip-commits
  Cc: tglx, mingo, peterz, linux-kernel, yunying.sun, hpa, kan.liang, torvalds

Commit-ID:  3b238a64c3009fed36eaea1af629d9377759d87d
Gitweb:     https://git.kernel.org/tip/3b238a64c3009fed36eaea1af629d9377759d87d
Author:     Yunying Sun <yunying.sun@intel.com>
AuthorDate: Wed, 24 Jul 2019 16:29:32 +0800
Committer:  Ingo Molnar <mingo@kernel.org>
CommitDate: Thu, 25 Jul 2019 15:41:30 +0200

perf/x86/intel: Fix invalid Bit 13 for Icelake MSR_OFFCORE_RSP_x register

The Intel SDM states that bit 13 of Icelake's MSR_OFFCORE_RSP_x
register is valid, and used for counting hardware generated prefetches
of L3 cache. Update the bitmask to allow bit 13.

Before:
$ perf stat -e cpu/event=0xb7,umask=0x1,config1=0x1bfff/u sleep 3
 Performance counter stats for 'sleep 3':
   <not supported>      cpu/event=0xb7,umask=0x1,config1=0x1bfff/u

After:
$ perf stat -e cpu/event=0xb7,umask=0x1,config1=0x1bfff/u sleep 3
 Performance counter stats for 'sleep 3':
             9,293      cpu/event=0xb7,umask=0x1,config1=0x1bfff/u

Signed-off-by: Yunying Sun <yunying.sun@intel.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: acme@kernel.org
Cc: alexander.shishkin@linux.intel.com
Cc: bp@alien8.de
Cc: hpa@zytor.com
Cc: jolsa@redhat.com
Cc: namhyung@kernel.org
Link: https://lkml.kernel.org/r/20190724082932.12833-1-yunying.sun@intel.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
---
 arch/x86/events/intel/core.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 9e911a96972b..b35519cbc8b4 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -263,8 +263,8 @@ static struct event_constraint intel_icl_event_constraints[] = {
 };
 
 static struct extra_reg intel_icl_extra_regs[] __read_mostly = {
-	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffff9fffull, RSP_0),
-	INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffff9fffull, RSP_1),
+	INTEL_UEVENT_EXTRA_REG(0x01b7, MSR_OFFCORE_RSP_0, 0x3fffffbfffull, RSP_0),
+	INTEL_UEVENT_EXTRA_REG(0x01bb, MSR_OFFCORE_RSP_1, 0x3fffffbfffull, RSP_1),
 	INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(0x01cd),
 	INTEL_UEVENT_EXTRA_REG(0x01c6, MSR_PEBS_FRONTEND, 0x7fff17, FE),
 	EVENT_EXTRA_END

^ permalink raw reply related	[flat|nested] 4+ messages in thread
end of thread, other threads:[~2019-07-25 16:06 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
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     [not found] <20190724073911.12177-1-yunying.sun@intel.com>
2019-07-24  8:29 ` [PATCH RESEND] perf/x86/intel: Bit 13 is valid for Icelake MSR_OFFCORE_RSP_x register Yunying Sun
2019-07-24 13:11   ` Liang, Kan
2019-07-25  7:50     ` Peter Zijlstra
2019-07-25 16:06   ` [tip:perf/urgent] perf/x86/intel: Fix invalid Bit 13 " tip-bot for Yunying Sun

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