From: Christoph Hellwig <hch@lst.de>
To: Mark Rutland <mark.rutland@arm.com>
Cc: Rob Clark <robdclark@chromium.org>,
Christoph Hellwig <hch@lst.de>, Rob Clark <robdclark@gmail.com>,
dri-devel <dri-devel@lists.freedesktop.org>,
Catalin Marinas <catalin.marinas@arm.com>,
Will Deacon <will@kernel.org>,
Maarten Lankhorst <maarten.lankhorst@linux.intel.com>,
Maxime Ripard <maxime.ripard@bootlin.com>,
Sean Paul <sean@poorly.run>, David Airlie <airlied@linux.ie>,
Daniel Vetter <daniel@ffwll.ch>,
Allison Randal <allison@lohutok.net>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Thomas Gleixner <tglx@linutronix.de>,
linux-arm-kernel@lists.infradead.org,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH 1/2] drm: add cache support for arm64
Date: Thu, 8 Aug 2019 09:58:27 +0200 [thread overview]
Message-ID: <20190808075827.GD30308@lst.de> (raw)
In-Reply-To: <20190807164958.GA44765@lakrids.cambridge.arm.com>
On Wed, Aug 07, 2019 at 05:49:59PM +0100, Mark Rutland wrote:
> I'm fairly confident that the linear/direct map cacheable alias is not
> torn down when pages are allocated. The gneeric page allocation code
> doesn't do so, and I see nothing the shmem code to do so.
It is not torn down anywhere.
> For arm64, we can tear down portions of the linear map, but that has to
> be done explicitly, and this is only possible when using rodata_full. If
> not using rodata_full, it is not possible to dynamically tear down the
> cacheable alias.
Interesting. For this or next merge window I plan to add support to the
generic DMA code to remap pages as uncachable in place based on the
openrisc code. Aѕ far as I can tell the requirement for that is
basically just that the kernel direct mapping doesn't use PMD or bigger
mapping so that it supports changing protection bits on a per-PTE basis.
Is that the case with arm64 + rodata_full?
> > My understanding is that a cacheable alias is "ok", with some
> > caveats.. ie. that the cacheable alias is not accessed.
>
> Unfortunately, that is not true. You'll often get away with it in
> practice, but that's a matter of probability rather than a guarantee.
>
> You cannot prevent a CPU from accessing a VA arbitrarily (e.g. as the
> result of wild speculation). The ARM ARM (ARM DDI 0487E.a) points this
> out explicitly:
Well, if we want to fix this properly we'll have to remap in place
for dma_alloc_coherent and friends.
next prev parent reply other threads:[~2019-08-08 7:58 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-05 21:14 [PATCH 1/2] drm: add cache support for arm64 Rob Clark
2019-08-05 21:14 ` [PATCH 2/2] drm/msm: use drm_cache when available Rob Clark
2019-08-06 8:48 ` [PATCH 1/2] drm: add cache support for arm64 Christoph Hellwig
2019-08-06 9:38 ` Daniel Vetter
2019-08-06 11:38 ` Christoph Hellwig
2019-08-06 14:11 ` Rob Clark
2019-08-06 14:34 ` Mark Rutland
2019-08-06 16:31 ` Rob Clark
2019-08-07 12:38 ` Mark Rutland
2019-08-07 16:15 ` Rob Clark
2019-08-07 16:49 ` Mark Rutland
2019-08-07 17:30 ` Rob Clark
2019-08-08 7:59 ` Christoph Hellwig
2019-08-08 16:44 ` Rob Clark
2019-08-09 8:18 ` Christoph Hellwig
2019-08-08 7:58 ` Christoph Hellwig [this message]
2019-08-08 10:20 ` Mark Rutland
2019-08-08 10:24 ` Mark Rutland
2019-08-08 10:32 ` Will Deacon
2019-08-08 7:53 ` Christoph Hellwig
2019-08-06 15:50 ` Christoph Hellwig
2019-08-06 16:23 ` Rob Clark
2019-08-06 16:26 ` Rob Clark
2019-08-07 6:25 ` Christoph Hellwig
2019-08-07 8:48 ` Daniel Vetter
2019-08-08 9:55 ` Christoph Hellwig
2019-08-08 11:58 ` Daniel Vetter
2019-08-09 8:14 ` Christoph Hellwig
2019-08-07 16:09 ` Rob Clark
2019-08-08 10:00 ` Christoph Hellwig
2019-08-08 16:32 ` Rob Clark
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