From: Peter Zijlstra <peterz@infradead.org>
To: kan.liang@linux.intel.com
Cc: acme@kernel.org, mingo@redhat.com, linux-kernel@vger.kernel.org,
tglx@linutronix.de, jolsa@kernel.org, eranian@google.com,
alexander.shishkin@linux.intel.com, ak@linux.intel.com
Subject: Re: [RESEND PATCH V3 2/8] perf/x86/intel: Basic support for metrics counters
Date: Wed, 28 Aug 2019 10:44:16 +0200 [thread overview]
Message-ID: <20190828084416.GC2369@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <20190826144740.10163-3-kan.liang@linux.intel.com>
On Mon, Aug 26, 2019 at 07:47:34AM -0700, kan.liang@linux.intel.com wrote:
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index 1b2c37ed49db..f4d6335a18e2 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -2131,7 +2131,7 @@ static inline void intel_pmu_ack_status(u64 ack)
>
> static void intel_pmu_disable_fixed(struct hw_perf_event *hwc)
> {
> - int idx = hwc->idx - INTEL_PMC_IDX_FIXED;
> + int idx = get_reg_idx(hwc->idx) - INTEL_PMC_IDX_FIXED;
> u64 ctrl_val, mask;
>
> mask = 0xfULL << (idx * 4);
> @@ -2150,6 +2150,7 @@ static void intel_pmu_disable_event(struct perf_event *event)
> {
> struct hw_perf_event *hwc = &event->hw;
> struct cpu_hw_events *cpuc = this_cpu_ptr(&cpu_hw_events);
> + int reg_idx = get_reg_idx(hwc->idx);
>
> if (unlikely(hwc->idx == INTEL_PMC_IDX_FIXED_BTS)) {
> intel_pmu_disable_bts();
It is unfortunate we need that in both cases; and note how the
inconsitent naming.
> @@ -2157,9 +2158,16 @@ static void intel_pmu_disable_event(struct perf_event *event)
> return;
> }
>
> - cpuc->intel_ctrl_guest_mask &= ~(1ull << hwc->idx);
> - cpuc->intel_ctrl_host_mask &= ~(1ull << hwc->idx);
> - cpuc->intel_cp_status &= ~(1ull << hwc->idx);
> + /*
> + * When any other topdown events are still enabled,
> + * cancel the disabling.
> + */
> + if (has_other_topdown_event(cpuc->active_mask, hwc->idx))
> + return;
And this includes a 3rd instance of that check :/ Also, this really
wants to be in disable_fixed.
> +
> + cpuc->intel_ctrl_guest_mask &= ~(1ull << reg_idx);
> + cpuc->intel_ctrl_host_mask &= ~(1ull << reg_idx);
> + cpuc->intel_cp_status &= ~(1ull << reg_idx);
>
> if (unlikely(hwc->config_base == MSR_ARCH_PERFMON_FIXED_CTR_CTRL))
> intel_pmu_disable_fixed(hwc);
Same for the enable thing.
Let me clean up this mess for you.
next prev parent reply other threads:[~2019-08-28 8:44 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-26 14:47 [RESEND PATCH V3 0/8] TopDown metrics support for Icelake kan.liang
2019-08-26 14:47 ` [RESEND PATCH V3 1/8] perf/x86/intel: Set correct mask for TOPDOWN.SLOTS kan.liang
2019-08-28 7:48 ` Peter Zijlstra
2019-08-26 14:47 ` [RESEND PATCH V3 2/8] perf/x86/intel: Basic support for metrics counters kan.liang
2019-08-28 7:48 ` Peter Zijlstra
2019-08-28 7:52 ` Peter Zijlstra
2019-08-28 13:59 ` Liang, Kan
2019-08-28 8:44 ` Peter Zijlstra [this message]
2019-08-28 9:02 ` Peter Zijlstra
2019-08-28 9:37 ` Peter Zijlstra
2019-08-28 13:51 ` Liang, Kan
2019-08-28 8:52 ` Peter Zijlstra
2019-08-26 14:47 ` [RESEND PATCH V3 3/8] perf/x86/intel: Support hardware TopDown metrics kan.liang
2019-08-28 15:02 ` Peter Zijlstra
2019-08-28 19:04 ` Andi Kleen
2019-08-31 9:19 ` Peter Zijlstra
2019-09-09 13:40 ` Liang, Kan
2019-08-28 19:35 ` Liang, Kan
2019-08-28 15:19 ` Peter Zijlstra
2019-08-28 16:11 ` [PATCH] x86/math64: Provide a sane mul_u64_u32_div() implementation for x86_64 Peter Zijlstra
2019-08-29 9:30 ` Peter Zijlstra
2019-08-28 16:17 ` [RESEND PATCH V3 3/8] perf/x86/intel: Support hardware TopDown metrics Andi Kleen
2019-08-28 16:28 ` Peter Zijlstra
2019-08-29 3:11 ` Andi Kleen
2019-08-29 9:17 ` Peter Zijlstra
2019-08-29 13:31 ` Liang, Kan
2019-08-29 13:52 ` Peter Zijlstra
2019-08-29 16:56 ` Liang, Kan
2019-08-31 9:18 ` Peter Zijlstra
2019-08-30 23:18 ` Stephane Eranian
2019-08-31 0:31 ` Andi Kleen
2019-08-31 9:13 ` Stephane Eranian
2019-08-31 9:29 ` Peter Zijlstra
2019-08-31 17:53 ` Andi Kleen
2019-08-26 14:47 ` [RESEND PATCH V3 4/8] perf/x86/intel: Support per thread RDPMC " kan.liang
2019-08-26 14:47 ` [RESEND PATCH V3 5/8] perf/x86/intel: Export TopDown events for Icelake kan.liang
2019-08-26 14:47 ` [RESEND PATCH V3 6/8] perf/x86/intel: Disable sampling read slots and topdown kan.liang
2019-08-26 14:47 ` [RESEND PATCH V3 7/8] perf, tools, stat: Support new per thread TopDown metrics kan.liang
2019-08-26 14:47 ` [RESEND PATCH V3 8/8] perf, tools: Add documentation for topdown metrics kan.liang
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