From: Peter Zijlstra <peterz@infradead.org>
To: "Liang, Kan" <kan.liang@linux.intel.com>
Cc: acme@kernel.org, mingo@redhat.com, linux-kernel@vger.kernel.org,
tglx@linutronix.de, jolsa@kernel.org, eranian@google.com,
alexander.shishkin@linux.intel.com, ak@linux.intel.com
Subject: Re: [RESEND PATCH V3 3/8] perf/x86/intel: Support hardware TopDown metrics
Date: Sat, 31 Aug 2019 11:18:02 +0200 [thread overview]
Message-ID: <20190831091802.GI2369@hirez.programming.kicks-ass.net> (raw)
In-Reply-To: <cc2ee16d-b10f-a31e-7411-320e90413ceb@linux.intel.com>
On Thu, Aug 29, 2019 at 12:56:02PM -0400, Liang, Kan wrote:
> On 8/29/2019 9:52 AM, Peter Zijlstra wrote:
> > What what? The PERF_METRICS contents depends on the FIXCTR3 value ?!
>
> Yes.
>
> For current implementation, PERF_METRIC MSR is composed by four fields,
> backend bound, frontend bound, bad speculation and retiring.
> Each of the fields are populated using the below formula for eg:
> PERF_METRIC[RETIRING] = (0xFF *
> PERF_METRICS_RETIRING_INTERNAL_48bit_COUNTER)
> / FIXCTR3
So it really depends on the actual exposed FIXCTR3 _value_ to compute
the PERF_METRIC field? *mind boggles*, that's really unspeakable crap.
And this isn't documented anywhere afaict.
I was thinking they've have an internal counter for the SLOTS value too,
so the PERF_METRIC fields are indenpendent; which would be like 'sane'.
Exposing the internal counters would've been _soooo_ much better, just
add 4 more fixed counters and call it a day.
> The METRICS_OVF indicates the overflow of any internal counters.
OK, but I'm thinking that by that time the fraction in PERF_METRIC will
be too coarse and we're loosing precision. Reconstruction will be
inaccurate.
> The internal counters only start counting from 0, which cannot be programmed
> by SW. But resetting the PERF_METRIC would implicitly resetting the internal
> counters.
The only possible option given the choices.
next prev parent reply other threads:[~2019-08-31 9:18 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-08-26 14:47 [RESEND PATCH V3 0/8] TopDown metrics support for Icelake kan.liang
2019-08-26 14:47 ` [RESEND PATCH V3 1/8] perf/x86/intel: Set correct mask for TOPDOWN.SLOTS kan.liang
2019-08-28 7:48 ` Peter Zijlstra
2019-08-26 14:47 ` [RESEND PATCH V3 2/8] perf/x86/intel: Basic support for metrics counters kan.liang
2019-08-28 7:48 ` Peter Zijlstra
2019-08-28 7:52 ` Peter Zijlstra
2019-08-28 13:59 ` Liang, Kan
2019-08-28 8:44 ` Peter Zijlstra
2019-08-28 9:02 ` Peter Zijlstra
2019-08-28 9:37 ` Peter Zijlstra
2019-08-28 13:51 ` Liang, Kan
2019-08-28 8:52 ` Peter Zijlstra
2019-08-26 14:47 ` [RESEND PATCH V3 3/8] perf/x86/intel: Support hardware TopDown metrics kan.liang
2019-08-28 15:02 ` Peter Zijlstra
2019-08-28 19:04 ` Andi Kleen
2019-08-31 9:19 ` Peter Zijlstra
2019-09-09 13:40 ` Liang, Kan
2019-08-28 19:35 ` Liang, Kan
2019-08-28 15:19 ` Peter Zijlstra
2019-08-28 16:11 ` [PATCH] x86/math64: Provide a sane mul_u64_u32_div() implementation for x86_64 Peter Zijlstra
2019-08-29 9:30 ` Peter Zijlstra
2019-08-28 16:17 ` [RESEND PATCH V3 3/8] perf/x86/intel: Support hardware TopDown metrics Andi Kleen
2019-08-28 16:28 ` Peter Zijlstra
2019-08-29 3:11 ` Andi Kleen
2019-08-29 9:17 ` Peter Zijlstra
2019-08-29 13:31 ` Liang, Kan
2019-08-29 13:52 ` Peter Zijlstra
2019-08-29 16:56 ` Liang, Kan
2019-08-31 9:18 ` Peter Zijlstra [this message]
2019-08-30 23:18 ` Stephane Eranian
2019-08-31 0:31 ` Andi Kleen
2019-08-31 9:13 ` Stephane Eranian
2019-08-31 9:29 ` Peter Zijlstra
2019-08-31 17:53 ` Andi Kleen
2019-08-26 14:47 ` [RESEND PATCH V3 4/8] perf/x86/intel: Support per thread RDPMC " kan.liang
2019-08-26 14:47 ` [RESEND PATCH V3 5/8] perf/x86/intel: Export TopDown events for Icelake kan.liang
2019-08-26 14:47 ` [RESEND PATCH V3 6/8] perf/x86/intel: Disable sampling read slots and topdown kan.liang
2019-08-26 14:47 ` [RESEND PATCH V3 7/8] perf, tools, stat: Support new per thread TopDown metrics kan.liang
2019-08-26 14:47 ` [RESEND PATCH V3 8/8] perf, tools: Add documentation for topdown metrics kan.liang
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