From: Dmitry Osipenko <digetx@gmail.com>
To: Thierry Reding <thierry.reding@gmail.com>,
Jonathan Hunter <jonathanh@nvidia.com>,
Peter De Schrijver <pdeschrijver@nvidia.com>,
Prashant Gaikwad <pgaikwad@nvidia.com>,
"Rafael J. Wysocki" <rjw@rjwysocki.net>,
Viresh Kumar <viresh.kumar@linaro.org>,
Rob Herring <robh+dt@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Peter Geis <pgwipeout@gmail.com>,
Nicolas Chauvet <kwizart@gmail.com>,
Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: linux-pm@vger.kernel.org, linux-tegra@vger.kernel.org,
devicetree@vger.kernel.org, linux-clk@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH v2 11/17] ARM: dts: tegra20: Add CPU Operating Performance Points
Date: Fri, 25 Oct 2019 01:14:10 +0300 [thread overview]
Message-ID: <20191024221416.14197-12-digetx@gmail.com> (raw)
In-Reply-To: <20191024221416.14197-1-digetx@gmail.com>
Operating Point are specified per HW version. The OPP voltages are kept
in a separate DTSI file because some boards may not define CPU regulator
in their device-tree if voltage scaling isn't necessary, like for example
in a case of tegra20-trimslice which is outlet-powered device.
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
---
.../boot/dts/tegra20-cpu-opp-microvolt.dtsi | 201 ++++++++++++
arch/arm/boot/dts/tegra20-cpu-opp.dtsi | 302 ++++++++++++++++++
2 files changed, 503 insertions(+)
create mode 100644 arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi
create mode 100644 arch/arm/boot/dts/tegra20-cpu-opp.dtsi
diff --git a/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi b/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi
new file mode 100644
index 000000000000..e85ffdbef876
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi
@@ -0,0 +1,201 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+ cpu0_opp_table: cpu_opp_table0 {
+ opp@216000000_750 {
+ opp-microvolt = <750000 750000 1125000>;
+ };
+
+ opp@216000000_800 {
+ opp-microvolt = <800000 800000 1125000>;
+ };
+
+ opp@312000000_750 {
+ opp-microvolt = <750000 750000 1125000>;
+ };
+
+ opp@312000000_800 {
+ opp-microvolt = <800000 800000 1125000>;
+ };
+
+ opp@456000000_750 {
+ opp-microvolt = <750000 750000 1125000>;
+ };
+
+ opp@456000000_800 {
+ opp-microvolt = <800000 800000 1125000>;
+ };
+
+ opp@456000000_800_2_2 {
+ opp-microvolt = <800000 800000 1125000>;
+ };
+
+ opp@456000000_800_3_2 {
+ opp-microvolt = <800000 800000 1125000>;
+ };
+
+ opp@456000000_825 {
+ opp-microvolt = <825000 825000 1125000>;
+ };
+
+ opp@608000000_750 {
+ opp-microvolt = <750000 750000 1125000>;
+ };
+
+ opp@608000000_800 {
+ opp-microvolt = <800000 800000 1125000>;
+ };
+
+ opp@608000000_800_3_2 {
+ opp-microvolt = <800000 800000 1125000>;
+ };
+
+ opp@608000000_825 {
+ opp-microvolt = <825000 825000 1125000>;
+ };
+
+ opp@608000000_850 {
+ opp-microvolt = <850000 850000 1125000>;
+ };
+
+ opp@608000000_900 {
+ opp-microvolt = <900000 900000 1125000>;
+ };
+
+ opp@760000000_775 {
+ opp-microvolt = <775000 775000 1125000>;
+ };
+
+ opp@760000000_800 {
+ opp-microvolt = <800000 800000 1125000>;
+ };
+
+ opp@760000000_850 {
+ opp-microvolt = <850000 850000 1125000>;
+ };
+
+ opp@760000000_875 {
+ opp-microvolt = <875000 875000 1125000>;
+ };
+
+ opp@760000000_875_1_1 {
+ opp-microvolt = <875000 875000 1125000>;
+ };
+
+ opp@760000000_875_0_2 {
+ opp-microvolt = <875000 875000 1125000>;
+ };
+
+ opp@760000000_875_1_2 {
+ opp-microvolt = <875000 875000 1125000>;
+ };
+
+ opp@760000000_900 {
+ opp-microvolt = <900000 900000 1125000>;
+ };
+
+ opp@760000000_975 {
+ opp-microvolt = <975000 975000 1125000>;
+ };
+
+ opp@816000000_800 {
+ opp-microvolt = <800000 800000 1125000>;
+ };
+
+ opp@816000000_850 {
+ opp-microvolt = <850000 850000 1125000>;
+ };
+
+ opp@816000000_875 {
+ opp-microvolt = <875000 875000 1125000>;
+ };
+
+ opp@816000000_950 {
+ opp-microvolt = <950000 950000 1125000>;
+ };
+
+ opp@816000000_1000 {
+ opp-microvolt = <1000000 1000000 1125000>;
+ };
+
+ opp@912000000_850 {
+ opp-microvolt = <850000 850000 1125000>;
+ };
+
+ opp@912000000_900 {
+ opp-microvolt = <900000 900000 1125000>;
+ };
+
+ opp@912000000_925 {
+ opp-microvolt = <925000 925000 1125000>;
+ };
+
+ opp@912000000_950 {
+ opp-microvolt = <950000 950000 1125000>;
+ };
+
+ opp@912000000_950_0_2 {
+ opp-microvolt = <950000 950000 1125000>;
+ };
+
+ opp@912000000_950_2_2 {
+ opp-microvolt = <950000 950000 1125000>;
+ };
+
+ opp@912000000_1000 {
+ opp-microvolt = <1000000 1000000 1125000>;
+ };
+
+ opp@912000000_1050 {
+ opp-microvolt = <1050000 1050000 1125000>;
+ };
+
+ opp@1000000000_875 {
+ opp-microvolt = <875000 875000 1125000>;
+ };
+
+ opp@1000000000_900 {
+ opp-microvolt = <900000 900000 1125000>;
+ };
+
+ opp@1000000000_950 {
+ opp-microvolt = <950000 950000 1125000>;
+ };
+
+ opp@1000000000_975 {
+ opp-microvolt = <975000 975000 1125000>;
+ };
+
+ opp@1000000000_1000 {
+ opp-microvolt = <1000000 1000000 1125000>;
+ };
+
+ opp@1000000000_1000_0_2 {
+ opp-microvolt = <1000000 1000000 1125000>;
+ };
+
+ opp@1000000000_1025 {
+ opp-microvolt = <1025000 1025000 1125000>;
+ };
+
+ opp@1000000000_1100 {
+ opp-microvolt = <1100000 1100000 1125000>;
+ };
+
+ opp@1200000000_1000 {
+ opp-microvolt = <1000000 1000000 1125000>;
+ };
+
+ opp@1200000000_1050 {
+ opp-microvolt = <1050000 1050000 1125000>;
+ };
+
+ opp@1200000000_1100 {
+ opp-microvolt = <1100000 1100000 1125000>;
+ };
+
+ opp@1200000000_1125 {
+ opp-microvolt = <1125000 1125000 1125000>;
+ };
+ };
+};
diff --git a/arch/arm/boot/dts/tegra20-cpu-opp.dtsi b/arch/arm/boot/dts/tegra20-cpu-opp.dtsi
new file mode 100644
index 000000000000..c878f4231791
--- /dev/null
+++ b/arch/arm/boot/dts/tegra20-cpu-opp.dtsi
@@ -0,0 +1,302 @@
+// SPDX-License-Identifier: GPL-2.0
+
+/ {
+ cpu0_opp_table: cpu_opp_table0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp@216000000_750 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x0F 0x0003>;
+ opp-hz = /bits/ 64 <216000000>;
+ };
+
+ opp@216000000_800 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x0F 0x0004>;
+ opp-hz = /bits/ 64 <216000000>;
+ };
+
+ opp@312000000_750 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x0F 0x0003>;
+ opp-hz = /bits/ 64 <312000000>;
+ };
+
+ opp@312000000_800 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x0F 0x0004>;
+ opp-hz = /bits/ 64 <312000000>;
+ };
+
+ opp@456000000_750 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x0C 0x0003>;
+ opp-hz = /bits/ 64 <456000000>;
+ };
+
+ opp@456000000_800 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x03 0x0006>;
+ opp-hz = /bits/ 64 <456000000>;
+ };
+
+ opp@456000000_800_2_2 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x04 0x0004>;
+ opp-hz = /bits/ 64 <456000000>;
+ };
+
+ opp@456000000_800_3_2 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x08 0x0004>;
+ opp-hz = /bits/ 64 <456000000>;
+ };
+
+ opp@456000000_825 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x03 0x0001>;
+ opp-hz = /bits/ 64 <456000000>;
+ };
+
+ opp@608000000_750 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x08 0x0003>;
+ opp-hz = /bits/ 64 <608000000>;
+ };
+
+ opp@608000000_800 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x04 0x0006>;
+ opp-hz = /bits/ 64 <608000000>;
+ };
+
+ opp@608000000_800_3_2 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x08 0x0004>;
+ opp-hz = /bits/ 64 <608000000>;
+ };
+
+ opp@608000000_825 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x04 0x0001>;
+ opp-hz = /bits/ 64 <608000000>;
+ };
+
+ opp@608000000_850 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x03 0x0006>;
+ opp-hz = /bits/ 64 <608000000>;
+ };
+
+ opp@608000000_900 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x03 0x0001>;
+ opp-hz = /bits/ 64 <608000000>;
+ };
+
+ opp@760000000_775 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x08 0x0003>;
+ opp-hz = /bits/ 64 <760000000>;
+ };
+
+ opp@760000000_800 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x08 0x0004>;
+ opp-hz = /bits/ 64 <760000000>;
+ };
+
+ opp@760000000_850 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x04 0x0006>;
+ opp-hz = /bits/ 64 <760000000>;
+ };
+
+ opp@760000000_875 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x04 0x0001>;
+ opp-hz = /bits/ 64 <760000000>;
+ };
+
+ opp@760000000_875_1_1 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x02 0x0002>;
+ opp-hz = /bits/ 64 <760000000>;
+ };
+
+ opp@760000000_875_0_2 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x01 0x0004>;
+ opp-hz = /bits/ 64 <760000000>;
+ };
+
+ opp@760000000_875_1_2 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x02 0x0004>;
+ opp-hz = /bits/ 64 <760000000>;
+ };
+
+ opp@760000000_900 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x01 0x0002>;
+ opp-hz = /bits/ 64 <760000000>;
+ };
+
+ opp@760000000_975 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x03 0x0001>;
+ opp-hz = /bits/ 64 <760000000>;
+ };
+
+ opp@816000000_800 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x08 0x0007>;
+ opp-hz = /bits/ 64 <816000000>;
+ };
+
+ opp@816000000_850 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x04 0x0002>;
+ opp-hz = /bits/ 64 <816000000>;
+ };
+
+ opp@816000000_875 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x04 0x0005>;
+ opp-hz = /bits/ 64 <816000000>;
+ };
+
+ opp@816000000_950 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x03 0x0006>;
+ opp-hz = /bits/ 64 <816000000>;
+ };
+
+ opp@816000000_1000 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x03 0x0001>;
+ opp-hz = /bits/ 64 <816000000>;
+ };
+
+ opp@912000000_850 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x08 0x0007>;
+ opp-hz = /bits/ 64 <912000000>;
+ };
+
+ opp@912000000_900 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x04 0x0002>;
+ opp-hz = /bits/ 64 <912000000>;
+ };
+
+ opp@912000000_925 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x04 0x0001>;
+ opp-hz = /bits/ 64 <912000000>;
+ };
+
+ opp@912000000_950 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x02 0x0006>;
+ opp-hz = /bits/ 64 <912000000>;
+ };
+
+ opp@912000000_950_0_2 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x01 0x0004>;
+ opp-hz = /bits/ 64 <912000000>;
+ };
+
+ opp@912000000_950_2_2 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x04 0x0004>;
+ opp-hz = /bits/ 64 <912000000>;
+ };
+
+ opp@912000000_1000 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x01 0x0002>;
+ opp-hz = /bits/ 64 <912000000>;
+ };
+
+ opp@912000000_1050 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x03 0x0001>;
+ opp-hz = /bits/ 64 <912000000>;
+ };
+
+ opp@1000000000_875 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x08 0x0007>;
+ opp-hz = /bits/ 64 <1000000000>;
+ };
+
+ opp@1000000000_900 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x04 0x0002>;
+ opp-hz = /bits/ 64 <1000000000>;
+ };
+
+ opp@1000000000_950 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x04 0x0004>;
+ opp-hz = /bits/ 64 <1000000000>;
+ };
+
+ opp@1000000000_975 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x04 0x0001>;
+ opp-hz = /bits/ 64 <1000000000>;
+ };
+
+ opp@1000000000_1000 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x02 0x0006>;
+ opp-hz = /bits/ 64 <1000000000>;
+ };
+
+ opp@1000000000_1000_0_2 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x01 0x0004>;
+ opp-hz = /bits/ 64 <1000000000>;
+ };
+
+ opp@1000000000_1025 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x01 0x0002>;
+ opp-hz = /bits/ 64 <1000000000>;
+ };
+
+ opp@1000000000_1100 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x03 0x0001>;
+ opp-hz = /bits/ 64 <1000000000>;
+ };
+
+ opp@1200000000_1000 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x08 0x0004>;
+ opp-hz = /bits/ 64 <1200000000>;
+ };
+
+ opp@1200000000_1050 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x04 0x0004>;
+ opp-hz = /bits/ 64 <1200000000>;
+ };
+
+ opp@1200000000_1100 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x02 0x0004>;
+ opp-hz = /bits/ 64 <1200000000>;
+ };
+
+ opp@1200000000_1125 {
+ clock-latency-ns = <400000>;
+ opp-supported-hw = <0x01 0x0004>;
+ opp-hz = /bits/ 64 <1200000000>;
+ };
+ };
+};
--
2.23.0
next prev parent reply other threads:[~2019-10-24 22:17 UTC|newest]
Thread overview: 29+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-24 22:13 [PATCH v2 00/17] NVIDIA Tegra20 CPUFreq driver major update Dmitry Osipenko
2019-10-24 22:14 ` [PATCH v2 01/17] clk: tegra: Add custom CCLK implementation Dmitry Osipenko
2019-10-24 22:14 ` [PATCH v2 02/17] clk: tegra: pll: Add pre/post rate-change hooks Dmitry Osipenko
2019-10-24 22:14 ` [PATCH v2 03/17] clk: tegra: cclk: Add helpers for handling PLLX rate changes Dmitry Osipenko
2019-10-24 22:14 ` [PATCH v2 04/17] clk: tegra20: Support custom CCLK implementation Dmitry Osipenko
2019-10-24 22:14 ` [PATCH v2 05/17] clk: tegra30: " Dmitry Osipenko
2019-10-24 22:14 ` [PATCH v2 06/17] dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30 Dmitry Osipenko
2019-10-29 21:42 ` Rob Herring
2019-10-30 21:05 ` Dmitry Osipenko
2019-10-24 22:14 ` [PATCH v2 07/17] cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported now) Dmitry Osipenko
2019-10-24 22:14 ` [PATCH v2 08/17] ARM: tegra: Create tegra20-cpufreq platform device on Tegra30 Dmitry Osipenko
2019-10-24 22:14 ` [PATCH v2 09/17] ARM: dts: tegra20: Add CPU clock Dmitry Osipenko
2019-10-24 22:14 ` [PATCH v2 10/17] ARM: dts: tegra30: " Dmitry Osipenko
2019-10-24 22:14 ` Dmitry Osipenko [this message]
2019-10-24 22:14 ` [PATCH v2 12/17] ARM: dts: tegra30: Add CPU Operating Performance Points Dmitry Osipenko
2019-10-24 22:14 ` [PATCH v2 13/17] ARM: dts: tegra20: paz00: Set up voltage regulators for DVFS Dmitry Osipenko
2019-10-24 22:14 ` [PATCH v2 14/17] ARM: dts: tegra20: paz00: Add CPU Operating Performance Points Dmitry Osipenko
2019-10-24 22:14 ` [PATCH v2 15/17] ARM: dts: tegra20: trimslice: " Dmitry Osipenko
2019-10-24 22:14 ` [PATCH v2 16/17] ARM: dts: tegra30: cardhu-a04: Set up voltage regulators for DVFS Dmitry Osipenko
2019-10-24 22:14 ` [PATCH v2 17/17] ARM: dts: tegra30: cardhu-a04: Add CPU Operating Performance Points Dmitry Osipenko
2019-11-13 6:52 ` Jon Hunter
2019-11-13 13:57 ` Dmitry Osipenko
2019-11-15 12:52 ` Jon Hunter
2019-11-15 14:55 ` Dmitry Osipenko
2019-11-15 17:31 ` Jon Hunter
2019-11-15 20:35 ` Dmitry Osipenko
2019-11-18 9:52 ` Jon Hunter
2019-10-29 14:09 ` [PATCH v2 00/17] NVIDIA Tegra20 CPUFreq driver major update Thierry Reding
2019-10-29 14:41 ` Dmitry Osipenko
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