* [PATCH v3 01/36] soc: fsl: qe: remove space-before-tab
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
@ 2019-11-01 12:41 ` Rasmus Villemoes
2019-11-01 12:41 ` [PATCH v3 02/36] soc: fsl: qe: drop volatile qualifier of struct qe_ic::regs Rasmus Villemoes
` (34 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:41 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/soc/fsl/qe/qe.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index 417df7e19281..2a0e6e642776 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -378,8 +378,8 @@ static int qe_sdma_init(void)
}
out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK);
- out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |
- (0x1 << QE_SDMR_CEN_SHIFT)));
+ out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |
+ (0x1 << QE_SDMR_CEN_SHIFT)));
return 0;
}
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 02/36] soc: fsl: qe: drop volatile qualifier of struct qe_ic::regs
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
2019-11-01 12:41 ` [PATCH v3 01/36] soc: fsl: qe: remove space-before-tab Rasmus Villemoes
@ 2019-11-01 12:41 ` Rasmus Villemoes
2019-11-01 12:41 ` [PATCH v3 03/36] soc: fsl: qe: rename qe_(clr/set/clrset)bit* helpers Rasmus Villemoes
` (33 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:41 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes
The actual io accessors (e.g. in_be32) implicitly add a volatile
qualifier to their address argument. Remove volatile from the struct
definition and the qe_ic_(read/write) helpers, in preparation for
switching from the ppc-specific io accessors to generic ones.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/soc/fsl/qe/qe_ic.c | 4 ++--
drivers/soc/fsl/qe/qe_ic.h | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index 9bac546998d3..791adcd121d1 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -171,12 +171,12 @@ static struct qe_ic_info qe_ic_info[] = {
},
};
-static inline u32 qe_ic_read(volatile __be32 __iomem * base, unsigned int reg)
+static inline u32 qe_ic_read(__be32 __iomem *base, unsigned int reg)
{
return in_be32(base + (reg >> 2));
}
-static inline void qe_ic_write(volatile __be32 __iomem * base, unsigned int reg,
+static inline void qe_ic_write(__be32 __iomem *base, unsigned int reg,
u32 value)
{
out_be32(base + (reg >> 2), value);
diff --git a/drivers/soc/fsl/qe/qe_ic.h b/drivers/soc/fsl/qe/qe_ic.h
index 08c695672a03..9420378d9b6b 100644
--- a/drivers/soc/fsl/qe/qe_ic.h
+++ b/drivers/soc/fsl/qe/qe_ic.h
@@ -72,7 +72,7 @@
struct qe_ic {
/* Control registers offset */
- volatile u32 __iomem *regs;
+ u32 __iomem *regs;
/* The remapper for this QEIC */
struct irq_domain *irqhost;
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 03/36] soc: fsl: qe: rename qe_(clr/set/clrset)bit* helpers
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
2019-11-01 12:41 ` [PATCH v3 01/36] soc: fsl: qe: remove space-before-tab Rasmus Villemoes
2019-11-01 12:41 ` [PATCH v3 02/36] soc: fsl: qe: drop volatile qualifier of struct qe_ic::regs Rasmus Villemoes
@ 2019-11-01 12:41 ` Rasmus Villemoes
2019-11-01 12:41 ` [PATCH v3 04/36] soc: fsl: qe: introduce qe_io{read,write}* wrappers Rasmus Villemoes
` (32 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:41 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes, netdev
Make it clear that these operate on big-endian registers (i.e. use the
iowrite*be primitives) before we introduce more uses of them and allow
the QE drivers to be built for platforms other than ppc32.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/net/wan/fsl_ucc_hdlc.c | 4 ++--
drivers/soc/fsl/qe/ucc.c | 10 +++++-----
include/soc/fsl/qe/qe.h | 18 +++++++++---------
3 files changed, 16 insertions(+), 16 deletions(-)
diff --git a/drivers/net/wan/fsl_ucc_hdlc.c b/drivers/net/wan/fsl_ucc_hdlc.c
index ca0f3be2b6bf..ce6af7d5380f 100644
--- a/drivers/net/wan/fsl_ucc_hdlc.c
+++ b/drivers/net/wan/fsl_ucc_hdlc.c
@@ -623,8 +623,8 @@ static int ucc_hdlc_poll(struct napi_struct *napi, int budget)
if (howmany < budget) {
napi_complete_done(napi, howmany);
- qe_setbits32(priv->uccf->p_uccm,
- (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS) << 16);
+ qe_setbits_be32(priv->uccf->p_uccm,
+ (UCCE_HDLC_RX_EVENTS | UCCE_HDLC_TX_EVENTS) << 16);
}
return howmany;
diff --git a/drivers/soc/fsl/qe/ucc.c b/drivers/soc/fsl/qe/ucc.c
index 024d239ac1e1..ae9f2cf560cb 100644
--- a/drivers/soc/fsl/qe/ucc.c
+++ b/drivers/soc/fsl/qe/ucc.c
@@ -540,8 +540,8 @@ int ucc_set_tdm_rxtx_clk(u32 tdm_num, enum qe_clock clock,
cmxs1cr = (tdm_num < 4) ? &qe_mux_reg->cmxsi1cr_l :
&qe_mux_reg->cmxsi1cr_h;
- qe_clrsetbits32(cmxs1cr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
- clock_bits << shift);
+ qe_clrsetbits_be32(cmxs1cr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
+ clock_bits << shift);
return 0;
}
@@ -650,9 +650,9 @@ int ucc_set_tdm_rxtx_sync(u32 tdm_num, enum qe_clock clock,
shift = ucc_get_tdm_sync_shift(mode, tdm_num);
- qe_clrsetbits32(&qe_mux_reg->cmxsi1syr,
- QE_CMXUCR_TX_CLK_SRC_MASK << shift,
- source << shift);
+ qe_clrsetbits_be32(&qe_mux_reg->cmxsi1syr,
+ QE_CMXUCR_TX_CLK_SRC_MASK << shift,
+ source << shift);
return 0;
}
diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h
index c1036d16ed03..a1aa4eb28f0c 100644
--- a/include/soc/fsl/qe/qe.h
+++ b/include/soc/fsl/qe/qe.h
@@ -241,20 +241,20 @@ static inline int qe_alive_during_sleep(void)
#define qe_muram_offset cpm_muram_offset
#define qe_muram_dma cpm_muram_dma
-#define qe_setbits32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr))
-#define qe_clrbits32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
+#define qe_setbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr))
+#define qe_clrbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
-#define qe_setbits16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr))
-#define qe_clrbits16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
+#define qe_setbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr))
+#define qe_clrbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
-#define qe_setbits8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr))
-#define qe_clrbits8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
+#define qe_setbits_8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr))
+#define qe_clrbits_8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
-#define qe_clrsetbits32(addr, clear, set) \
+#define qe_clrsetbits_be32(addr, clear, set) \
iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))
-#define qe_clrsetbits16(addr, clear, set) \
+#define qe_clrsetbits_be16(addr, clear, set) \
iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))
-#define qe_clrsetbits8(addr, clear, set) \
+#define qe_clrsetbits_8(addr, clear, set) \
iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))
/* Structure that defines QE firmware binary files.
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 04/36] soc: fsl: qe: introduce qe_io{read,write}* wrappers
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (2 preceding siblings ...)
2019-11-01 12:41 ` [PATCH v3 03/36] soc: fsl: qe: rename qe_(clr/set/clrset)bit* helpers Rasmus Villemoes
@ 2019-11-01 12:41 ` Rasmus Villemoes
2019-11-01 12:41 ` [PATCH v3 05/36] soc: fsl: qe: avoid ppc-specific io accessors Rasmus Villemoes
` (31 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:41 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes
The QUICC engine drivers use the powerpc-specific out_be32() etc. In
order to allow those drivers to build for other architectures, those
must be replaced by iowrite32be(). However, on powerpc, out_be32() is
a simple inline function while iowrite32be() is out-of-line. So in
order not to introduce a performance regression on powerpc when making
the drivers work on other architectures, introduce qe_io* helpers.
Also define the qe_{clr,set,clrset}bits* helpers in terms of these new
macros.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
include/soc/fsl/qe/qe.h | 34 +++++++++++++++++++++++++---------
1 file changed, 25 insertions(+), 9 deletions(-)
diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h
index a1aa4eb28f0c..9cac04c692fd 100644
--- a/include/soc/fsl/qe/qe.h
+++ b/include/soc/fsl/qe/qe.h
@@ -241,21 +241,37 @@ static inline int qe_alive_during_sleep(void)
#define qe_muram_offset cpm_muram_offset
#define qe_muram_dma cpm_muram_dma
-#define qe_setbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) | (_v), (_addr))
-#define qe_clrbits_be32(_addr, _v) iowrite32be(ioread32be(_addr) & ~(_v), (_addr))
+#ifdef CONFIG_PPC32
+#define qe_iowrite8(val, addr) out_8(addr, val)
+#define qe_iowrite16be(val, addr) out_be16(addr, val)
+#define qe_iowrite32be(val, addr) out_be32(addr, val)
+#define qe_ioread8(addr) in_8(addr)
+#define qe_ioread16be(addr) in_be16(addr)
+#define qe_ioread32be(addr) in_be32(addr)
+#else
+#define qe_iowrite8(val, addr) iowrite8(val, addr)
+#define qe_iowrite16be(val, addr) iowrite16be(val, addr)
+#define qe_iowrite32be(val, addr) iowrite32be(val, addr)
+#define qe_ioread8(addr) ioread8(addr)
+#define qe_ioread16be(addr) ioread16be(addr)
+#define qe_ioread32be(addr) ioread32be(addr)
+#endif
+
+#define qe_setbits_be32(_addr, _v) qe_iowrite32be(qe_ioread32be(_addr) | (_v), (_addr))
+#define qe_clrbits_be32(_addr, _v) qe_iowrite32be(qe_ioread32be(_addr) & ~(_v), (_addr))
-#define qe_setbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) | (_v), (_addr))
-#define qe_clrbits_be16(_addr, _v) iowrite16be(ioread16be(_addr) & ~(_v), (_addr))
+#define qe_setbits_be16(_addr, _v) qe_iowrite16be(qe_ioread16be(_addr) | (_v), (_addr))
+#define qe_clrbits_be16(_addr, _v) qe_iowrite16be(qe_ioread16be(_addr) & ~(_v), (_addr))
-#define qe_setbits_8(_addr, _v) iowrite8(ioread8(_addr) | (_v), (_addr))
-#define qe_clrbits_8(_addr, _v) iowrite8(ioread8(_addr) & ~(_v), (_addr))
+#define qe_setbits_8(_addr, _v) qe_iowrite8(qe_ioread8(_addr) | (_v), (_addr))
+#define qe_clrbits_8(_addr, _v) qe_iowrite8(qe_ioread8(_addr) & ~(_v), (_addr))
#define qe_clrsetbits_be32(addr, clear, set) \
- iowrite32be((ioread32be(addr) & ~(clear)) | (set), (addr))
+ qe_iowrite32be((qe_ioread32be(addr) & ~(clear)) | (set), (addr))
#define qe_clrsetbits_be16(addr, clear, set) \
- iowrite16be((ioread16be(addr) & ~(clear)) | (set), (addr))
+ qe_iowrite16be((qe_ioread16be(addr) & ~(clear)) | (set), (addr))
#define qe_clrsetbits_8(addr, clear, set) \
- iowrite8((ioread8(addr) & ~(clear)) | (set), (addr))
+ qe_iowrite8((qe_ioread8(addr) & ~(clear)) | (set), (addr))
/* Structure that defines QE firmware binary files.
*
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 05/36] soc: fsl: qe: avoid ppc-specific io accessors
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (3 preceding siblings ...)
2019-11-01 12:41 ` [PATCH v3 04/36] soc: fsl: qe: introduce qe_io{read,write}* wrappers Rasmus Villemoes
@ 2019-11-01 12:41 ` Rasmus Villemoes
2019-11-01 12:41 ` [PATCH v3 06/36] soc: fsl: qe: replace spin_event_timeout by readx_poll_timeout_atomic Rasmus Villemoes
` (30 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:41 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes
In preparation for allowing to build QE support for architectures
other than PPC, replace the ppc-specific io accessors by the qe_io*
macros. Done via
$ spatch --sp-file io.cocci --in-place drivers/soc/fsl/qe/
where io.cocci is
@@
expression addr, val;
@@
- out_be32(addr, val)
+ qe_iowrite32be(val, addr)
@@
expression addr;
@@
- in_be32(addr)
+ qe_ioread32be(addr)
@@
expression addr, val;
@@
- out_be16(addr, val)
+ qe_iowrite16be(val, addr)
@@
expression addr;
@@
- in_be16(addr)
+ qe_ioread16be(addr)
@@
expression addr, val;
@@
- out_8(addr, val)
+ qe_iowrite8(val, addr)
@@
expression addr;
@@
- in_8(addr)
+ qe_ioread8(addr)
@@
expression addr, clr, set;
@@
- clrsetbits_be32(addr, clr, set)
+ qe_clrsetbits_be32(addr, clr, set)
@@
expression addr, clr, set;
@@
- clrsetbits_be16(addr, clr, set)
+ qe_clrsetbits_be16(addr, clr, set)
@@
expression addr, clr, set;
@@
- clrsetbits_8(addr, clr, set)
+ qe_clrsetbits_8(addr, clr, set)
@@
expression addr, set;
@@
- setbits32(addr, set)
+ qe_setbits_be32(addr, set)
@@
expression addr, set;
@@
- setbits16(addr, set)
+ qe_setbits_be16(addr, set)
@@
expression addr, set;
@@
- setbits8(addr, set)
+ qe_setbits_8(addr, set)
@@
expression addr, clr;
@@
- clrbits32(addr, clr)
+ qe_clrbits_be32(addr, clr)
@@
expression addr, clr;
@@
- clrbits16(addr, clr)
+ qe_clrbits_be16(addr, clr)
@@
expression addr, clr;
@@
- clrbits8(addr, clr)
+ qe_clrbits_8(addr, clr)
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/soc/fsl/qe/gpio.c | 34 +++++++++--------
drivers/soc/fsl/qe/qe.c | 38 ++++++++++---------
drivers/soc/fsl/qe/qe_ic.c | 5 ++-
drivers/soc/fsl/qe/qe_io.c | 40 +++++++++-----------
drivers/soc/fsl/qe/qe_tdm.c | 8 ++--
drivers/soc/fsl/qe/ucc.c | 16 ++++----
drivers/soc/fsl/qe/ucc_fast.c | 71 ++++++++++++++++++-----------------
drivers/soc/fsl/qe/ucc_slow.c | 38 +++++++++----------
drivers/soc/fsl/qe/usb.c | 2 +-
9 files changed, 129 insertions(+), 123 deletions(-)
diff --git a/drivers/soc/fsl/qe/gpio.c b/drivers/soc/fsl/qe/gpio.c
index f0c29ed8f0ff..12bdfd9cbe7c 100644
--- a/drivers/soc/fsl/qe/gpio.c
+++ b/drivers/soc/fsl/qe/gpio.c
@@ -41,13 +41,13 @@ static void qe_gpio_save_regs(struct of_mm_gpio_chip *mm_gc)
container_of(mm_gc, struct qe_gpio_chip, mm_gc);
struct qe_pio_regs __iomem *regs = mm_gc->regs;
- qe_gc->cpdata = in_be32(®s->cpdata);
+ qe_gc->cpdata = qe_ioread32be(®s->cpdata);
qe_gc->saved_regs.cpdata = qe_gc->cpdata;
- qe_gc->saved_regs.cpdir1 = in_be32(®s->cpdir1);
- qe_gc->saved_regs.cpdir2 = in_be32(®s->cpdir2);
- qe_gc->saved_regs.cppar1 = in_be32(®s->cppar1);
- qe_gc->saved_regs.cppar2 = in_be32(®s->cppar2);
- qe_gc->saved_regs.cpodr = in_be32(®s->cpodr);
+ qe_gc->saved_regs.cpdir1 = qe_ioread32be(®s->cpdir1);
+ qe_gc->saved_regs.cpdir2 = qe_ioread32be(®s->cpdir2);
+ qe_gc->saved_regs.cppar1 = qe_ioread32be(®s->cppar1);
+ qe_gc->saved_regs.cppar2 = qe_ioread32be(®s->cppar2);
+ qe_gc->saved_regs.cpodr = qe_ioread32be(®s->cpodr);
}
static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
@@ -56,7 +56,7 @@ static int qe_gpio_get(struct gpio_chip *gc, unsigned int gpio)
struct qe_pio_regs __iomem *regs = mm_gc->regs;
u32 pin_mask = 1 << (QE_PIO_PINS - 1 - gpio);
- return !!(in_be32(®s->cpdata) & pin_mask);
+ return !!(qe_ioread32be(®s->cpdata) & pin_mask);
}
static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
@@ -74,7 +74,7 @@ static void qe_gpio_set(struct gpio_chip *gc, unsigned int gpio, int val)
else
qe_gc->cpdata &= ~pin_mask;
- out_be32(®s->cpdata, qe_gc->cpdata);
+ qe_iowrite32be(qe_gc->cpdata, ®s->cpdata);
spin_unlock_irqrestore(&qe_gc->lock, flags);
}
@@ -101,7 +101,7 @@ static void qe_gpio_set_multiple(struct gpio_chip *gc,
}
}
- out_be32(®s->cpdata, qe_gc->cpdata);
+ qe_iowrite32be(qe_gc->cpdata, ®s->cpdata);
spin_unlock_irqrestore(&qe_gc->lock, flags);
}
@@ -255,11 +255,15 @@ void qe_pin_set_dedicated(struct qe_pin *qe_pin)
spin_lock_irqsave(&qe_gc->lock, flags);
if (second_reg) {
- clrsetbits_be32(®s->cpdir2, mask2, sregs->cpdir2 & mask2);
- clrsetbits_be32(®s->cppar2, mask2, sregs->cppar2 & mask2);
+ qe_clrsetbits_be32(®s->cpdir2, mask2,
+ sregs->cpdir2 & mask2);
+ qe_clrsetbits_be32(®s->cppar2, mask2,
+ sregs->cppar2 & mask2);
} else {
- clrsetbits_be32(®s->cpdir1, mask2, sregs->cpdir1 & mask2);
- clrsetbits_be32(®s->cppar1, mask2, sregs->cppar1 & mask2);
+ qe_clrsetbits_be32(®s->cpdir1, mask2,
+ sregs->cpdir1 & mask2);
+ qe_clrsetbits_be32(®s->cppar1, mask2,
+ sregs->cppar1 & mask2);
}
if (sregs->cpdata & mask1)
@@ -267,8 +271,8 @@ void qe_pin_set_dedicated(struct qe_pin *qe_pin)
else
qe_gc->cpdata &= ~mask1;
- out_be32(®s->cpdata, qe_gc->cpdata);
- clrsetbits_be32(®s->cpodr, mask1, sregs->cpodr & mask1);
+ qe_iowrite32be(qe_gc->cpdata, ®s->cpdata);
+ qe_clrsetbits_be32(®s->cpodr, mask1, sregs->cpodr & mask1);
spin_unlock_irqrestore(&qe_gc->lock, flags);
}
diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index 2a0e6e642776..456bd7416876 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -112,7 +112,7 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
spin_lock_irqsave(&qe_lock, flags);
if (cmd == QE_RESET) {
- out_be32(&qe_immr->cp.cecr, (u32) (cmd | QE_CR_FLG));
+ qe_iowrite32be((u32)(cmd | QE_CR_FLG), &qe_immr->cp.cecr);
} else {
if (cmd == QE_ASSIGN_PAGE) {
/* Here device is the SNUM, not sub-block */
@@ -129,15 +129,14 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
mcn_shift = QE_CR_MCN_NORMAL_SHIFT;
}
- out_be32(&qe_immr->cp.cecdr, cmd_input);
- out_be32(&qe_immr->cp.cecr,
- (cmd | QE_CR_FLG | ((u32) device << dev_shift) | (u32)
- mcn_protocol << mcn_shift));
+ qe_iowrite32be(cmd_input, &qe_immr->cp.cecdr);
+ qe_iowrite32be((cmd | QE_CR_FLG | ((u32)device << dev_shift) | (u32)mcn_protocol << mcn_shift),
+ &qe_immr->cp.cecr);
}
/* wait for the QE_CR_FLG to clear */
- ret = spin_event_timeout((in_be32(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,
- 100, 0);
+ ret = spin_event_timeout((qe_ioread32be(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,
+ 100, 0);
/* On timeout (e.g. failure), the expression will be false (ret == 0),
otherwise it will be true (ret == 1). */
spin_unlock_irqrestore(&qe_lock, flags);
@@ -230,7 +229,7 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
tempval = ((divisor - 1) << QE_BRGC_DIVISOR_SHIFT) |
QE_BRGC_ENABLE | div16;
- out_be32(&qe_immr->brg.brgc[brg - QE_BRG1], tempval);
+ qe_iowrite32be(tempval, &qe_immr->brg.brgc[brg - QE_BRG1]);
return 0;
}
@@ -377,9 +376,10 @@ static int qe_sdma_init(void)
return -ENOMEM;
}
- out_be32(&sdma->sdebcr, (u32) sdma_buf_offset & QE_SDEBCR_BA_MASK);
- out_be32(&sdma->sdmr, (QE_SDMR_GLB_1_MSK |
- (0x1 << QE_SDMR_CEN_SHIFT)));
+ qe_iowrite32be((u32)sdma_buf_offset & QE_SDEBCR_BA_MASK,
+ &sdma->sdebcr);
+ qe_iowrite32be((QE_SDMR_GLB_1_MSK | (0x1 << QE_SDMR_CEN_SHIFT)),
+ &sdma->sdmr);
return 0;
}
@@ -417,14 +417,14 @@ static void qe_upload_microcode(const void *base,
"uploading microcode '%s'\n", ucode->id);
/* Use auto-increment */
- out_be32(&qe_immr->iram.iadd, be32_to_cpu(ucode->iram_offset) |
- QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR);
+ qe_iowrite32be(be32_to_cpu(ucode->iram_offset) | QE_IRAM_IADD_AIE | QE_IRAM_IADD_BADDR,
+ &qe_immr->iram.iadd);
for (i = 0; i < be32_to_cpu(ucode->count); i++)
- out_be32(&qe_immr->iram.idata, be32_to_cpu(code[i]));
+ qe_iowrite32be(be32_to_cpu(code[i]), &qe_immr->iram.idata);
/* Set I-RAM Ready Register */
- out_be32(&qe_immr->iram.iready, be32_to_cpu(QE_IRAM_READY));
+ qe_iowrite32be(be32_to_cpu(QE_IRAM_READY), &qe_immr->iram.iready);
}
/*
@@ -509,7 +509,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
* If the microcode calls for it, split the I-RAM.
*/
if (!firmware->split)
- setbits16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);
+ qe_setbits_be16(&qe_immr->cp.cercr, QE_CP_CERCR_CIR);
if (firmware->soc.model)
printk(KERN_INFO
@@ -543,11 +543,13 @@ int qe_upload_firmware(const struct qe_firmware *firmware)
u32 trap = be32_to_cpu(ucode->traps[j]);
if (trap)
- out_be32(&qe_immr->rsp[i].tibcr[j], trap);
+ qe_iowrite32be(trap,
+ &qe_immr->rsp[i].tibcr[j]);
}
/* Enable traps */
- out_be32(&qe_immr->rsp[i].eccr, be32_to_cpu(ucode->eccr));
+ qe_iowrite32be(be32_to_cpu(ucode->eccr),
+ &qe_immr->rsp[i].eccr);
}
qe_firmware_uploaded = 1;
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index 791adcd121d1..8c874372416b 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -24,6 +24,7 @@
#include <linux/spinlock.h>
#include <asm/irq.h>
#include <asm/io.h>
+#include <soc/fsl/qe/qe.h>
#include <soc/fsl/qe/qe_ic.h>
#include "qe_ic.h"
@@ -173,13 +174,13 @@ static struct qe_ic_info qe_ic_info[] = {
static inline u32 qe_ic_read(__be32 __iomem *base, unsigned int reg)
{
- return in_be32(base + (reg >> 2));
+ return qe_ioread32be(base + (reg >> 2));
}
static inline void qe_ic_write(__be32 __iomem *base, unsigned int reg,
u32 value)
{
- out_be32(base + (reg >> 2), value);
+ qe_iowrite32be(value, base + (reg >> 2));
}
static inline struct qe_ic *qe_ic_from_irq(unsigned int virq)
diff --git a/drivers/soc/fsl/qe/qe_io.c b/drivers/soc/fsl/qe/qe_io.c
index 3657e296a8a2..5e3471ac09dd 100644
--- a/drivers/soc/fsl/qe/qe_io.c
+++ b/drivers/soc/fsl/qe/qe_io.c
@@ -57,16 +57,16 @@ void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir,
pin_mask1bit = (u32) (1 << (QE_PIO_PINS - (pin + 1)));
/* Set open drain, if required */
- tmp_val = in_be32(&par_io->cpodr);
+ tmp_val = qe_ioread32be(&par_io->cpodr);
if (open_drain)
- out_be32(&par_io->cpodr, pin_mask1bit | tmp_val);
+ qe_iowrite32be(pin_mask1bit | tmp_val, &par_io->cpodr);
else
- out_be32(&par_io->cpodr, ~pin_mask1bit & tmp_val);
+ qe_iowrite32be(~pin_mask1bit & tmp_val, &par_io->cpodr);
/* define direction */
tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
- in_be32(&par_io->cpdir2) :
- in_be32(&par_io->cpdir1);
+ qe_ioread32be(&par_io->cpdir2) :
+ qe_ioread32be(&par_io->cpdir1);
/* get all bits mask for 2 bit per port */
pin_mask2bits = (u32) (0x3 << (QE_PIO_PINS -
@@ -78,34 +78,30 @@ void __par_io_config_pin(struct qe_pio_regs __iomem *par_io, u8 pin, int dir,
/* clear and set 2 bits mask */
if (pin > (QE_PIO_PINS / 2) - 1) {
- out_be32(&par_io->cpdir2,
- ~pin_mask2bits & tmp_val);
+ qe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir2);
tmp_val &= ~pin_mask2bits;
- out_be32(&par_io->cpdir2, new_mask2bits | tmp_val);
+ qe_iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir2);
} else {
- out_be32(&par_io->cpdir1,
- ~pin_mask2bits & tmp_val);
+ qe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cpdir1);
tmp_val &= ~pin_mask2bits;
- out_be32(&par_io->cpdir1, new_mask2bits | tmp_val);
+ qe_iowrite32be(new_mask2bits | tmp_val, &par_io->cpdir1);
}
/* define pin assignment */
tmp_val = (pin > (QE_PIO_PINS / 2) - 1) ?
- in_be32(&par_io->cppar2) :
- in_be32(&par_io->cppar1);
+ qe_ioread32be(&par_io->cppar2) :
+ qe_ioread32be(&par_io->cppar1);
new_mask2bits = (u32) (assignment << (QE_PIO_PINS -
(pin % (QE_PIO_PINS / 2) + 1) * 2));
/* clear and set 2 bits mask */
if (pin > (QE_PIO_PINS / 2) - 1) {
- out_be32(&par_io->cppar2,
- ~pin_mask2bits & tmp_val);
+ qe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar2);
tmp_val &= ~pin_mask2bits;
- out_be32(&par_io->cppar2, new_mask2bits | tmp_val);
+ qe_iowrite32be(new_mask2bits | tmp_val, &par_io->cppar2);
} else {
- out_be32(&par_io->cppar1,
- ~pin_mask2bits & tmp_val);
+ qe_iowrite32be(~pin_mask2bits & tmp_val, &par_io->cppar1);
tmp_val &= ~pin_mask2bits;
- out_be32(&par_io->cppar1, new_mask2bits | tmp_val);
+ qe_iowrite32be(new_mask2bits | tmp_val, &par_io->cppar1);
}
}
EXPORT_SYMBOL(__par_io_config_pin);
@@ -133,12 +129,12 @@ int par_io_data_set(u8 port, u8 pin, u8 val)
/* calculate pin location */
pin_mask = (u32) (1 << (QE_PIO_PINS - 1 - pin));
- tmp_val = in_be32(&par_io[port].cpdata);
+ tmp_val = qe_ioread32be(&par_io[port].cpdata);
if (val == 0) /* clear */
- out_be32(&par_io[port].cpdata, ~pin_mask & tmp_val);
+ qe_iowrite32be(~pin_mask & tmp_val, &par_io[port].cpdata);
else /* set */
- out_be32(&par_io[port].cpdata, pin_mask | tmp_val);
+ qe_iowrite32be(pin_mask | tmp_val, &par_io[port].cpdata);
return 0;
}
diff --git a/drivers/soc/fsl/qe/qe_tdm.c b/drivers/soc/fsl/qe/qe_tdm.c
index e37ebc3be661..7d7d78d3ee50 100644
--- a/drivers/soc/fsl/qe/qe_tdm.c
+++ b/drivers/soc/fsl/qe/qe_tdm.c
@@ -169,10 +169,10 @@ void ucc_tdm_init(struct ucc_tdm *utdm, struct ucc_tdm_info *ut_info)
&siram[siram_entry_id * 32 + 0x200 + i]);
}
- setbits16(&siram[(siram_entry_id * 32) + (utdm->num_of_ts - 1)],
- SIR_LAST);
- setbits16(&siram[(siram_entry_id * 32) + 0x200 + (utdm->num_of_ts - 1)],
- SIR_LAST);
+ qe_setbits_be16(&siram[(siram_entry_id * 32) + (utdm->num_of_ts - 1)],
+ SIR_LAST);
+ qe_setbits_be16(&siram[(siram_entry_id * 32) + 0x200 + (utdm->num_of_ts - 1)],
+ SIR_LAST);
/* Set SIxMR register */
sixmr = SIMR_SAD(siram_entry_id);
diff --git a/drivers/soc/fsl/qe/ucc.c b/drivers/soc/fsl/qe/ucc.c
index ae9f2cf560cb..da3d7e2dd837 100644
--- a/drivers/soc/fsl/qe/ucc.c
+++ b/drivers/soc/fsl/qe/ucc.c
@@ -35,8 +35,8 @@ int ucc_set_qe_mux_mii_mng(unsigned int ucc_num)
return -EINVAL;
spin_lock_irqsave(&cmxgcr_lock, flags);
- clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
- ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
+ qe_clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG,
+ ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT);
spin_unlock_irqrestore(&cmxgcr_lock, flags);
return 0;
@@ -80,8 +80,8 @@ int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed)
return -EINVAL;
}
- clrsetbits_8(guemr, UCC_GUEMR_MODE_MASK,
- UCC_GUEMR_SET_RESERVED3 | speed);
+ qe_clrsetbits_8(guemr, UCC_GUEMR_MODE_MASK,
+ UCC_GUEMR_SET_RESERVED3 | speed);
return 0;
}
@@ -109,9 +109,9 @@ int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask)
get_cmxucr_reg(ucc_num, &cmxucr, ®_num, &shift);
if (set)
- setbits32(cmxucr, mask << shift);
+ qe_setbits_be32(cmxucr, mask << shift);
else
- clrbits32(cmxucr, mask << shift);
+ qe_clrbits_be32(cmxucr, mask << shift);
return 0;
}
@@ -207,8 +207,8 @@ int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock,
if (mode == COMM_DIR_RX)
shift += 4;
- clrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
- clock_bits << shift);
+ qe_clrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift,
+ clock_bits << shift);
return 0;
}
diff --git a/drivers/soc/fsl/qe/ucc_fast.c b/drivers/soc/fsl/qe/ucc_fast.c
index af4d80e38521..ca0452497a20 100644
--- a/drivers/soc/fsl/qe/ucc_fast.c
+++ b/drivers/soc/fsl/qe/ucc_fast.c
@@ -29,41 +29,42 @@ void ucc_fast_dump_regs(struct ucc_fast_private * uccf)
printk(KERN_INFO "Base address: 0x%p\n", uccf->uf_regs);
printk(KERN_INFO "gumr : addr=0x%p, val=0x%08x\n",
- &uccf->uf_regs->gumr, in_be32(&uccf->uf_regs->gumr));
+ &uccf->uf_regs->gumr, qe_ioread32be(&uccf->uf_regs->gumr));
printk(KERN_INFO "upsmr : addr=0x%p, val=0x%08x\n",
- &uccf->uf_regs->upsmr, in_be32(&uccf->uf_regs->upsmr));
+ &uccf->uf_regs->upsmr, qe_ioread32be(&uccf->uf_regs->upsmr));
printk(KERN_INFO "utodr : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->utodr, in_be16(&uccf->uf_regs->utodr));
+ &uccf->uf_regs->utodr, qe_ioread16be(&uccf->uf_regs->utodr));
printk(KERN_INFO "udsr : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->udsr, in_be16(&uccf->uf_regs->udsr));
+ &uccf->uf_regs->udsr, qe_ioread16be(&uccf->uf_regs->udsr));
printk(KERN_INFO "ucce : addr=0x%p, val=0x%08x\n",
- &uccf->uf_regs->ucce, in_be32(&uccf->uf_regs->ucce));
+ &uccf->uf_regs->ucce, qe_ioread32be(&uccf->uf_regs->ucce));
printk(KERN_INFO "uccm : addr=0x%p, val=0x%08x\n",
- &uccf->uf_regs->uccm, in_be32(&uccf->uf_regs->uccm));
+ &uccf->uf_regs->uccm, qe_ioread32be(&uccf->uf_regs->uccm));
printk(KERN_INFO "uccs : addr=0x%p, val=0x%02x\n",
- &uccf->uf_regs->uccs, in_8(&uccf->uf_regs->uccs));
+ &uccf->uf_regs->uccs, qe_ioread8(&uccf->uf_regs->uccs));
printk(KERN_INFO "urfb : addr=0x%p, val=0x%08x\n",
- &uccf->uf_regs->urfb, in_be32(&uccf->uf_regs->urfb));
+ &uccf->uf_regs->urfb, qe_ioread32be(&uccf->uf_regs->urfb));
printk(KERN_INFO "urfs : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->urfs, in_be16(&uccf->uf_regs->urfs));
+ &uccf->uf_regs->urfs, qe_ioread16be(&uccf->uf_regs->urfs));
printk(KERN_INFO "urfet : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->urfet, in_be16(&uccf->uf_regs->urfet));
+ &uccf->uf_regs->urfet, qe_ioread16be(&uccf->uf_regs->urfet));
printk(KERN_INFO "urfset: addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->urfset, in_be16(&uccf->uf_regs->urfset));
+ &uccf->uf_regs->urfset,
+ qe_ioread16be(&uccf->uf_regs->urfset));
printk(KERN_INFO "utfb : addr=0x%p, val=0x%08x\n",
- &uccf->uf_regs->utfb, in_be32(&uccf->uf_regs->utfb));
+ &uccf->uf_regs->utfb, qe_ioread32be(&uccf->uf_regs->utfb));
printk(KERN_INFO "utfs : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->utfs, in_be16(&uccf->uf_regs->utfs));
+ &uccf->uf_regs->utfs, qe_ioread16be(&uccf->uf_regs->utfs));
printk(KERN_INFO "utfet : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->utfet, in_be16(&uccf->uf_regs->utfet));
+ &uccf->uf_regs->utfet, qe_ioread16be(&uccf->uf_regs->utfet));
printk(KERN_INFO "utftt : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->utftt, in_be16(&uccf->uf_regs->utftt));
+ &uccf->uf_regs->utftt, qe_ioread16be(&uccf->uf_regs->utftt));
printk(KERN_INFO "utpt : addr=0x%p, val=0x%04x\n",
- &uccf->uf_regs->utpt, in_be16(&uccf->uf_regs->utpt));
+ &uccf->uf_regs->utpt, qe_ioread16be(&uccf->uf_regs->utpt));
printk(KERN_INFO "urtry : addr=0x%p, val=0x%08x\n",
- &uccf->uf_regs->urtry, in_be32(&uccf->uf_regs->urtry));
+ &uccf->uf_regs->urtry, qe_ioread32be(&uccf->uf_regs->urtry));
printk(KERN_INFO "guemr : addr=0x%p, val=0x%02x\n",
- &uccf->uf_regs->guemr, in_8(&uccf->uf_regs->guemr));
+ &uccf->uf_regs->guemr, qe_ioread8(&uccf->uf_regs->guemr));
}
EXPORT_SYMBOL(ucc_fast_dump_regs);
@@ -85,7 +86,7 @@ EXPORT_SYMBOL(ucc_fast_get_qe_cr_subblock);
void ucc_fast_transmit_on_demand(struct ucc_fast_private * uccf)
{
- out_be16(&uccf->uf_regs->utodr, UCC_FAST_TOD);
+ qe_iowrite16be(UCC_FAST_TOD, &uccf->uf_regs->utodr);
}
EXPORT_SYMBOL(ucc_fast_transmit_on_demand);
@@ -97,7 +98,7 @@ void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode)
uf_regs = uccf->uf_regs;
/* Enable reception and/or transmission on this UCC. */
- gumr = in_be32(&uf_regs->gumr);
+ gumr = qe_ioread32be(&uf_regs->gumr);
if (mode & COMM_DIR_TX) {
gumr |= UCC_FAST_GUMR_ENT;
uccf->enabled_tx = 1;
@@ -106,7 +107,7 @@ void ucc_fast_enable(struct ucc_fast_private * uccf, enum comm_dir mode)
gumr |= UCC_FAST_GUMR_ENR;
uccf->enabled_rx = 1;
}
- out_be32(&uf_regs->gumr, gumr);
+ qe_iowrite32be(gumr, &uf_regs->gumr);
}
EXPORT_SYMBOL(ucc_fast_enable);
@@ -118,7 +119,7 @@ void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode)
uf_regs = uccf->uf_regs;
/* Disable reception and/or transmission on this UCC. */
- gumr = in_be32(&uf_regs->gumr);
+ gumr = qe_ioread32be(&uf_regs->gumr);
if (mode & COMM_DIR_TX) {
gumr &= ~UCC_FAST_GUMR_ENT;
uccf->enabled_tx = 0;
@@ -127,7 +128,7 @@ void ucc_fast_disable(struct ucc_fast_private * uccf, enum comm_dir mode)
gumr &= ~UCC_FAST_GUMR_ENR;
uccf->enabled_rx = 0;
}
- out_be32(&uf_regs->gumr, gumr);
+ qe_iowrite32be(gumr, &uf_regs->gumr);
}
EXPORT_SYMBOL(ucc_fast_disable);
@@ -259,7 +260,7 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
gumr |= uf_info->tenc;
gumr |= uf_info->tcrc;
gumr |= uf_info->mode;
- out_be32(&uf_regs->gumr, gumr);
+ qe_iowrite32be(gumr, &uf_regs->gumr);
/* Allocate memory for Tx Virtual Fifo */
uccf->ucc_fast_tx_virtual_fifo_base_offset =
@@ -286,15 +287,17 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
}
/* Set Virtual Fifo registers */
- out_be16(&uf_regs->urfs, uf_info->urfs);
- out_be16(&uf_regs->urfet, uf_info->urfet);
- out_be16(&uf_regs->urfset, uf_info->urfset);
- out_be16(&uf_regs->utfs, uf_info->utfs);
- out_be16(&uf_regs->utfet, uf_info->utfet);
- out_be16(&uf_regs->utftt, uf_info->utftt);
+ qe_iowrite16be(uf_info->urfs, &uf_regs->urfs);
+ qe_iowrite16be(uf_info->urfet, &uf_regs->urfet);
+ qe_iowrite16be(uf_info->urfset, &uf_regs->urfset);
+ qe_iowrite16be(uf_info->utfs, &uf_regs->utfs);
+ qe_iowrite16be(uf_info->utfet, &uf_regs->utfet);
+ qe_iowrite16be(uf_info->utftt, &uf_regs->utftt);
/* utfb, urfb are offsets from MURAM base */
- out_be32(&uf_regs->utfb, uccf->ucc_fast_tx_virtual_fifo_base_offset);
- out_be32(&uf_regs->urfb, uccf->ucc_fast_rx_virtual_fifo_base_offset);
+ qe_iowrite32be(uccf->ucc_fast_tx_virtual_fifo_base_offset,
+ &uf_regs->utfb);
+ qe_iowrite32be(uccf->ucc_fast_rx_virtual_fifo_base_offset,
+ &uf_regs->urfb);
/* Mux clocking */
/* Grant Support */
@@ -362,14 +365,14 @@ int ucc_fast_init(struct ucc_fast_info * uf_info, struct ucc_fast_private ** ucc
}
/* Set interrupt mask register at UCC level. */
- out_be32(&uf_regs->uccm, uf_info->uccm_mask);
+ qe_iowrite32be(uf_info->uccm_mask, &uf_regs->uccm);
/* First, clear anything pending at UCC level,
* otherwise, old garbage may come through
* as soon as the dam is opened. */
/* Writing '1' clears */
- out_be32(&uf_regs->ucce, 0xffffffff);
+ qe_iowrite32be(0xffffffff, &uf_regs->ucce);
*uccf_ret = uccf;
return 0;
diff --git a/drivers/soc/fsl/qe/ucc_slow.c b/drivers/soc/fsl/qe/ucc_slow.c
index 34f0ec3a63b5..9b55fd0f50c6 100644
--- a/drivers/soc/fsl/qe/ucc_slow.c
+++ b/drivers/soc/fsl/qe/ucc_slow.c
@@ -78,7 +78,7 @@ void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)
us_regs = uccs->us_regs;
/* Enable reception and/or transmission on this UCC. */
- gumr_l = in_be32(&us_regs->gumr_l);
+ gumr_l = qe_ioread32be(&us_regs->gumr_l);
if (mode & COMM_DIR_TX) {
gumr_l |= UCC_SLOW_GUMR_L_ENT;
uccs->enabled_tx = 1;
@@ -87,7 +87,7 @@ void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)
gumr_l |= UCC_SLOW_GUMR_L_ENR;
uccs->enabled_rx = 1;
}
- out_be32(&us_regs->gumr_l, gumr_l);
+ qe_iowrite32be(gumr_l, &us_regs->gumr_l);
}
EXPORT_SYMBOL(ucc_slow_enable);
@@ -99,7 +99,7 @@ void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
us_regs = uccs->us_regs;
/* Disable reception and/or transmission on this UCC. */
- gumr_l = in_be32(&us_regs->gumr_l);
+ gumr_l = qe_ioread32be(&us_regs->gumr_l);
if (mode & COMM_DIR_TX) {
gumr_l &= ~UCC_SLOW_GUMR_L_ENT;
uccs->enabled_tx = 0;
@@ -108,7 +108,7 @@ void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
gumr_l &= ~UCC_SLOW_GUMR_L_ENR;
uccs->enabled_rx = 0;
}
- out_be32(&us_regs->gumr_l, gumr_l);
+ qe_iowrite32be(gumr_l, &us_regs->gumr_l);
}
EXPORT_SYMBOL(ucc_slow_disable);
@@ -198,7 +198,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
return ret;
}
- out_be16(&uccs->us_pram->mrblr, us_info->max_rx_buf_length);
+ qe_iowrite16be(us_info->max_rx_buf_length, &uccs->us_pram->mrblr);
INIT_LIST_HEAD(&uccs->confQ);
@@ -228,27 +228,27 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
bd = uccs->confBd = uccs->tx_bd = qe_muram_addr(uccs->tx_base_offset);
for (i = 0; i < us_info->tx_bd_ring_len - 1; i++) {
/* clear bd buffer */
- out_be32(&bd->buf, 0);
+ qe_iowrite32be(0, &bd->buf);
/* set bd status and length */
- out_be32((u32 *) bd, 0);
+ qe_iowrite32be(0, (u32 *)bd);
bd++;
}
/* for last BD set Wrap bit */
- out_be32(&bd->buf, 0);
- out_be32((u32 *) bd, cpu_to_be32(T_W));
+ qe_iowrite32be(0, &bd->buf);
+ qe_iowrite32be(cpu_to_be32(T_W), (u32 *)bd);
/* Init Rx bds */
bd = uccs->rx_bd = qe_muram_addr(uccs->rx_base_offset);
for (i = 0; i < us_info->rx_bd_ring_len - 1; i++) {
/* set bd status and length */
- out_be32((u32*)bd, 0);
+ qe_iowrite32be(0, (u32 *)bd);
/* clear bd buffer */
- out_be32(&bd->buf, 0);
+ qe_iowrite32be(0, &bd->buf);
bd++;
}
/* for last BD set Wrap bit */
- out_be32((u32*)bd, cpu_to_be32(R_W));
- out_be32(&bd->buf, 0);
+ qe_iowrite32be(cpu_to_be32(R_W), (u32 *)bd);
+ qe_iowrite32be(0, &bd->buf);
/* Set GUMR (For more details see the hardware spec.). */
/* gumr_h */
@@ -269,7 +269,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
gumr |= UCC_SLOW_GUMR_H_TXSY;
if (us_info->rtsm)
gumr |= UCC_SLOW_GUMR_H_RTSM;
- out_be32(&us_regs->gumr_h, gumr);
+ qe_iowrite32be(gumr, &us_regs->gumr_h);
/* gumr_l */
gumr = us_info->tdcr | us_info->rdcr | us_info->tenc | us_info->renc |
@@ -282,7 +282,7 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
gumr |= UCC_SLOW_GUMR_L_TINV;
if (us_info->tend)
gumr |= UCC_SLOW_GUMR_L_TEND;
- out_be32(&us_regs->gumr_l, gumr);
+ qe_iowrite32be(gumr, &us_regs->gumr_l);
/* Function code registers */
@@ -292,8 +292,8 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
uccs->us_pram->rbmr = UCC_BMR_BO_BE;
/* rbase, tbase are offsets from MURAM base */
- out_be16(&uccs->us_pram->rbase, uccs->rx_base_offset);
- out_be16(&uccs->us_pram->tbase, uccs->tx_base_offset);
+ qe_iowrite16be(uccs->rx_base_offset, &uccs->us_pram->rbase);
+ qe_iowrite16be(uccs->tx_base_offset, &uccs->us_pram->tbase);
/* Mux clocking */
/* Grant Support */
@@ -323,14 +323,14 @@ int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** ucc
}
/* Set interrupt mask register at UCC level. */
- out_be16(&us_regs->uccm, us_info->uccm_mask);
+ qe_iowrite16be(us_info->uccm_mask, &us_regs->uccm);
/* First, clear anything pending at UCC level,
* otherwise, old garbage may come through
* as soon as the dam is opened. */
/* Writing '1' clears */
- out_be16(&us_regs->ucce, 0xffff);
+ qe_iowrite16be(0xffff, &us_regs->ucce);
/* Issue QE Init command */
if (us_info->init_tx && us_info->init_rx)
diff --git a/drivers/soc/fsl/qe/usb.c b/drivers/soc/fsl/qe/usb.c
index 32d8269fa692..890f236ea697 100644
--- a/drivers/soc/fsl/qe/usb.c
+++ b/drivers/soc/fsl/qe/usb.c
@@ -43,7 +43,7 @@ int qe_usb_clock_set(enum qe_clock clk, int rate)
spin_lock_irqsave(&cmxgcr_lock, flags);
- clrsetbits_be32(&mux->cmxgcr, QE_CMXGCR_USBCS, val);
+ qe_clrsetbits_be32(&mux->cmxgcr, QE_CMXGCR_USBCS, val);
spin_unlock_irqrestore(&cmxgcr_lock, flags);
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 06/36] soc: fsl: qe: replace spin_event_timeout by readx_poll_timeout_atomic
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (4 preceding siblings ...)
2019-11-01 12:41 ` [PATCH v3 05/36] soc: fsl: qe: avoid ppc-specific io accessors Rasmus Villemoes
@ 2019-11-01 12:41 ` Rasmus Villemoes
2019-11-01 12:41 ` [PATCH v3 07/36] soc: fsl: qe: qe.c: guard use of pvr_version_is() with CONFIG_PPC32 Rasmus Villemoes
` (29 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:41 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes
In preparation for allowing QE to be built for architectures other
than ppc, use the generic readx_poll_timeout_atomic() helper from
iopoll.h rather than the ppc-only spin_event_timeout().
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/soc/fsl/qe/qe.c | 13 +++++++------
1 file changed, 7 insertions(+), 6 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index 456bd7416876..85737e6f5b62 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -22,6 +22,7 @@
#include <linux/module.h>
#include <linux/delay.h>
#include <linux/ioport.h>
+#include <linux/iopoll.h>
#include <linux/crc32.h>
#include <linux/mod_devicetable.h>
#include <linux/of_platform.h>
@@ -108,7 +109,8 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
{
unsigned long flags;
u8 mcn_shift = 0, dev_shift = 0;
- u32 ret;
+ u32 val;
+ int ret;
spin_lock_irqsave(&qe_lock, flags);
if (cmd == QE_RESET) {
@@ -135,13 +137,12 @@ int qe_issue_cmd(u32 cmd, u32 device, u8 mcn_protocol, u32 cmd_input)
}
/* wait for the QE_CR_FLG to clear */
- ret = spin_event_timeout((qe_ioread32be(&qe_immr->cp.cecr) & QE_CR_FLG) == 0,
- 100, 0);
- /* On timeout (e.g. failure), the expression will be false (ret == 0),
- otherwise it will be true (ret == 1). */
+ ret = readx_poll_timeout_atomic(qe_ioread32be, &qe_immr->cp.cecr, val,
+ (val & QE_CR_FLG) == 0, 0, 100);
+ /* On timeout, ret is -ETIMEDOUT, otherwise it will be 0. */
spin_unlock_irqrestore(&qe_lock, flags);
- return ret == 1;
+ return ret == 0;
}
EXPORT_SYMBOL(qe_issue_cmd);
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 07/36] soc: fsl: qe: qe.c: guard use of pvr_version_is() with CONFIG_PPC32
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (5 preceding siblings ...)
2019-11-01 12:41 ` [PATCH v3 06/36] soc: fsl: qe: replace spin_event_timeout by readx_poll_timeout_atomic Rasmus Villemoes
@ 2019-11-01 12:41 ` Rasmus Villemoes
2019-11-01 12:41 ` [PATCH v3 08/36] soc: fsl: qe: drop unneeded #includes Rasmus Villemoes
` (28 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:41 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes
Commit e5c5c8d23fef (soc/fsl/qe: only apply QE_General4 workaround on
affected SoCs) introduced use of pvr_version_is(), saying
The QE_General4 workaround is only valid for the MPC832x and MPC836x
SoCs. The other SoCs that embed a QUICC engine are not affected by this
hardware bug and thus can use the computed divisors (this was
successfully tested on the T1040).
I'm reading the above as saying that the errata does not apply to the
ARM-based SOCs with QUICC engine. In any case, use of pvr_version_is()
must be guarded by CONFIG_PPC32 before we can remove the PPC32
dependency from CONFIG_QUICC_ENGINE, so introduce qe_general4_errata()
to keep the necessary #ifdeffery localized to a trivial helper.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/soc/fsl/qe/qe.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index 85737e6f5b62..1d8aa62c7ddf 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -197,6 +197,14 @@ EXPORT_SYMBOL(qe_get_brg_clk);
#define PVR_VER_836x 0x8083
#define PVR_VER_832x 0x8084
+static bool qe_general4_errata(void)
+{
+#ifdef CONFIG_PPC32
+ return pvr_version_is(PVR_VER_836x) || pvr_version_is(PVR_VER_832x);
+#endif
+ return false;
+}
+
/* Program the BRG to the given sampling rate and multiplier
*
* @brg: the BRG, QE_BRG1 - QE_BRG16
@@ -223,7 +231,7 @@ int qe_setbrg(enum qe_clock brg, unsigned int rate, unsigned int multiplier)
/* Errata QE_General4, which affects some MPC832x and MPC836x SOCs, says
that the BRG divisor must be even if you're not using divide-by-16
mode. */
- if (pvr_version_is(PVR_VER_836x) || pvr_version_is(PVR_VER_832x))
+ if (qe_general4_errata())
if (!div16 && (divisor & 1) && (divisor > 3))
divisor++;
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 08/36] soc: fsl: qe: drop unneeded #includes
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (6 preceding siblings ...)
2019-11-01 12:41 ` [PATCH v3 07/36] soc: fsl: qe: qe.c: guard use of pvr_version_is() with CONFIG_PPC32 Rasmus Villemoes
@ 2019-11-01 12:41 ` Rasmus Villemoes
2019-11-01 12:41 ` [PATCH v3 09/36] soc: fsl: qe: drop assign-only high_active in qe_ic_init Rasmus Villemoes
` (27 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:41 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes
These includes are not actually needed, and asm/rheap.h and
sysdev/fsl_soc.h are PPC-specific, hence prevent compiling QE for
other architectures.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/soc/fsl/qe/qe.c | 5 -----
drivers/soc/fsl/qe/qe_io.c | 2 --
2 files changed, 7 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index 1d8aa62c7ddf..a4763282ea68 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -26,13 +26,8 @@
#include <linux/crc32.h>
#include <linux/mod_devicetable.h>
#include <linux/of_platform.h>
-#include <asm/irq.h>
-#include <asm/page.h>
-#include <asm/pgtable.h>
#include <soc/fsl/qe/immap_qe.h>
#include <soc/fsl/qe/qe.h>
-#include <asm/prom.h>
-#include <asm/rheap.h>
static void qe_snums_init(void);
static int qe_sdma_init(void);
diff --git a/drivers/soc/fsl/qe/qe_io.c b/drivers/soc/fsl/qe/qe_io.c
index 5e3471ac09dd..f6b10f38b2f4 100644
--- a/drivers/soc/fsl/qe/qe_io.c
+++ b/drivers/soc/fsl/qe/qe_io.c
@@ -18,8 +18,6 @@
#include <asm/io.h>
#include <soc/fsl/qe/qe.h>
-#include <asm/prom.h>
-#include <sysdev/fsl_soc.h>
#undef DEBUG
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 09/36] soc: fsl: qe: drop assign-only high_active in qe_ic_init
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (7 preceding siblings ...)
2019-11-01 12:41 ` [PATCH v3 08/36] soc: fsl: qe: drop unneeded #includes Rasmus Villemoes
@ 2019-11-01 12:41 ` Rasmus Villemoes
2019-11-01 12:41 ` [PATCH v3 10/36] soc: fsl: qe: remove pointless sysfs registration in qe_ic.c Rasmus Villemoes
` (26 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:41 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes
high_active is only assigned to but never used. Remove it.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/soc/fsl/qe/qe_ic.c | 6 ++----
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index 8c874372416b..4b03060d8079 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -320,7 +320,7 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags,
{
struct qe_ic *qe_ic;
struct resource res;
- u32 temp = 0, ret, high_active = 0;
+ u32 temp = 0, ret;
ret = of_address_to_resource(node, 0, &res);
if (ret)
@@ -366,10 +366,8 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags,
temp |= CICR_GRTB;
/* choose destination signal for highest priority interrupt */
- if (flags & QE_IC_HIGH_SIGNAL) {
+ if (flags & QE_IC_HIGH_SIGNAL)
temp |= (SIGNAL_HIGH << CICR_HPIT_SHIFT);
- high_active = 1;
- }
qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 10/36] soc: fsl: qe: remove pointless sysfs registration in qe_ic.c
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (8 preceding siblings ...)
2019-11-01 12:41 ` [PATCH v3 09/36] soc: fsl: qe: drop assign-only high_active in qe_ic_init Rasmus Villemoes
@ 2019-11-01 12:41 ` Rasmus Villemoes
2019-11-01 12:41 ` [PATCH v3 11/36] soc: fsl: qe: use qe_ic_cascade_{low,high}_mpic also on 83xx Rasmus Villemoes
` (25 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:41 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes
There's no point in registering with sysfs when that doesn't actually
allow any interaction with the device or driver (no uevents, no sysfs
files that provide information or allow configuration, no nothing).
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/soc/fsl/qe/qe_ic.c | 31 -------------------------------
1 file changed, 31 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index 4b03060d8079..f170926ce4d1 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -474,34 +474,3 @@ int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
return 0;
}
-
-static struct bus_type qe_ic_subsys = {
- .name = "qe_ic",
- .dev_name = "qe_ic",
-};
-
-static struct device device_qe_ic = {
- .id = 0,
- .bus = &qe_ic_subsys,
-};
-
-static int __init init_qe_ic_sysfs(void)
-{
- int rc;
-
- printk(KERN_DEBUG "Registering qe_ic with sysfs...\n");
-
- rc = subsys_system_register(&qe_ic_subsys, NULL);
- if (rc) {
- printk(KERN_ERR "Failed registering qe_ic sys class\n");
- return -ENODEV;
- }
- rc = device_register(&device_qe_ic);
- if (rc) {
- printk(KERN_ERR "Failed registering qe_ic sys device\n");
- return -ENODEV;
- }
- return 0;
-}
-
-subsys_initcall(init_qe_ic_sysfs);
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 11/36] soc: fsl: qe: use qe_ic_cascade_{low,high}_mpic also on 83xx
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (9 preceding siblings ...)
2019-11-01 12:41 ` [PATCH v3 10/36] soc: fsl: qe: remove pointless sysfs registration in qe_ic.c Rasmus Villemoes
@ 2019-11-01 12:41 ` Rasmus Villemoes
2019-11-01 12:41 ` [PATCH v3 12/36] soc: fsl: qe: move calls of qe_ic_init out of arch/powerpc/ Rasmus Villemoes
` (24 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:41 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes
The *_ipic and *_mpic handlers are almost identical - the only
difference is that the latter end with an unconditional
chip->irq_eoi() call. Since IPIC does not have ->irq_eoi, we can
reduce some code duplication by calling irq_eoi conditionally.
This is similar to what is already done in mpc8xxx_gpio_irq_cascade().
This leaves the functions slightly misnamed, but that will be fixed in
a subsequent patch.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
arch/powerpc/platforms/83xx/misc.c | 2 +-
include/soc/fsl/qe/qe_ic.h | 24 ++++--------------------
2 files changed, 5 insertions(+), 21 deletions(-)
diff --git a/arch/powerpc/platforms/83xx/misc.c b/arch/powerpc/platforms/83xx/misc.c
index f46d7bf3b140..779791c0570f 100644
--- a/arch/powerpc/platforms/83xx/misc.c
+++ b/arch/powerpc/platforms/83xx/misc.c
@@ -100,7 +100,7 @@ void __init mpc83xx_qe_init_IRQ(void)
if (!np)
return;
}
- qe_ic_init(np, 0, qe_ic_cascade_low_ipic, qe_ic_cascade_high_ipic);
+ qe_ic_init(np, 0, qe_ic_cascade_low_mpic, qe_ic_cascade_high_mpic);
of_node_put(np);
}
diff --git a/include/soc/fsl/qe/qe_ic.h b/include/soc/fsl/qe/qe_ic.h
index 714a9b890d8d..bfaa233d8328 100644
--- a/include/soc/fsl/qe/qe_ic.h
+++ b/include/soc/fsl/qe/qe_ic.h
@@ -74,24 +74,6 @@ void qe_ic_set_highest_priority(unsigned int virq, int high);
int qe_ic_set_priority(unsigned int virq, unsigned int priority);
int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
-static inline void qe_ic_cascade_low_ipic(struct irq_desc *desc)
-{
- struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
- unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
-
- if (cascade_irq != NO_IRQ)
- generic_handle_irq(cascade_irq);
-}
-
-static inline void qe_ic_cascade_high_ipic(struct irq_desc *desc)
-{
- struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
- unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
-
- if (cascade_irq != NO_IRQ)
- generic_handle_irq(cascade_irq);
-}
-
static inline void qe_ic_cascade_low_mpic(struct irq_desc *desc)
{
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
@@ -101,7 +83,8 @@ static inline void qe_ic_cascade_low_mpic(struct irq_desc *desc)
if (cascade_irq != NO_IRQ)
generic_handle_irq(cascade_irq);
- chip->irq_eoi(&desc->irq_data);
+ if (chip->irq_eoi)
+ chip->irq_eoi(&desc->irq_data);
}
static inline void qe_ic_cascade_high_mpic(struct irq_desc *desc)
@@ -113,7 +96,8 @@ static inline void qe_ic_cascade_high_mpic(struct irq_desc *desc)
if (cascade_irq != NO_IRQ)
generic_handle_irq(cascade_irq);
- chip->irq_eoi(&desc->irq_data);
+ if (chip->irq_eoi)
+ chip->irq_eoi(&desc->irq_data);
}
static inline void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 12/36] soc: fsl: qe: move calls of qe_ic_init out of arch/powerpc/
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (10 preceding siblings ...)
2019-11-01 12:41 ` [PATCH v3 11/36] soc: fsl: qe: use qe_ic_cascade_{low,high}_mpic also on 83xx Rasmus Villemoes
@ 2019-11-01 12:41 ` Rasmus Villemoes
2019-11-01 12:41 ` [PATCH v3 13/36] powerpc/83xx: remove mpc83xx_ipic_and_qe_init_IRQ Rasmus Villemoes
` (23 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:41 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes
Having to call qe_ic_init() from platform-specific code makes it
awkward to allow building the QE drivers for ARM. It's also a needless
duplication of code, and slightly error-prone: Instead of the caller
needing to know the details of whether the QUICC Engine High and QUICC
Engine Low are actually the same interrupt (see e.g. the machine_is()
in mpc85xx_mds_qeic_init), just let the init function choose the
appropriate handlers after it has parsed the DT and figured it out. If
the two interrupts are distinct, use separate handlers, otherwise use
the handler which first checks the CHIVEC register (for the high
priority interrupts), then the CIVEC.
All existing callers pass 0 for flags, so continue to do that from the
new single caller. Later cleanups will remove that argument
from qe_ic_init and simplify the body, as well as make qe_ic_init into
a proper init function for an IRQCHIP_DECLARE, eliminating the need to
manually look up the fsl,qe-ic node.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
arch/powerpc/platforms/83xx/km83xx.c | 1 -
arch/powerpc/platforms/83xx/misc.c | 16 ----------
arch/powerpc/platforms/83xx/mpc832x_mds.c | 1 -
arch/powerpc/platforms/83xx/mpc832x_rdb.c | 1 -
arch/powerpc/platforms/83xx/mpc836x_mds.c | 1 -
arch/powerpc/platforms/83xx/mpc836x_rdk.c | 1 -
arch/powerpc/platforms/83xx/mpc83xx.h | 2 --
arch/powerpc/platforms/85xx/corenet_generic.c | 10 -------
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 27 -----------------
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 17 -----------
arch/powerpc/platforms/85xx/twr_p102x.c | 15 ----------
drivers/soc/fsl/qe/qe_ic.c | 29 +++++++++++++++++--
include/soc/fsl/qe/qe_ic.h | 7 -----
13 files changed, 26 insertions(+), 102 deletions(-)
diff --git a/arch/powerpc/platforms/83xx/km83xx.c b/arch/powerpc/platforms/83xx/km83xx.c
index 273145aed90a..5c6227f7bc37 100644
--- a/arch/powerpc/platforms/83xx/km83xx.c
+++ b/arch/powerpc/platforms/83xx/km83xx.c
@@ -34,7 +34,6 @@
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include <soc/fsl/qe/qe.h>
-#include <soc/fsl/qe/qe_ic.h>
#include "mpc83xx.h"
diff --git a/arch/powerpc/platforms/83xx/misc.c b/arch/powerpc/platforms/83xx/misc.c
index 779791c0570f..6935a5b9fbd1 100644
--- a/arch/powerpc/platforms/83xx/misc.c
+++ b/arch/powerpc/platforms/83xx/misc.c
@@ -14,7 +14,6 @@
#include <asm/io.h>
#include <asm/hw_irq.h>
#include <asm/ipic.h>
-#include <soc/fsl/qe/qe_ic.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
@@ -90,24 +89,9 @@ void __init mpc83xx_ipic_init_IRQ(void)
}
#ifdef CONFIG_QUICC_ENGINE
-void __init mpc83xx_qe_init_IRQ(void)
-{
- struct device_node *np;
-
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (!np) {
- np = of_find_node_by_type(NULL, "qeic");
- if (!np)
- return;
- }
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic, qe_ic_cascade_high_mpic);
- of_node_put(np);
-}
-
void __init mpc83xx_ipic_and_qe_init_IRQ(void)
{
mpc83xx_ipic_init_IRQ();
- mpc83xx_qe_init_IRQ();
}
#endif /* CONFIG_QUICC_ENGINE */
diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c b/arch/powerpc/platforms/83xx/mpc832x_mds.c
index b428835e5919..1c73af104d19 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_mds.c
@@ -33,7 +33,6 @@
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
#include <soc/fsl/qe/qe.h>
-#include <soc/fsl/qe/qe_ic.h>
#include "mpc83xx.h"
diff --git a/arch/powerpc/platforms/83xx/mpc832x_rdb.c b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
index 4588ce632484..87f68ca06255 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
@@ -22,7 +22,6 @@
#include <asm/ipic.h>
#include <asm/udbg.h>
#include <soc/fsl/qe/qe.h>
-#include <soc/fsl/qe/qe_ic.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c
index 4a4efa906d35..5b484da9533e 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c
@@ -41,7 +41,6 @@
#include <sysdev/fsl_pci.h>
#include <sysdev/simple_gpio.h>
#include <soc/fsl/qe/qe.h>
-#include <soc/fsl/qe/qe_ic.h>
#include "mpc83xx.h"
diff --git a/arch/powerpc/platforms/83xx/mpc836x_rdk.c b/arch/powerpc/platforms/83xx/mpc836x_rdk.c
index 9923059cb111..b7119e443920 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_rdk.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_rdk.c
@@ -17,7 +17,6 @@
#include <asm/ipic.h>
#include <asm/udbg.h>
#include <soc/fsl/qe/qe.h>
-#include <soc/fsl/qe/qe_ic.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h b/arch/powerpc/platforms/83xx/mpc83xx.h
index 459145623334..d343f6ce2599 100644
--- a/arch/powerpc/platforms/83xx/mpc83xx.h
+++ b/arch/powerpc/platforms/83xx/mpc83xx.h
@@ -73,10 +73,8 @@ extern int mpc834x_usb_cfg(void);
extern int mpc831x_usb_cfg(void);
extern void mpc83xx_ipic_init_IRQ(void);
#ifdef CONFIG_QUICC_ENGINE
-extern void mpc83xx_qe_init_IRQ(void);
extern void mpc83xx_ipic_and_qe_init_IRQ(void);
#else
-static inline void __init mpc83xx_qe_init_IRQ(void) {}
#define mpc83xx_ipic_and_qe_init_IRQ mpc83xx_ipic_init_IRQ
#endif /* CONFIG_QUICC_ENGINE */
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c b/arch/powerpc/platforms/85xx/corenet_generic.c
index 7ee2c6628f64..8c1bb3941642 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -24,7 +24,6 @@
#include <asm/mpic.h>
#include <asm/ehv_pic.h>
#include <asm/swiotlb.h>
-#include <soc/fsl/qe/qe_ic.h>
#include <linux/of_platform.h>
#include <sysdev/fsl_soc.h>
@@ -38,8 +37,6 @@ void __init corenet_gen_pic_init(void)
unsigned int flags = MPIC_BIG_ENDIAN | MPIC_SINGLE_DEST_CPU |
MPIC_NO_RESET;
- struct device_node *np;
-
if (ppc_md.get_irq == mpic_get_coreint_irq)
flags |= MPIC_ENABLE_COREINT;
@@ -47,13 +44,6 @@ void __init corenet_gen_pic_init(void)
BUG_ON(mpic == NULL);
mpic_init(mpic);
-
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (np) {
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
- of_node_put(np);
- }
}
/*
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 5ca254256c47..4bc49e5ec0b6 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -45,7 +45,6 @@
#include <sysdev/fsl_pci.h>
#include <sysdev/simple_gpio.h>
#include <soc/fsl/qe/qe.h>
-#include <soc/fsl/qe/qe_ic.h>
#include <asm/mpic.h>
#include <asm/swiotlb.h>
#include "smp.h"
@@ -270,33 +269,8 @@ static void __init mpc85xx_mds_qe_init(void)
}
}
-static void __init mpc85xx_mds_qeic_init(void)
-{
- struct device_node *np;
-
- np = of_find_compatible_node(NULL, NULL, "fsl,qe");
- if (!of_device_is_available(np)) {
- of_node_put(np);
- return;
- }
-
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (!np) {
- np = of_find_node_by_type(NULL, "qeic");
- if (!np)
- return;
- }
-
- if (machine_is(p1021_mds))
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
- else
- qe_ic_init(np, 0, qe_ic_cascade_muxed_mpic, NULL);
- of_node_put(np);
-}
#else
static void __init mpc85xx_mds_qe_init(void) { }
-static void __init mpc85xx_mds_qeic_init(void) { }
#endif /* CONFIG_QUICC_ENGINE */
static void __init mpc85xx_mds_setup_arch(void)
@@ -371,7 +345,6 @@ static void __init mpc85xx_mds_pic_init(void)
BUG_ON(mpic == NULL);
mpic_init(mpic);
- mpc85xx_mds_qeic_init();
}
static int __init mpc85xx_mds_probe(void)
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index d3c540ee558f..14b5a61d49c1 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -23,7 +23,6 @@
#include <asm/udbg.h>
#include <asm/mpic.h>
#include <soc/fsl/qe/qe.h>
-#include <soc/fsl/qe/qe_ic.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
@@ -44,10 +43,6 @@ void __init mpc85xx_rdb_pic_init(void)
{
struct mpic *mpic;
-#ifdef CONFIG_QUICC_ENGINE
- struct device_node *np;
-#endif
-
if (of_machine_is_compatible("fsl,MPC85XXRDB-CAMP")) {
mpic = mpic_alloc(NULL, 0, MPIC_NO_RESET |
MPIC_BIG_ENDIAN |
@@ -62,18 +57,6 @@ void __init mpc85xx_rdb_pic_init(void)
BUG_ON(mpic == NULL);
mpic_init(mpic);
-
-#ifdef CONFIG_QUICC_ENGINE
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (np) {
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
- of_node_put(np);
-
- } else
- pr_err("%s: Could not find qe-ic node\n", __func__);
-#endif
-
}
/*
diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c b/arch/powerpc/platforms/85xx/twr_p102x.c
index 720b0c0f03ba..b099f5607120 100644
--- a/arch/powerpc/platforms/85xx/twr_p102x.c
+++ b/arch/powerpc/platforms/85xx/twr_p102x.c
@@ -19,7 +19,6 @@
#include <asm/udbg.h>
#include <asm/mpic.h>
#include <soc/fsl/qe/qe.h>
-#include <soc/fsl/qe/qe_ic.h>
#include <sysdev/fsl_soc.h>
#include <sysdev/fsl_pci.h>
@@ -31,26 +30,12 @@ static void __init twr_p1025_pic_init(void)
{
struct mpic *mpic;
-#ifdef CONFIG_QUICC_ENGINE
- struct device_node *np;
-#endif
-
mpic = mpic_alloc(NULL, 0, MPIC_BIG_ENDIAN |
MPIC_SINGLE_DEST_CPU,
0, 256, " OpenPIC ");
BUG_ON(mpic == NULL);
mpic_init(mpic);
-
-#ifdef CONFIG_QUICC_ENGINE
- np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
- if (np) {
- qe_ic_init(np, 0, qe_ic_cascade_low_mpic,
- qe_ic_cascade_high_mpic);
- of_node_put(np);
- } else
- pr_err("Could not find qe-ic node\n");
-#endif
}
/* ************************************************************************
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index f170926ce4d1..a062efac398b 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -314,10 +314,10 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
return irq_linear_revmap(qe_ic->irqhost, irq);
}
-void __init qe_ic_init(struct device_node *node, unsigned int flags,
- void (*low_handler)(struct irq_desc *desc),
- void (*high_handler)(struct irq_desc *desc))
+static void __init qe_ic_init(struct device_node *node, unsigned int flags)
{
+ void (*low_handler)(struct irq_desc *desc);
+ void (*high_handler)(struct irq_desc *desc);
struct qe_ic *qe_ic;
struct resource res;
u32 temp = 0, ret;
@@ -349,6 +349,13 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags,
kfree(qe_ic);
return;
}
+ if (qe_ic->virq_high != qe_ic->virq_low) {
+ low_handler = qe_ic_cascade_low_mpic;
+ high_handler = qe_ic_cascade_high_mpic;
+ } else {
+ low_handler = qe_ic_cascade_muxed_mpic;
+ high_handler = NULL;
+ }
/* default priority scheme is grouped. If spread mode is */
/* required, configure cicr accordingly. */
@@ -381,6 +388,22 @@ void __init qe_ic_init(struct device_node *node, unsigned int flags,
}
}
+static int __init qe_ic_of_init(void)
+{
+ struct device_node *np;
+
+ np = of_find_compatible_node(NULL, NULL, "fsl,qe-ic");
+ if (!np) {
+ np = of_find_node_by_type(NULL, "qeic");
+ if (!np)
+ return -ENODEV;
+ }
+ qe_ic_init(np, 0);
+ of_node_put(np);
+ return 0;
+}
+subsys_initcall(qe_ic_of_init);
+
void qe_ic_set_highest_priority(unsigned int virq, int high)
{
struct qe_ic *qe_ic = qe_ic_from_irq(virq);
diff --git a/include/soc/fsl/qe/qe_ic.h b/include/soc/fsl/qe/qe_ic.h
index bfaa233d8328..a47a0d26acbd 100644
--- a/include/soc/fsl/qe/qe_ic.h
+++ b/include/soc/fsl/qe/qe_ic.h
@@ -54,16 +54,9 @@ enum qe_ic_grp_id {
};
#ifdef CONFIG_QUICC_ENGINE
-void qe_ic_init(struct device_node *node, unsigned int flags,
- void (*low_handler)(struct irq_desc *desc),
- void (*high_handler)(struct irq_desc *desc));
unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
#else
-static inline void qe_ic_init(struct device_node *node, unsigned int flags,
- void (*low_handler)(struct irq_desc *desc),
- void (*high_handler)(struct irq_desc *desc))
-{}
static inline unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
{ return 0; }
static inline unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 13/36] powerpc/83xx: remove mpc83xx_ipic_and_qe_init_IRQ
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (11 preceding siblings ...)
2019-11-01 12:41 ` [PATCH v3 12/36] soc: fsl: qe: move calls of qe_ic_init out of arch/powerpc/ Rasmus Villemoes
@ 2019-11-01 12:41 ` Rasmus Villemoes
2019-11-01 12:41 ` [PATCH v3 14/36] powerpc/85xx: remove mostly pointless mpc85xx_qe_init() Rasmus Villemoes
` (22 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:41 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes
This is now exactly the same as mpc83xx_ipic_init_IRQ, so just use
that directly.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
arch/powerpc/platforms/83xx/km83xx.c | 2 +-
arch/powerpc/platforms/83xx/misc.c | 7 -------
arch/powerpc/platforms/83xx/mpc832x_mds.c | 2 +-
arch/powerpc/platforms/83xx/mpc832x_rdb.c | 2 +-
arch/powerpc/platforms/83xx/mpc836x_mds.c | 2 +-
arch/powerpc/platforms/83xx/mpc836x_rdk.c | 2 +-
arch/powerpc/platforms/83xx/mpc83xx.h | 5 -----
7 files changed, 5 insertions(+), 17 deletions(-)
diff --git a/arch/powerpc/platforms/83xx/km83xx.c b/arch/powerpc/platforms/83xx/km83xx.c
index 5c6227f7bc37..3d89569e9e71 100644
--- a/arch/powerpc/platforms/83xx/km83xx.c
+++ b/arch/powerpc/platforms/83xx/km83xx.c
@@ -177,7 +177,7 @@ define_machine(mpc83xx_km) {
.name = "mpc83xx-km-platform",
.probe = mpc83xx_km_probe,
.setup_arch = mpc83xx_km_setup_arch,
- .init_IRQ = mpc83xx_ipic_and_qe_init_IRQ,
+ .init_IRQ = mpc83xx_ipic_init_IRQ,
.get_irq = ipic_get_irq,
.restart = mpc83xx_restart,
.time_init = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/misc.c b/arch/powerpc/platforms/83xx/misc.c
index 6935a5b9fbd1..1d8306eb2958 100644
--- a/arch/powerpc/platforms/83xx/misc.c
+++ b/arch/powerpc/platforms/83xx/misc.c
@@ -88,13 +88,6 @@ void __init mpc83xx_ipic_init_IRQ(void)
ipic_set_default_priority();
}
-#ifdef CONFIG_QUICC_ENGINE
-void __init mpc83xx_ipic_and_qe_init_IRQ(void)
-{
- mpc83xx_ipic_init_IRQ();
-}
-#endif /* CONFIG_QUICC_ENGINE */
-
static const struct of_device_id of_bus_ids[] __initconst = {
{ .type = "soc", },
{ .compatible = "soc", },
diff --git a/arch/powerpc/platforms/83xx/mpc832x_mds.c b/arch/powerpc/platforms/83xx/mpc832x_mds.c
index 1c73af104d19..6fa5402ebf20 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_mds.c
@@ -101,7 +101,7 @@ define_machine(mpc832x_mds) {
.name = "MPC832x MDS",
.probe = mpc832x_sys_probe,
.setup_arch = mpc832x_sys_setup_arch,
- .init_IRQ = mpc83xx_ipic_and_qe_init_IRQ,
+ .init_IRQ = mpc83xx_ipic_init_IRQ,
.get_irq = ipic_get_irq,
.restart = mpc83xx_restart,
.time_init = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc832x_rdb.c b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
index 87f68ca06255..622c625d5ce4 100644
--- a/arch/powerpc/platforms/83xx/mpc832x_rdb.c
+++ b/arch/powerpc/platforms/83xx/mpc832x_rdb.c
@@ -219,7 +219,7 @@ define_machine(mpc832x_rdb) {
.name = "MPC832x RDB",
.probe = mpc832x_rdb_probe,
.setup_arch = mpc832x_rdb_setup_arch,
- .init_IRQ = mpc83xx_ipic_and_qe_init_IRQ,
+ .init_IRQ = mpc83xx_ipic_init_IRQ,
.get_irq = ipic_get_irq,
.restart = mpc83xx_restart,
.time_init = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc836x_mds.c b/arch/powerpc/platforms/83xx/mpc836x_mds.c
index 5b484da9533e..219a83ab6c00 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_mds.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_mds.c
@@ -208,7 +208,7 @@ define_machine(mpc836x_mds) {
.name = "MPC836x MDS",
.probe = mpc836x_mds_probe,
.setup_arch = mpc836x_mds_setup_arch,
- .init_IRQ = mpc83xx_ipic_and_qe_init_IRQ,
+ .init_IRQ = mpc83xx_ipic_init_IRQ,
.get_irq = ipic_get_irq,
.restart = mpc83xx_restart,
.time_init = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc836x_rdk.c b/arch/powerpc/platforms/83xx/mpc836x_rdk.c
index b7119e443920..b4aac2cde849 100644
--- a/arch/powerpc/platforms/83xx/mpc836x_rdk.c
+++ b/arch/powerpc/platforms/83xx/mpc836x_rdk.c
@@ -41,7 +41,7 @@ define_machine(mpc836x_rdk) {
.name = "MPC836x RDK",
.probe = mpc836x_rdk_probe,
.setup_arch = mpc836x_rdk_setup_arch,
- .init_IRQ = mpc83xx_ipic_and_qe_init_IRQ,
+ .init_IRQ = mpc83xx_ipic_init_IRQ,
.get_irq = ipic_get_irq,
.restart = mpc83xx_restart,
.time_init = mpc83xx_time_init,
diff --git a/arch/powerpc/platforms/83xx/mpc83xx.h b/arch/powerpc/platforms/83xx/mpc83xx.h
index d343f6ce2599..f37d04332fc7 100644
--- a/arch/powerpc/platforms/83xx/mpc83xx.h
+++ b/arch/powerpc/platforms/83xx/mpc83xx.h
@@ -72,11 +72,6 @@ extern int mpc837x_usb_cfg(void);
extern int mpc834x_usb_cfg(void);
extern int mpc831x_usb_cfg(void);
extern void mpc83xx_ipic_init_IRQ(void);
-#ifdef CONFIG_QUICC_ENGINE
-extern void mpc83xx_ipic_and_qe_init_IRQ(void);
-#else
-#define mpc83xx_ipic_and_qe_init_IRQ mpc83xx_ipic_init_IRQ
-#endif /* CONFIG_QUICC_ENGINE */
#ifdef CONFIG_PCI
extern void mpc83xx_setup_pci(void);
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 14/36] powerpc/85xx: remove mostly pointless mpc85xx_qe_init()
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (12 preceding siblings ...)
2019-11-01 12:41 ` [PATCH v3 13/36] powerpc/83xx: remove mpc83xx_ipic_and_qe_init_IRQ Rasmus Villemoes
@ 2019-11-01 12:41 ` Rasmus Villemoes
2019-11-01 12:41 ` [PATCH v3 15/36] soc: fsl: qe: move qe_ic_cascade_* functions to qe_ic.c Rasmus Villemoes
` (21 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:41 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes
Since commit 302c059f2e7b (QE: use subsys_initcall to init qe),
mpc85xx_qe_init() has done nothing apart from possibly emitting a
pr_err(). As part of reducing the amount of QE-related code in
arch/powerpc/ (and eventually support QE on other architectures),
remove this low-hanging fruit.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
arch/powerpc/platforms/85xx/common.c | 23 -------------------
arch/powerpc/platforms/85xx/corenet_generic.c | 2 --
arch/powerpc/platforms/85xx/mpc85xx.h | 2 --
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 1 -
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 1 -
arch/powerpc/platforms/85xx/twr_p102x.c | 1 -
6 files changed, 30 deletions(-)
diff --git a/arch/powerpc/platforms/85xx/common.c b/arch/powerpc/platforms/85xx/common.c
index fe0606439b5a..a554b6d87cf7 100644
--- a/arch/powerpc/platforms/85xx/common.c
+++ b/arch/powerpc/platforms/85xx/common.c
@@ -86,29 +86,6 @@ void __init mpc85xx_cpm2_pic_init(void)
#endif
#ifdef CONFIG_QUICC_ENGINE
-void __init mpc85xx_qe_init(void)
-{
- struct device_node *np;
-
- np = of_find_compatible_node(NULL, NULL, "fsl,qe");
- if (!np) {
- np = of_find_node_by_name(NULL, "qe");
- if (!np) {
- pr_err("%s: Could not find Quicc Engine node\n",
- __func__);
- return;
- }
- }
-
- if (!of_device_is_available(np)) {
- of_node_put(np);
- return;
- }
-
- of_node_put(np);
-
-}
-
void __init mpc85xx_qe_par_io_init(void)
{
struct device_node *np;
diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c b/arch/powerpc/platforms/85xx/corenet_generic.c
index 8c1bb3941642..27ac38f7e1a9 100644
--- a/arch/powerpc/platforms/85xx/corenet_generic.c
+++ b/arch/powerpc/platforms/85xx/corenet_generic.c
@@ -56,8 +56,6 @@ void __init corenet_gen_setup_arch(void)
swiotlb_detect_4g();
pr_info("%s board\n", ppc_md.name);
-
- mpc85xx_qe_init();
}
static const struct of_device_id of_device_ids[] = {
diff --git a/arch/powerpc/platforms/85xx/mpc85xx.h b/arch/powerpc/platforms/85xx/mpc85xx.h
index fa23f9b0592c..cb84c5c56c36 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx.h
+++ b/arch/powerpc/platforms/85xx/mpc85xx.h
@@ -10,10 +10,8 @@ static inline void __init mpc85xx_cpm2_pic_init(void) {}
#endif /* CONFIG_CPM2 */
#ifdef CONFIG_QUICC_ENGINE
-extern void mpc85xx_qe_init(void);
extern void mpc85xx_qe_par_io_init(void);
#else
-static inline void __init mpc85xx_qe_init(void) {}
static inline void __init mpc85xx_qe_par_io_init(void) {}
#endif
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_mds.c b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
index 4bc49e5ec0b6..fb05b4d5bf1e 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_mds.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_mds.c
@@ -237,7 +237,6 @@ static void __init mpc85xx_mds_qe_init(void)
{
struct device_node *np;
- mpc85xx_qe_init();
mpc85xx_qe_par_io_init();
mpc85xx_mds_reset_ucc_phys();
diff --git a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
index 14b5a61d49c1..80a80174768c 100644
--- a/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
+++ b/arch/powerpc/platforms/85xx/mpc85xx_rdb.c
@@ -72,7 +72,6 @@ static void __init mpc85xx_rdb_setup_arch(void)
fsl_pci_assign_primary();
#ifdef CONFIG_QUICC_ENGINE
- mpc85xx_qe_init();
mpc85xx_qe_par_io_init();
#if defined(CONFIG_UCC_GETH) || defined(CONFIG_SERIAL_QE)
if (machine_is(p1025_rdb)) {
diff --git a/arch/powerpc/platforms/85xx/twr_p102x.c b/arch/powerpc/platforms/85xx/twr_p102x.c
index b099f5607120..9abb1e9f73c4 100644
--- a/arch/powerpc/platforms/85xx/twr_p102x.c
+++ b/arch/powerpc/platforms/85xx/twr_p102x.c
@@ -57,7 +57,6 @@ static void __init twr_p1025_setup_arch(void)
fsl_pci_assign_primary();
#ifdef CONFIG_QUICC_ENGINE
- mpc85xx_qe_init();
mpc85xx_qe_par_io_init();
#if IS_ENABLED(CONFIG_UCC_GETH) || IS_ENABLED(CONFIG_SERIAL_QE)
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 15/36] soc: fsl: qe: move qe_ic_cascade_* functions to qe_ic.c
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (13 preceding siblings ...)
2019-11-01 12:41 ` [PATCH v3 14/36] powerpc/85xx: remove mostly pointless mpc85xx_qe_init() Rasmus Villemoes
@ 2019-11-01 12:41 ` Rasmus Villemoes
2019-11-01 12:41 ` [PATCH v3 16/36] soc: fsl: qe: rename qe_ic_cascade_low_mpic -> qe_ic_cascade_low Rasmus Villemoes
` (20 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:41 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes
These functions are only ever called through a function pointer, and
therefore it makes no sense for them to be "static inline" - gcc has
no choice but to emit a copy in each translation unit that takes the
address of one of these. Since they are now only referenced from
qe_ic.c, just make them local to that file.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/soc/fsl/qe/qe_ic.c | 42 ++++++++++++++++++++++++++++++++++++++
include/soc/fsl/qe/qe_ic.h | 42 --------------------------------------
2 files changed, 42 insertions(+), 42 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index a062efac398b..94ccbeeb1ad1 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -314,6 +314,48 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
return irq_linear_revmap(qe_ic->irqhost, irq);
}
+static void qe_ic_cascade_low_mpic(struct irq_desc *desc)
+{
+ struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
+ unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+
+ if (cascade_irq != NO_IRQ)
+ generic_handle_irq(cascade_irq);
+
+ if (chip->irq_eoi)
+ chip->irq_eoi(&desc->irq_data);
+}
+
+static void qe_ic_cascade_high_mpic(struct irq_desc *desc)
+{
+ struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
+ unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+
+ if (cascade_irq != NO_IRQ)
+ generic_handle_irq(cascade_irq);
+
+ if (chip->irq_eoi)
+ chip->irq_eoi(&desc->irq_data);
+}
+
+static void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
+{
+ struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
+ unsigned int cascade_irq;
+ struct irq_chip *chip = irq_desc_get_chip(desc);
+
+ cascade_irq = qe_ic_get_high_irq(qe_ic);
+ if (cascade_irq == NO_IRQ)
+ cascade_irq = qe_ic_get_low_irq(qe_ic);
+
+ if (cascade_irq != NO_IRQ)
+ generic_handle_irq(cascade_irq);
+
+ chip->irq_eoi(&desc->irq_data);
+}
+
static void __init qe_ic_init(struct device_node *node, unsigned int flags)
{
void (*low_handler)(struct irq_desc *desc);
diff --git a/include/soc/fsl/qe/qe_ic.h b/include/soc/fsl/qe/qe_ic.h
index a47a0d26acbd..43e4ce95c6a0 100644
--- a/include/soc/fsl/qe/qe_ic.h
+++ b/include/soc/fsl/qe/qe_ic.h
@@ -67,46 +67,4 @@ void qe_ic_set_highest_priority(unsigned int virq, int high);
int qe_ic_set_priority(unsigned int virq, unsigned int priority);
int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
-static inline void qe_ic_cascade_low_mpic(struct irq_desc *desc)
-{
- struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
- unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
- struct irq_chip *chip = irq_desc_get_chip(desc);
-
- if (cascade_irq != NO_IRQ)
- generic_handle_irq(cascade_irq);
-
- if (chip->irq_eoi)
- chip->irq_eoi(&desc->irq_data);
-}
-
-static inline void qe_ic_cascade_high_mpic(struct irq_desc *desc)
-{
- struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
- unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
- struct irq_chip *chip = irq_desc_get_chip(desc);
-
- if (cascade_irq != NO_IRQ)
- generic_handle_irq(cascade_irq);
-
- if (chip->irq_eoi)
- chip->irq_eoi(&desc->irq_data);
-}
-
-static inline void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
-{
- struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
- unsigned int cascade_irq;
- struct irq_chip *chip = irq_desc_get_chip(desc);
-
- cascade_irq = qe_ic_get_high_irq(qe_ic);
- if (cascade_irq == NO_IRQ)
- cascade_irq = qe_ic_get_low_irq(qe_ic);
-
- if (cascade_irq != NO_IRQ)
- generic_handle_irq(cascade_irq);
-
- chip->irq_eoi(&desc->irq_data);
-}
-
#endif /* _ASM_POWERPC_QE_IC_H */
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 16/36] soc: fsl: qe: rename qe_ic_cascade_low_mpic -> qe_ic_cascade_low
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (14 preceding siblings ...)
2019-11-01 12:41 ` [PATCH v3 15/36] soc: fsl: qe: move qe_ic_cascade_* functions to qe_ic.c Rasmus Villemoes
@ 2019-11-01 12:41 ` Rasmus Villemoes
2019-11-01 12:41 ` [PATCH v3 17/36] soc: fsl: qe: remove unused qe_ic_set_* functions Rasmus Villemoes
` (19 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:41 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes
The qe_ic_cascade_{low,high}_mpic functions are now used as handlers
both when the interrupt parent is mpic as well as ipic, so remove the
_mpic suffix.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/soc/fsl/qe/qe_ic.c | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index 94ccbeeb1ad1..de2ca2e3a648 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -314,7 +314,7 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
return irq_linear_revmap(qe_ic->irqhost, irq);
}
-static void qe_ic_cascade_low_mpic(struct irq_desc *desc)
+static void qe_ic_cascade_low(struct irq_desc *desc)
{
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
@@ -327,7 +327,7 @@ static void qe_ic_cascade_low_mpic(struct irq_desc *desc)
chip->irq_eoi(&desc->irq_data);
}
-static void qe_ic_cascade_high_mpic(struct irq_desc *desc)
+static void qe_ic_cascade_high(struct irq_desc *desc)
{
struct qe_ic *qe_ic = irq_desc_get_handler_data(desc);
unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
@@ -392,8 +392,8 @@ static void __init qe_ic_init(struct device_node *node, unsigned int flags)
return;
}
if (qe_ic->virq_high != qe_ic->virq_low) {
- low_handler = qe_ic_cascade_low_mpic;
- high_handler = qe_ic_cascade_high_mpic;
+ low_handler = qe_ic_cascade_low;
+ high_handler = qe_ic_cascade_high;
} else {
low_handler = qe_ic_cascade_muxed_mpic;
high_handler = NULL;
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 17/36] soc: fsl: qe: remove unused qe_ic_set_* functions
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (15 preceding siblings ...)
2019-11-01 12:41 ` [PATCH v3 16/36] soc: fsl: qe: rename qe_ic_cascade_low_mpic -> qe_ic_cascade_low Rasmus Villemoes
@ 2019-11-01 12:41 ` Rasmus Villemoes
2019-11-01 12:41 ` [PATCH v3 18/36] soc: fsl: qe: don't use NO_IRQ in qe_ic.c Rasmus Villemoes
` (18 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:41 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes
There are no current callers of these functions, and they use the
ppc-specific virq_to_hw(). So removing them gets us one step closer to
building QE support for ARM.
If the functionality is ever actually needed, the code can be dug out
of git and then adapted to work on all architectures, but for future
reference please note that I believe qe_ic_set_priority is buggy: The
"priority < 4" should be "priority <= 4", and in the else branch 24
should be replaced by 28, at least if I'm reading the data sheet right.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/soc/fsl/qe/qe_ic.c | 94 --------------------------------------
include/soc/fsl/qe/qe_ic.h | 4 --
2 files changed, 98 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index de2ca2e3a648..4839dcd5c5d3 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -445,97 +445,3 @@ static int __init qe_ic_of_init(void)
return 0;
}
subsys_initcall(qe_ic_of_init);
-
-void qe_ic_set_highest_priority(unsigned int virq, int high)
-{
- struct qe_ic *qe_ic = qe_ic_from_irq(virq);
- unsigned int src = virq_to_hw(virq);
- u32 temp = 0;
-
- temp = qe_ic_read(qe_ic->regs, QEIC_CICR);
-
- temp &= ~CICR_HP_MASK;
- temp |= src << CICR_HP_SHIFT;
-
- temp &= ~CICR_HPIT_MASK;
- temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << CICR_HPIT_SHIFT;
-
- qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
-}
-
-/* Set Priority level within its group, from 1 to 8 */
-int qe_ic_set_priority(unsigned int virq, unsigned int priority)
-{
- struct qe_ic *qe_ic = qe_ic_from_irq(virq);
- unsigned int src = virq_to_hw(virq);
- u32 temp;
-
- if (priority > 8 || priority == 0)
- return -EINVAL;
- if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),
- "%s: Invalid hw irq number for QEIC\n", __func__))
- return -EINVAL;
- if (qe_ic_info[src].pri_reg == 0)
- return -EINVAL;
-
- temp = qe_ic_read(qe_ic->regs, qe_ic_info[src].pri_reg);
-
- if (priority < 4) {
- temp &= ~(0x7 << (32 - priority * 3));
- temp |= qe_ic_info[src].pri_code << (32 - priority * 3);
- } else {
- temp &= ~(0x7 << (24 - priority * 3));
- temp |= qe_ic_info[src].pri_code << (24 - priority * 3);
- }
-
- qe_ic_write(qe_ic->regs, qe_ic_info[src].pri_reg, temp);
-
- return 0;
-}
-
-/* Set a QE priority to use high irq, only priority 1~2 can use high irq */
-int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high)
-{
- struct qe_ic *qe_ic = qe_ic_from_irq(virq);
- unsigned int src = virq_to_hw(virq);
- u32 temp, control_reg = QEIC_CICNR, shift = 0;
-
- if (priority > 2 || priority == 0)
- return -EINVAL;
- if (WARN_ONCE(src >= ARRAY_SIZE(qe_ic_info),
- "%s: Invalid hw irq number for QEIC\n", __func__))
- return -EINVAL;
-
- switch (qe_ic_info[src].pri_reg) {
- case QEIC_CIPZCC:
- shift = CICNR_ZCC1T_SHIFT;
- break;
- case QEIC_CIPWCC:
- shift = CICNR_WCC1T_SHIFT;
- break;
- case QEIC_CIPYCC:
- shift = CICNR_YCC1T_SHIFT;
- break;
- case QEIC_CIPXCC:
- shift = CICNR_XCC1T_SHIFT;
- break;
- case QEIC_CIPRTA:
- shift = CRICR_RTA1T_SHIFT;
- control_reg = QEIC_CRICR;
- break;
- case QEIC_CIPRTB:
- shift = CRICR_RTB1T_SHIFT;
- control_reg = QEIC_CRICR;
- break;
- default:
- return -EINVAL;
- }
-
- shift += (2 - priority) * 2;
- temp = qe_ic_read(qe_ic->regs, control_reg);
- temp &= ~(SIGNAL_MASK << shift);
- temp |= (high ? SIGNAL_HIGH : SIGNAL_LOW) << shift;
- qe_ic_write(qe_ic->regs, control_reg, temp);
-
- return 0;
-}
diff --git a/include/soc/fsl/qe/qe_ic.h b/include/soc/fsl/qe/qe_ic.h
index 43e4ce95c6a0..d47eb231519e 100644
--- a/include/soc/fsl/qe/qe_ic.h
+++ b/include/soc/fsl/qe/qe_ic.h
@@ -63,8 +63,4 @@ static inline unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
{ return 0; }
#endif /* CONFIG_QUICC_ENGINE */
-void qe_ic_set_highest_priority(unsigned int virq, int high);
-int qe_ic_set_priority(unsigned int virq, unsigned int priority);
-int qe_ic_set_high_priority(unsigned int virq, unsigned int priority, int high);
-
#endif /* _ASM_POWERPC_QE_IC_H */
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 18/36] soc: fsl: qe: don't use NO_IRQ in qe_ic.c
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (16 preceding siblings ...)
2019-11-01 12:41 ` [PATCH v3 17/36] soc: fsl: qe: remove unused qe_ic_set_* functions Rasmus Villemoes
@ 2019-11-01 12:41 ` Rasmus Villemoes
2019-11-01 12:41 ` [PATCH v3 19/36] soc: fsl: qe: make qe_ic_get_{low,high}_irq static Rasmus Villemoes
` (17 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:41 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes
This driver is currently PPC-only, and on powerpc, NO_IRQ is 0, so
this doesn't change functionality. However, not every architecture
defines NO_IRQ, and some define it as -1, so the detection of a failed
irq_of_parse_and_map() (which returns 0 on failure) would be wrong on
those. So to prepare for allowing this driver to build on other
architectures, drop all references to NO_IRQ.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/soc/fsl/qe/qe_ic.c | 21 ++++++++++-----------
1 file changed, 10 insertions(+), 11 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index 4839dcd5c5d3..8f74bc6efd5c 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -282,7 +282,7 @@ static const struct irq_domain_ops qe_ic_host_ops = {
.xlate = irq_domain_xlate_onetwocell,
};
-/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
+/* Return an interrupt vector or 0 if no interrupt is pending. */
unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
{
int irq;
@@ -293,12 +293,12 @@ unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
irq = qe_ic_read(qe_ic->regs, QEIC_CIVEC) >> 26;
if (irq == 0)
- return NO_IRQ;
+ return 0;
return irq_linear_revmap(qe_ic->irqhost, irq);
}
-/* Return an interrupt vector or NO_IRQ if no interrupt is pending. */
+/* Return an interrupt vector or 0 if no interrupt is pending. */
unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
{
int irq;
@@ -309,7 +309,7 @@ unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
irq = qe_ic_read(qe_ic->regs, QEIC_CHIVEC) >> 26;
if (irq == 0)
- return NO_IRQ;
+ return 0;
return irq_linear_revmap(qe_ic->irqhost, irq);
}
@@ -320,7 +320,7 @@ static void qe_ic_cascade_low(struct irq_desc *desc)
unsigned int cascade_irq = qe_ic_get_low_irq(qe_ic);
struct irq_chip *chip = irq_desc_get_chip(desc);
- if (cascade_irq != NO_IRQ)
+ if (cascade_irq != 0)
generic_handle_irq(cascade_irq);
if (chip->irq_eoi)
@@ -333,7 +333,7 @@ static void qe_ic_cascade_high(struct irq_desc *desc)
unsigned int cascade_irq = qe_ic_get_high_irq(qe_ic);
struct irq_chip *chip = irq_desc_get_chip(desc);
- if (cascade_irq != NO_IRQ)
+ if (cascade_irq != 0)
generic_handle_irq(cascade_irq);
if (chip->irq_eoi)
@@ -347,10 +347,10 @@ static void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
struct irq_chip *chip = irq_desc_get_chip(desc);
cascade_irq = qe_ic_get_high_irq(qe_ic);
- if (cascade_irq == NO_IRQ)
+ if (cascade_irq == 0)
cascade_irq = qe_ic_get_low_irq(qe_ic);
- if (cascade_irq != NO_IRQ)
+ if (cascade_irq != 0)
generic_handle_irq(cascade_irq);
chip->irq_eoi(&desc->irq_data);
@@ -386,7 +386,7 @@ static void __init qe_ic_init(struct device_node *node, unsigned int flags)
qe_ic->virq_high = irq_of_parse_and_map(node, 0);
qe_ic->virq_low = irq_of_parse_and_map(node, 1);
- if (qe_ic->virq_low == NO_IRQ) {
+ if (!qe_ic->virq_low) {
printk(KERN_ERR "Failed to map QE_IC low IRQ\n");
kfree(qe_ic);
return;
@@ -423,8 +423,7 @@ static void __init qe_ic_init(struct device_node *node, unsigned int flags)
irq_set_handler_data(qe_ic->virq_low, qe_ic);
irq_set_chained_handler(qe_ic->virq_low, low_handler);
- if (qe_ic->virq_high != NO_IRQ &&
- qe_ic->virq_high != qe_ic->virq_low) {
+ if (qe_ic->virq_high && qe_ic->virq_high != qe_ic->virq_low) {
irq_set_handler_data(qe_ic->virq_high, qe_ic);
irq_set_chained_handler(qe_ic->virq_high, high_handler);
}
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 19/36] soc: fsl: qe: make qe_ic_get_{low,high}_irq static
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (17 preceding siblings ...)
2019-11-01 12:41 ` [PATCH v3 18/36] soc: fsl: qe: don't use NO_IRQ in qe_ic.c Rasmus Villemoes
@ 2019-11-01 12:41 ` Rasmus Villemoes
2019-11-01 12:41 ` [PATCH v3 20/36] soc: fsl: qe: simplify qe_ic_init() Rasmus Villemoes
` (16 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:41 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes
These are only called from within qe_ic.c, so make them static.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/soc/fsl/qe/qe_ic.c | 4 ++--
include/soc/fsl/qe/qe_ic.h | 10 ----------
2 files changed, 2 insertions(+), 12 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index 8f74bc6efd5c..23b457e884d8 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -283,7 +283,7 @@ static const struct irq_domain_ops qe_ic_host_ops = {
};
/* Return an interrupt vector or 0 if no interrupt is pending. */
-unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
+static unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
{
int irq;
@@ -299,7 +299,7 @@ unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
}
/* Return an interrupt vector or 0 if no interrupt is pending. */
-unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
+static unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
{
int irq;
diff --git a/include/soc/fsl/qe/qe_ic.h b/include/soc/fsl/qe/qe_ic.h
index d47eb231519e..70bb5a0f6535 100644
--- a/include/soc/fsl/qe/qe_ic.h
+++ b/include/soc/fsl/qe/qe_ic.h
@@ -53,14 +53,4 @@ enum qe_ic_grp_id {
QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */
};
-#ifdef CONFIG_QUICC_ENGINE
-unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic);
-unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic);
-#else
-static inline unsigned int qe_ic_get_low_irq(struct qe_ic *qe_ic)
-{ return 0; }
-static inline unsigned int qe_ic_get_high_irq(struct qe_ic *qe_ic)
-{ return 0; }
-#endif /* CONFIG_QUICC_ENGINE */
-
#endif /* _ASM_POWERPC_QE_IC_H */
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 20/36] soc: fsl: qe: simplify qe_ic_init()
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (18 preceding siblings ...)
2019-11-01 12:41 ` [PATCH v3 19/36] soc: fsl: qe: make qe_ic_get_{low,high}_irq static Rasmus Villemoes
@ 2019-11-01 12:41 ` Rasmus Villemoes
2019-11-01 12:41 ` [PATCH v3 21/36] soc: fsl: qe: merge qe_ic.h headers into qe_ic.c Rasmus Villemoes
` (15 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:41 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes
qe_ic_init() takes a flags parameter, but all callers (including the
sole remaining one) have always passed 0. So remove that parameter and
simplify the body accordingly. We still explicitly initialize the
Interrupt Configuration Register (CICR) to its reset value of
all-zeroes, just in case the bootloader has played funny games.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/soc/fsl/qe/qe_ic.c | 27 ++++-----------------------
1 file changed, 4 insertions(+), 23 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index 23b457e884d8..4832884da5bb 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -356,13 +356,13 @@ static void qe_ic_cascade_muxed_mpic(struct irq_desc *desc)
chip->irq_eoi(&desc->irq_data);
}
-static void __init qe_ic_init(struct device_node *node, unsigned int flags)
+static void __init qe_ic_init(struct device_node *node)
{
void (*low_handler)(struct irq_desc *desc);
void (*high_handler)(struct irq_desc *desc);
struct qe_ic *qe_ic;
struct resource res;
- u32 temp = 0, ret;
+ u32 ret;
ret = of_address_to_resource(node, 0, &res);
if (ret)
@@ -399,26 +399,7 @@ static void __init qe_ic_init(struct device_node *node, unsigned int flags)
high_handler = NULL;
}
- /* default priority scheme is grouped. If spread mode is */
- /* required, configure cicr accordingly. */
- if (flags & QE_IC_SPREADMODE_GRP_W)
- temp |= CICR_GWCC;
- if (flags & QE_IC_SPREADMODE_GRP_X)
- temp |= CICR_GXCC;
- if (flags & QE_IC_SPREADMODE_GRP_Y)
- temp |= CICR_GYCC;
- if (flags & QE_IC_SPREADMODE_GRP_Z)
- temp |= CICR_GZCC;
- if (flags & QE_IC_SPREADMODE_GRP_RISCA)
- temp |= CICR_GRTA;
- if (flags & QE_IC_SPREADMODE_GRP_RISCB)
- temp |= CICR_GRTB;
-
- /* choose destination signal for highest priority interrupt */
- if (flags & QE_IC_HIGH_SIGNAL)
- temp |= (SIGNAL_HIGH << CICR_HPIT_SHIFT);
-
- qe_ic_write(qe_ic->regs, QEIC_CICR, temp);
+ qe_ic_write(qe_ic->regs, QEIC_CICR, 0);
irq_set_handler_data(qe_ic->virq_low, qe_ic);
irq_set_chained_handler(qe_ic->virq_low, low_handler);
@@ -439,7 +420,7 @@ static int __init qe_ic_of_init(void)
if (!np)
return -ENODEV;
}
- qe_ic_init(np, 0);
+ qe_ic_init(np);
of_node_put(np);
return 0;
}
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 21/36] soc: fsl: qe: merge qe_ic.h headers into qe_ic.c
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (19 preceding siblings ...)
2019-11-01 12:41 ` [PATCH v3 20/36] soc: fsl: qe: simplify qe_ic_init() Rasmus Villemoes
@ 2019-11-01 12:41 ` Rasmus Villemoes
2019-11-01 12:41 ` [PATCH v3 22/36] soc: fsl: qe: qe.c: use of_property_read_* helpers Rasmus Villemoes
` (14 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:41 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes
The public qe_ic.h header is no longer included by anything but
qe_ic.c. Merge both headers into qe_ic.c, and drop the unused
constants.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/soc/fsl/qe/qe_ic.c | 52 +++++++++++++++++++-
drivers/soc/fsl/qe/qe_ic.h | 99 --------------------------------------
include/soc/fsl/qe/qe_ic.h | 56 ---------------------
3 files changed, 50 insertions(+), 157 deletions(-)
delete mode 100644 drivers/soc/fsl/qe/qe_ic.h
delete mode 100644 include/soc/fsl/qe/qe_ic.h
diff --git a/drivers/soc/fsl/qe/qe_ic.c b/drivers/soc/fsl/qe/qe_ic.c
index 4832884da5bb..0dd5bdb04a14 100644
--- a/drivers/soc/fsl/qe/qe_ic.c
+++ b/drivers/soc/fsl/qe/qe_ic.c
@@ -15,6 +15,7 @@
#include <linux/kernel.h>
#include <linux/init.h>
#include <linux/errno.h>
+#include <linux/irq.h>
#include <linux/reboot.h>
#include <linux/slab.h>
#include <linux/stddef.h>
@@ -25,9 +26,56 @@
#include <asm/irq.h>
#include <asm/io.h>
#include <soc/fsl/qe/qe.h>
-#include <soc/fsl/qe/qe_ic.h>
-#include "qe_ic.h"
+#define NR_QE_IC_INTS 64
+
+/* QE IC registers offset */
+#define QEIC_CICR 0x00
+#define QEIC_CIVEC 0x04
+#define QEIC_CIPXCC 0x10
+#define QEIC_CIPYCC 0x14
+#define QEIC_CIPWCC 0x18
+#define QEIC_CIPZCC 0x1c
+#define QEIC_CIMR 0x20
+#define QEIC_CRIMR 0x24
+#define QEIC_CIPRTA 0x30
+#define QEIC_CIPRTB 0x34
+#define QEIC_CHIVEC 0x60
+
+struct qe_ic {
+ /* Control registers offset */
+ u32 __iomem *regs;
+
+ /* The remapper for this QEIC */
+ struct irq_domain *irqhost;
+
+ /* The "linux" controller struct */
+ struct irq_chip hc_irq;
+
+ /* VIRQ numbers of QE high/low irqs */
+ unsigned int virq_high;
+ unsigned int virq_low;
+};
+
+/*
+ * QE interrupt controller internal structure
+ */
+struct qe_ic_info {
+ /* Location of this source at the QIMR register */
+ u32 mask;
+
+ /* Mask register offset */
+ u32 mask_reg;
+
+ /*
+ * For grouped interrupts sources - the interrupt code as
+ * appears at the group priority register
+ */
+ u8 pri_code;
+
+ /* Group priority register offset */
+ u32 pri_reg;
+};
static DEFINE_RAW_SPINLOCK(qe_ic_lock);
diff --git a/drivers/soc/fsl/qe/qe_ic.h b/drivers/soc/fsl/qe/qe_ic.h
deleted file mode 100644
index 9420378d9b6b..000000000000
--- a/drivers/soc/fsl/qe/qe_ic.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * drivers/soc/fsl/qe/qe_ic.h
- *
- * QUICC ENGINE Interrupt Controller Header
- *
- * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
- *
- * Author: Li Yang <leoli@freescale.com>
- * Based on code from Shlomi Gridish <gridish@freescale.com>
- */
-#ifndef _POWERPC_SYSDEV_QE_IC_H
-#define _POWERPC_SYSDEV_QE_IC_H
-
-#include <soc/fsl/qe/qe_ic.h>
-
-#define NR_QE_IC_INTS 64
-
-/* QE IC registers offset */
-#define QEIC_CICR 0x00
-#define QEIC_CIVEC 0x04
-#define QEIC_CRIPNR 0x08
-#define QEIC_CIPNR 0x0c
-#define QEIC_CIPXCC 0x10
-#define QEIC_CIPYCC 0x14
-#define QEIC_CIPWCC 0x18
-#define QEIC_CIPZCC 0x1c
-#define QEIC_CIMR 0x20
-#define QEIC_CRIMR 0x24
-#define QEIC_CICNR 0x28
-#define QEIC_CIPRTA 0x30
-#define QEIC_CIPRTB 0x34
-#define QEIC_CRICR 0x3c
-#define QEIC_CHIVEC 0x60
-
-/* Interrupt priority registers */
-#define CIPCC_SHIFT_PRI0 29
-#define CIPCC_SHIFT_PRI1 26
-#define CIPCC_SHIFT_PRI2 23
-#define CIPCC_SHIFT_PRI3 20
-#define CIPCC_SHIFT_PRI4 13
-#define CIPCC_SHIFT_PRI5 10
-#define CIPCC_SHIFT_PRI6 7
-#define CIPCC_SHIFT_PRI7 4
-
-/* CICR priority modes */
-#define CICR_GWCC 0x00040000
-#define CICR_GXCC 0x00020000
-#define CICR_GYCC 0x00010000
-#define CICR_GZCC 0x00080000
-#define CICR_GRTA 0x00200000
-#define CICR_GRTB 0x00400000
-#define CICR_HPIT_SHIFT 8
-#define CICR_HPIT_MASK 0x00000300
-#define CICR_HP_SHIFT 24
-#define CICR_HP_MASK 0x3f000000
-
-/* CICNR */
-#define CICNR_WCC1T_SHIFT 20
-#define CICNR_ZCC1T_SHIFT 28
-#define CICNR_YCC1T_SHIFT 12
-#define CICNR_XCC1T_SHIFT 4
-
-/* CRICR */
-#define CRICR_RTA1T_SHIFT 20
-#define CRICR_RTB1T_SHIFT 28
-
-/* Signal indicator */
-#define SIGNAL_MASK 3
-#define SIGNAL_HIGH 2
-#define SIGNAL_LOW 0
-
-struct qe_ic {
- /* Control registers offset */
- u32 __iomem *regs;
-
- /* The remapper for this QEIC */
- struct irq_domain *irqhost;
-
- /* The "linux" controller struct */
- struct irq_chip hc_irq;
-
- /* VIRQ numbers of QE high/low irqs */
- unsigned int virq_high;
- unsigned int virq_low;
-};
-
-/*
- * QE interrupt controller internal structure
- */
-struct qe_ic_info {
- u32 mask; /* location of this source at the QIMR register. */
- u32 mask_reg; /* Mask register offset */
- u8 pri_code; /* for grouped interrupts sources - the interrupt
- code as appears at the group priority register */
- u32 pri_reg; /* Group priority register offset */
-};
-
-#endif /* _POWERPC_SYSDEV_QE_IC_H */
diff --git a/include/soc/fsl/qe/qe_ic.h b/include/soc/fsl/qe/qe_ic.h
deleted file mode 100644
index 70bb5a0f6535..000000000000
--- a/include/soc/fsl/qe/qe_ic.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/* SPDX-License-Identifier: GPL-2.0-or-later */
-/*
- * Copyright (C) 2006 Freescale Semiconductor, Inc. All rights reserved.
- *
- * Authors: Shlomi Gridish <gridish@freescale.com>
- * Li Yang <leoli@freescale.com>
- *
- * Description:
- * QE IC external definitions and structure.
- */
-#ifndef _ASM_POWERPC_QE_IC_H
-#define _ASM_POWERPC_QE_IC_H
-
-#include <linux/irq.h>
-
-struct device_node;
-struct qe_ic;
-
-#define NUM_OF_QE_IC_GROUPS 6
-
-/* Flags when we init the QE IC */
-#define QE_IC_SPREADMODE_GRP_W 0x00000001
-#define QE_IC_SPREADMODE_GRP_X 0x00000002
-#define QE_IC_SPREADMODE_GRP_Y 0x00000004
-#define QE_IC_SPREADMODE_GRP_Z 0x00000008
-#define QE_IC_SPREADMODE_GRP_RISCA 0x00000010
-#define QE_IC_SPREADMODE_GRP_RISCB 0x00000020
-
-#define QE_IC_LOW_SIGNAL 0x00000100
-#define QE_IC_HIGH_SIGNAL 0x00000200
-
-#define QE_IC_GRP_W_PRI0_DEST_SIGNAL_HIGH 0x00001000
-#define QE_IC_GRP_W_PRI1_DEST_SIGNAL_HIGH 0x00002000
-#define QE_IC_GRP_X_PRI0_DEST_SIGNAL_HIGH 0x00004000
-#define QE_IC_GRP_X_PRI1_DEST_SIGNAL_HIGH 0x00008000
-#define QE_IC_GRP_Y_PRI0_DEST_SIGNAL_HIGH 0x00010000
-#define QE_IC_GRP_Y_PRI1_DEST_SIGNAL_HIGH 0x00020000
-#define QE_IC_GRP_Z_PRI0_DEST_SIGNAL_HIGH 0x00040000
-#define QE_IC_GRP_Z_PRI1_DEST_SIGNAL_HIGH 0x00080000
-#define QE_IC_GRP_RISCA_PRI0_DEST_SIGNAL_HIGH 0x00100000
-#define QE_IC_GRP_RISCA_PRI1_DEST_SIGNAL_HIGH 0x00200000
-#define QE_IC_GRP_RISCB_PRI0_DEST_SIGNAL_HIGH 0x00400000
-#define QE_IC_GRP_RISCB_PRI1_DEST_SIGNAL_HIGH 0x00800000
-#define QE_IC_GRP_W_DEST_SIGNAL_SHIFT (12)
-
-/* QE interrupt sources groups */
-enum qe_ic_grp_id {
- QE_IC_GRP_W = 0, /* QE interrupt controller group W */
- QE_IC_GRP_X, /* QE interrupt controller group X */
- QE_IC_GRP_Y, /* QE interrupt controller group Y */
- QE_IC_GRP_Z, /* QE interrupt controller group Z */
- QE_IC_GRP_RISCA, /* QE interrupt controller RISC group A */
- QE_IC_GRP_RISCB /* QE interrupt controller RISC group B */
-};
-
-#endif /* _ASM_POWERPC_QE_IC_H */
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 22/36] soc: fsl: qe: qe.c: use of_property_read_* helpers
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (20 preceding siblings ...)
2019-11-01 12:41 ` [PATCH v3 21/36] soc: fsl: qe: merge qe_ic.h headers into qe_ic.c Rasmus Villemoes
@ 2019-11-01 12:41 ` Rasmus Villemoes
2019-11-01 12:41 ` [PATCH v3 23/36] soc: fsl: qe: qe_io.c: don't open-code of_parse_phandle() Rasmus Villemoes
` (13 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:41 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes
Instead of manually doing of_get_property/of_find_property and reading
the value by assigning to a u32* or u64* and dereferencing, use the
of_property_read_* functions.
This make the code more readable, and more importantly, is required
for this to work correctly on little-endian platforms.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/soc/fsl/qe/qe.c | 33 ++++++++-------------------------
1 file changed, 8 insertions(+), 25 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe.c b/drivers/soc/fsl/qe/qe.c
index a4763282ea68..ec511840db3c 100644
--- a/drivers/soc/fsl/qe/qe.c
+++ b/drivers/soc/fsl/qe/qe.c
@@ -159,8 +159,7 @@ static unsigned int brg_clk = 0;
unsigned int qe_get_brg_clk(void)
{
struct device_node *qe;
- int size;
- const u32 *prop;
+ u32 brg;
unsigned int mod;
if (brg_clk)
@@ -170,9 +169,8 @@ unsigned int qe_get_brg_clk(void)
if (!qe)
return brg_clk;
- prop = of_get_property(qe, "brg-frequency", &size);
- if (prop && size == sizeof(*prop))
- brg_clk = *prop;
+ if (!of_property_read_u32(qe, "brg-frequency", &brg))
+ brg_clk = brg;
of_node_put(qe);
@@ -571,11 +569,9 @@ EXPORT_SYMBOL(qe_upload_firmware);
struct qe_firmware_info *qe_get_firmware_info(void)
{
static int initialized;
- struct property *prop;
struct device_node *qe;
struct device_node *fw = NULL;
const char *sprop;
- unsigned int i;
/*
* If we haven't checked yet, and a driver hasn't uploaded a firmware
@@ -609,20 +605,11 @@ struct qe_firmware_info *qe_get_firmware_info(void)
strlcpy(qe_firmware_info.id, sprop,
sizeof(qe_firmware_info.id));
- prop = of_find_property(fw, "extended-modes", NULL);
- if (prop && (prop->length == sizeof(u64))) {
- const u64 *iprop = prop->value;
-
- qe_firmware_info.extended_modes = *iprop;
- }
+ of_property_read_u64(fw, "extended-modes",
+ &qe_firmware_info.extended_modes);
- prop = of_find_property(fw, "virtual-traps", NULL);
- if (prop && (prop->length == 32)) {
- const u32 *iprop = prop->value;
-
- for (i = 0; i < ARRAY_SIZE(qe_firmware_info.vtraps); i++)
- qe_firmware_info.vtraps[i] = iprop[i];
- }
+ of_property_read_u32_array(fw, "virtual-traps", qe_firmware_info.vtraps,
+ ARRAY_SIZE(qe_firmware_info.vtraps));
of_node_put(fw);
@@ -633,17 +620,13 @@ EXPORT_SYMBOL(qe_get_firmware_info);
unsigned int qe_get_num_of_risc(void)
{
struct device_node *qe;
- int size;
unsigned int num_of_risc = 0;
- const u32 *prop;
qe = qe_get_device_node();
if (!qe)
return num_of_risc;
- prop = of_get_property(qe, "fsl,qe-num-riscs", &size);
- if (prop && size == sizeof(*prop))
- num_of_risc = *prop;
+ of_property_read_u32(qe, "fsl,qe-num-riscs", &num_of_risc);
of_node_put(qe);
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 23/36] soc: fsl: qe: qe_io.c: don't open-code of_parse_phandle()
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (21 preceding siblings ...)
2019-11-01 12:41 ` [PATCH v3 22/36] soc: fsl: qe: qe.c: use of_property_read_* helpers Rasmus Villemoes
@ 2019-11-01 12:41 ` Rasmus Villemoes
2019-11-01 12:41 ` [PATCH v3 24/36] soc: fsl: qe: qe_io.c: access device tree property using be32_to_cpu Rasmus Villemoes
` (12 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:41 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/soc/fsl/qe/qe_io.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe_io.c b/drivers/soc/fsl/qe/qe_io.c
index f6b10f38b2f4..99aeb01586bd 100644
--- a/drivers/soc/fsl/qe/qe_io.c
+++ b/drivers/soc/fsl/qe/qe_io.c
@@ -141,7 +141,6 @@ EXPORT_SYMBOL(par_io_data_set);
int par_io_of_config(struct device_node *np)
{
struct device_node *pio;
- const phandle *ph;
int pio_map_len;
const unsigned int *pio_map;
@@ -150,14 +149,12 @@ int par_io_of_config(struct device_node *np)
return -1;
}
- ph = of_get_property(np, "pio-handle", NULL);
- if (ph == NULL) {
+ pio = of_parse_phandle(np, "pio-handle", 0);
+ if (pio == NULL) {
printk(KERN_ERR "pio-handle not available\n");
return -1;
}
- pio = of_find_node_by_phandle(*ph);
-
pio_map = of_get_property(pio, "pio-map", &pio_map_len);
if (pio_map == NULL) {
printk(KERN_ERR "pio-map is not set!\n");
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 24/36] soc: fsl: qe: qe_io.c: access device tree property using be32_to_cpu
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (22 preceding siblings ...)
2019-11-01 12:41 ` [PATCH v3 23/36] soc: fsl: qe: qe_io.c: don't open-code of_parse_phandle() Rasmus Villemoes
@ 2019-11-01 12:41 ` Rasmus Villemoes
2019-11-01 12:41 ` [PATCH v3 25/36] soc: fsl: qe: qe_io.c: use of_property_read_u32() in par_io_init() Rasmus Villemoes
` (11 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:41 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes
We need to apply be32_to_cpu to make this work correctly on
little-endian hosts.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/soc/fsl/qe/qe_io.c | 14 ++++++++++----
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe_io.c b/drivers/soc/fsl/qe/qe_io.c
index 99aeb01586bd..61dd8eb8c0fe 100644
--- a/drivers/soc/fsl/qe/qe_io.c
+++ b/drivers/soc/fsl/qe/qe_io.c
@@ -142,7 +142,7 @@ int par_io_of_config(struct device_node *np)
{
struct device_node *pio;
int pio_map_len;
- const unsigned int *pio_map;
+ const __be32 *pio_map;
if (par_io == NULL) {
printk(KERN_ERR "par_io not initialized\n");
@@ -167,9 +167,15 @@ int par_io_of_config(struct device_node *np)
}
while (pio_map_len > 0) {
- par_io_config_pin((u8) pio_map[0], (u8) pio_map[1],
- (int) pio_map[2], (int) pio_map[3],
- (int) pio_map[4], (int) pio_map[5]);
+ u8 port = be32_to_cpu(pio_map[0]);
+ u8 pin = be32_to_cpu(pio_map[1]);
+ int dir = be32_to_cpu(pio_map[2]);
+ int open_drain = be32_to_cpu(pio_map[3]);
+ int assignment = be32_to_cpu(pio_map[4]);
+ int has_irq = be32_to_cpu(pio_map[5]);
+
+ par_io_config_pin(port, pin, dir, open_drain,
+ assignment, has_irq);
pio_map += 6;
pio_map_len -= 6;
}
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 25/36] soc: fsl: qe: qe_io.c: use of_property_read_u32() in par_io_init()
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (23 preceding siblings ...)
2019-11-01 12:41 ` [PATCH v3 24/36] soc: fsl: qe: qe_io.c: access device tree property using be32_to_cpu Rasmus Villemoes
@ 2019-11-01 12:41 ` Rasmus Villemoes
2019-11-01 12:42 ` [PATCH v3 26/36] soc: fsl: move cpm.h from powerpc/include/asm to include/soc/fsl Rasmus Villemoes
` (10 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:41 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes
This is necessary for this to work on little-endian hosts.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/soc/fsl/qe/qe_io.c | 7 +++----
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/drivers/soc/fsl/qe/qe_io.c b/drivers/soc/fsl/qe/qe_io.c
index 61dd8eb8c0fe..11ea08e97db7 100644
--- a/drivers/soc/fsl/qe/qe_io.c
+++ b/drivers/soc/fsl/qe/qe_io.c
@@ -28,7 +28,7 @@ int par_io_init(struct device_node *np)
{
struct resource res;
int ret;
- const u32 *num_ports;
+ u32 num_ports;
/* Map Parallel I/O ports registers */
ret = of_address_to_resource(np, 0, &res);
@@ -36,9 +36,8 @@ int par_io_init(struct device_node *np)
return ret;
par_io = ioremap(res.start, resource_size(&res));
- num_ports = of_get_property(np, "num-ports", NULL);
- if (num_ports)
- num_par_io_ports = *num_ports;
+ if (!of_property_read_u32(np, "num-ports", &num_ports))
+ num_par_io_ports = num_ports;
return 0;
}
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 26/36] soc: fsl: move cpm.h from powerpc/include/asm to include/soc/fsl
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (24 preceding siblings ...)
2019-11-01 12:41 ` [PATCH v3 25/36] soc: fsl: qe: qe_io.c: use of_property_read_u32() in par_io_init() Rasmus Villemoes
@ 2019-11-01 12:42 ` Rasmus Villemoes
2019-11-01 16:18 ` Christophe Leroy
2019-11-01 12:42 ` [PATCH v3 27/36] soc/fsl/qe/qe.h: update include path for cpm.h Rasmus Villemoes
` (9 subsequent siblings)
35 siblings, 1 reply; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:42 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes
Some drivers, e.g. ucc_uart, need definitions from cpm.h. In order to
allow building those drivers for non-ppc based SOCs, move the header
to include/soc/fsl. For now, leave a trivial wrapper at the old
location so drivers can be updated one by one.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
arch/powerpc/include/asm/cpm.h | 172 +--------------------------------
include/soc/fsl/cpm.h | 171 ++++++++++++++++++++++++++++++++
2 files changed, 172 insertions(+), 171 deletions(-)
create mode 100644 include/soc/fsl/cpm.h
diff --git a/arch/powerpc/include/asm/cpm.h b/arch/powerpc/include/asm/cpm.h
index 4c24ea8209bb..ce483b0f8a4d 100644
--- a/arch/powerpc/include/asm/cpm.h
+++ b/arch/powerpc/include/asm/cpm.h
@@ -1,171 +1 @@
-/* SPDX-License-Identifier: GPL-2.0 */
-#ifndef __CPM_H
-#define __CPM_H
-
-#include <linux/compiler.h>
-#include <linux/types.h>
-#include <linux/errno.h>
-#include <linux/of.h>
-#include <soc/fsl/qe/qe.h>
-
-/*
- * SPI Parameter RAM common to QE and CPM.
- */
-struct spi_pram {
- __be16 rbase; /* Rx Buffer descriptor base address */
- __be16 tbase; /* Tx Buffer descriptor base address */
- u8 rfcr; /* Rx function code */
- u8 tfcr; /* Tx function code */
- __be16 mrblr; /* Max receive buffer length */
- __be32 rstate; /* Internal */
- __be32 rdp; /* Internal */
- __be16 rbptr; /* Internal */
- __be16 rbc; /* Internal */
- __be32 rxtmp; /* Internal */
- __be32 tstate; /* Internal */
- __be32 tdp; /* Internal */
- __be16 tbptr; /* Internal */
- __be16 tbc; /* Internal */
- __be32 txtmp; /* Internal */
- __be32 res; /* Tx temp. */
- __be16 rpbase; /* Relocation pointer (CPM1 only) */
- __be16 res1; /* Reserved */
-};
-
-/*
- * USB Controller pram common to QE and CPM.
- */
-struct usb_ctlr {
- u8 usb_usmod;
- u8 usb_usadr;
- u8 usb_uscom;
- u8 res1[1];
- __be16 usb_usep[4];
- u8 res2[4];
- __be16 usb_usber;
- u8 res3[2];
- __be16 usb_usbmr;
- u8 res4[1];
- u8 usb_usbs;
- /* Fields down below are QE-only */
- __be16 usb_ussft;
- u8 res5[2];
- __be16 usb_usfrn;
- u8 res6[0x22];
-} __attribute__ ((packed));
-
-/*
- * Function code bits, usually generic to devices.
- */
-#ifdef CONFIG_CPM1
-#define CPMFCR_GBL ((u_char)0x00) /* Flag doesn't exist in CPM1 */
-#define CPMFCR_TC2 ((u_char)0x00) /* Flag doesn't exist in CPM1 */
-#define CPMFCR_DTB ((u_char)0x00) /* Flag doesn't exist in CPM1 */
-#define CPMFCR_BDB ((u_char)0x00) /* Flag doesn't exist in CPM1 */
-#else
-#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
-#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
-#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
-#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
-#endif
-#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
-
-/* Opcodes common to CPM1 and CPM2
-*/
-#define CPM_CR_INIT_TRX ((ushort)0x0000)
-#define CPM_CR_INIT_RX ((ushort)0x0001)
-#define CPM_CR_INIT_TX ((ushort)0x0002)
-#define CPM_CR_HUNT_MODE ((ushort)0x0003)
-#define CPM_CR_STOP_TX ((ushort)0x0004)
-#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
-#define CPM_CR_RESTART_TX ((ushort)0x0006)
-#define CPM_CR_CLOSE_RX_BD ((ushort)0x0007)
-#define CPM_CR_SET_GADDR ((ushort)0x0008)
-#define CPM_CR_SET_TIMER ((ushort)0x0008)
-#define CPM_CR_STOP_IDMA ((ushort)0x000b)
-
-/* Buffer descriptors used by many of the CPM protocols. */
-typedef struct cpm_buf_desc {
- ushort cbd_sc; /* Status and Control */
- ushort cbd_datlen; /* Data length in buffer */
- uint cbd_bufaddr; /* Buffer address in host memory */
-} cbd_t;
-
-/* Buffer descriptor control/status used by serial
- */
-
-#define BD_SC_EMPTY (0x8000) /* Receive is empty */
-#define BD_SC_READY (0x8000) /* Transmit is ready */
-#define BD_SC_WRAP (0x2000) /* Last buffer descriptor */
-#define BD_SC_INTRPT (0x1000) /* Interrupt on change */
-#define BD_SC_LAST (0x0800) /* Last buffer in frame */
-#define BD_SC_TC (0x0400) /* Transmit CRC */
-#define BD_SC_CM (0x0200) /* Continuous mode */
-#define BD_SC_ID (0x0100) /* Rec'd too many idles */
-#define BD_SC_P (0x0100) /* xmt preamble */
-#define BD_SC_BR (0x0020) /* Break received */
-#define BD_SC_FR (0x0010) /* Framing error */
-#define BD_SC_PR (0x0008) /* Parity error */
-#define BD_SC_NAK (0x0004) /* NAK - did not respond */
-#define BD_SC_OV (0x0002) /* Overrun */
-#define BD_SC_UN (0x0002) /* Underrun */
-#define BD_SC_CD (0x0001) /* */
-#define BD_SC_CL (0x0001) /* Collision */
-
-/* Buffer descriptor control/status used by Ethernet receive.
- * Common to SCC and FCC.
- */
-#define BD_ENET_RX_EMPTY (0x8000)
-#define BD_ENET_RX_WRAP (0x2000)
-#define BD_ENET_RX_INTR (0x1000)
-#define BD_ENET_RX_LAST (0x0800)
-#define BD_ENET_RX_FIRST (0x0400)
-#define BD_ENET_RX_MISS (0x0100)
-#define BD_ENET_RX_BC (0x0080) /* FCC Only */
-#define BD_ENET_RX_MC (0x0040) /* FCC Only */
-#define BD_ENET_RX_LG (0x0020)
-#define BD_ENET_RX_NO (0x0010)
-#define BD_ENET_RX_SH (0x0008)
-#define BD_ENET_RX_CR (0x0004)
-#define BD_ENET_RX_OV (0x0002)
-#define BD_ENET_RX_CL (0x0001)
-#define BD_ENET_RX_STATS (0x01ff) /* All status bits */
-
-/* Buffer descriptor control/status used by Ethernet transmit.
- * Common to SCC and FCC.
- */
-#define BD_ENET_TX_READY (0x8000)
-#define BD_ENET_TX_PAD (0x4000)
-#define BD_ENET_TX_WRAP (0x2000)
-#define BD_ENET_TX_INTR (0x1000)
-#define BD_ENET_TX_LAST (0x0800)
-#define BD_ENET_TX_TC (0x0400)
-#define BD_ENET_TX_DEF (0x0200)
-#define BD_ENET_TX_HB (0x0100)
-#define BD_ENET_TX_LC (0x0080)
-#define BD_ENET_TX_RL (0x0040)
-#define BD_ENET_TX_RCMASK (0x003c)
-#define BD_ENET_TX_UN (0x0002)
-#define BD_ENET_TX_CSL (0x0001)
-#define BD_ENET_TX_STATS (0x03ff) /* All status bits */
-
-/* Buffer descriptor control/status used by Transparent mode SCC.
- */
-#define BD_SCC_TX_LAST (0x0800)
-
-/* Buffer descriptor control/status used by I2C.
- */
-#define BD_I2C_START (0x0400)
-
-#ifdef CONFIG_CPM
-int cpm_command(u32 command, u8 opcode);
-#else
-static inline int cpm_command(u32 command, u8 opcode)
-{
- return -ENOSYS;
-}
-#endif /* CONFIG_CPM */
-
-int cpm2_gpiochip_add32(struct device *dev);
-
-#endif
+#include <soc/fsl/cpm.h>
diff --git a/include/soc/fsl/cpm.h b/include/soc/fsl/cpm.h
new file mode 100644
index 000000000000..4c24ea8209bb
--- /dev/null
+++ b/include/soc/fsl/cpm.h
@@ -0,0 +1,171 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __CPM_H
+#define __CPM_H
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <linux/errno.h>
+#include <linux/of.h>
+#include <soc/fsl/qe/qe.h>
+
+/*
+ * SPI Parameter RAM common to QE and CPM.
+ */
+struct spi_pram {
+ __be16 rbase; /* Rx Buffer descriptor base address */
+ __be16 tbase; /* Tx Buffer descriptor base address */
+ u8 rfcr; /* Rx function code */
+ u8 tfcr; /* Tx function code */
+ __be16 mrblr; /* Max receive buffer length */
+ __be32 rstate; /* Internal */
+ __be32 rdp; /* Internal */
+ __be16 rbptr; /* Internal */
+ __be16 rbc; /* Internal */
+ __be32 rxtmp; /* Internal */
+ __be32 tstate; /* Internal */
+ __be32 tdp; /* Internal */
+ __be16 tbptr; /* Internal */
+ __be16 tbc; /* Internal */
+ __be32 txtmp; /* Internal */
+ __be32 res; /* Tx temp. */
+ __be16 rpbase; /* Relocation pointer (CPM1 only) */
+ __be16 res1; /* Reserved */
+};
+
+/*
+ * USB Controller pram common to QE and CPM.
+ */
+struct usb_ctlr {
+ u8 usb_usmod;
+ u8 usb_usadr;
+ u8 usb_uscom;
+ u8 res1[1];
+ __be16 usb_usep[4];
+ u8 res2[4];
+ __be16 usb_usber;
+ u8 res3[2];
+ __be16 usb_usbmr;
+ u8 res4[1];
+ u8 usb_usbs;
+ /* Fields down below are QE-only */
+ __be16 usb_ussft;
+ u8 res5[2];
+ __be16 usb_usfrn;
+ u8 res6[0x22];
+} __attribute__ ((packed));
+
+/*
+ * Function code bits, usually generic to devices.
+ */
+#ifdef CONFIG_CPM1
+#define CPMFCR_GBL ((u_char)0x00) /* Flag doesn't exist in CPM1 */
+#define CPMFCR_TC2 ((u_char)0x00) /* Flag doesn't exist in CPM1 */
+#define CPMFCR_DTB ((u_char)0x00) /* Flag doesn't exist in CPM1 */
+#define CPMFCR_BDB ((u_char)0x00) /* Flag doesn't exist in CPM1 */
+#else
+#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
+#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
+#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
+#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
+#endif
+#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
+
+/* Opcodes common to CPM1 and CPM2
+*/
+#define CPM_CR_INIT_TRX ((ushort)0x0000)
+#define CPM_CR_INIT_RX ((ushort)0x0001)
+#define CPM_CR_INIT_TX ((ushort)0x0002)
+#define CPM_CR_HUNT_MODE ((ushort)0x0003)
+#define CPM_CR_STOP_TX ((ushort)0x0004)
+#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
+#define CPM_CR_RESTART_TX ((ushort)0x0006)
+#define CPM_CR_CLOSE_RX_BD ((ushort)0x0007)
+#define CPM_CR_SET_GADDR ((ushort)0x0008)
+#define CPM_CR_SET_TIMER ((ushort)0x0008)
+#define CPM_CR_STOP_IDMA ((ushort)0x000b)
+
+/* Buffer descriptors used by many of the CPM protocols. */
+typedef struct cpm_buf_desc {
+ ushort cbd_sc; /* Status and Control */
+ ushort cbd_datlen; /* Data length in buffer */
+ uint cbd_bufaddr; /* Buffer address in host memory */
+} cbd_t;
+
+/* Buffer descriptor control/status used by serial
+ */
+
+#define BD_SC_EMPTY (0x8000) /* Receive is empty */
+#define BD_SC_READY (0x8000) /* Transmit is ready */
+#define BD_SC_WRAP (0x2000) /* Last buffer descriptor */
+#define BD_SC_INTRPT (0x1000) /* Interrupt on change */
+#define BD_SC_LAST (0x0800) /* Last buffer in frame */
+#define BD_SC_TC (0x0400) /* Transmit CRC */
+#define BD_SC_CM (0x0200) /* Continuous mode */
+#define BD_SC_ID (0x0100) /* Rec'd too many idles */
+#define BD_SC_P (0x0100) /* xmt preamble */
+#define BD_SC_BR (0x0020) /* Break received */
+#define BD_SC_FR (0x0010) /* Framing error */
+#define BD_SC_PR (0x0008) /* Parity error */
+#define BD_SC_NAK (0x0004) /* NAK - did not respond */
+#define BD_SC_OV (0x0002) /* Overrun */
+#define BD_SC_UN (0x0002) /* Underrun */
+#define BD_SC_CD (0x0001) /* */
+#define BD_SC_CL (0x0001) /* Collision */
+
+/* Buffer descriptor control/status used by Ethernet receive.
+ * Common to SCC and FCC.
+ */
+#define BD_ENET_RX_EMPTY (0x8000)
+#define BD_ENET_RX_WRAP (0x2000)
+#define BD_ENET_RX_INTR (0x1000)
+#define BD_ENET_RX_LAST (0x0800)
+#define BD_ENET_RX_FIRST (0x0400)
+#define BD_ENET_RX_MISS (0x0100)
+#define BD_ENET_RX_BC (0x0080) /* FCC Only */
+#define BD_ENET_RX_MC (0x0040) /* FCC Only */
+#define BD_ENET_RX_LG (0x0020)
+#define BD_ENET_RX_NO (0x0010)
+#define BD_ENET_RX_SH (0x0008)
+#define BD_ENET_RX_CR (0x0004)
+#define BD_ENET_RX_OV (0x0002)
+#define BD_ENET_RX_CL (0x0001)
+#define BD_ENET_RX_STATS (0x01ff) /* All status bits */
+
+/* Buffer descriptor control/status used by Ethernet transmit.
+ * Common to SCC and FCC.
+ */
+#define BD_ENET_TX_READY (0x8000)
+#define BD_ENET_TX_PAD (0x4000)
+#define BD_ENET_TX_WRAP (0x2000)
+#define BD_ENET_TX_INTR (0x1000)
+#define BD_ENET_TX_LAST (0x0800)
+#define BD_ENET_TX_TC (0x0400)
+#define BD_ENET_TX_DEF (0x0200)
+#define BD_ENET_TX_HB (0x0100)
+#define BD_ENET_TX_LC (0x0080)
+#define BD_ENET_TX_RL (0x0040)
+#define BD_ENET_TX_RCMASK (0x003c)
+#define BD_ENET_TX_UN (0x0002)
+#define BD_ENET_TX_CSL (0x0001)
+#define BD_ENET_TX_STATS (0x03ff) /* All status bits */
+
+/* Buffer descriptor control/status used by Transparent mode SCC.
+ */
+#define BD_SCC_TX_LAST (0x0800)
+
+/* Buffer descriptor control/status used by I2C.
+ */
+#define BD_I2C_START (0x0400)
+
+#ifdef CONFIG_CPM
+int cpm_command(u32 command, u8 opcode);
+#else
+static inline int cpm_command(u32 command, u8 opcode)
+{
+ return -ENOSYS;
+}
+#endif /* CONFIG_CPM */
+
+int cpm2_gpiochip_add32(struct device *dev);
+
+#endif
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* Re: [PATCH v3 26/36] soc: fsl: move cpm.h from powerpc/include/asm to include/soc/fsl
2019-11-01 12:42 ` [PATCH v3 26/36] soc: fsl: move cpm.h from powerpc/include/asm to include/soc/fsl Rasmus Villemoes
@ 2019-11-01 16:18 ` Christophe Leroy
2019-11-01 16:59 ` Scott Wood
0 siblings, 1 reply; 120+ messages in thread
From: Christophe Leroy @ 2019-11-01 16:18 UTC (permalink / raw)
To: Rasmus Villemoes, Qiang Zhao, Li Yang
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood
Le 01/11/2019 à 13:42, Rasmus Villemoes a écrit :
> Some drivers, e.g. ucc_uart, need definitions from cpm.h. In order to
> allow building those drivers for non-ppc based SOCs, move the header
> to include/soc/fsl. For now, leave a trivial wrapper at the old
> location so drivers can be updated one by one.
I'm not sure that's the correct way to go.
As far as I know, CPM is specific to powerpc (or maybe common to some
motorola 68000). So only powerpc specific drivers should need it.
If cpm.h includes items that are needed for QE, those items should go in
another .h
Of course, it doesn't mean we can't move cpm.h in include/soc/fsl, but
anyway only platforms having CPM1 or CPM2 should include it.
Christophe
>
> Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
> ---
> arch/powerpc/include/asm/cpm.h | 172 +--------------------------------
> include/soc/fsl/cpm.h | 171 ++++++++++++++++++++++++++++++++
> 2 files changed, 172 insertions(+), 171 deletions(-)
> create mode 100644 include/soc/fsl/cpm.h
>
> diff --git a/arch/powerpc/include/asm/cpm.h b/arch/powerpc/include/asm/cpm.h
> index 4c24ea8209bb..ce483b0f8a4d 100644
> --- a/arch/powerpc/include/asm/cpm.h
> +++ b/arch/powerpc/include/asm/cpm.h
> @@ -1,171 +1 @@
> -/* SPDX-License-Identifier: GPL-2.0 */
> -#ifndef __CPM_H
> -#define __CPM_H
> -
> -#include <linux/compiler.h>
> -#include <linux/types.h>
> -#include <linux/errno.h>
> -#include <linux/of.h>
> -#include <soc/fsl/qe/qe.h>
> -
> -/*
> - * SPI Parameter RAM common to QE and CPM.
> - */
> -struct spi_pram {
> - __be16 rbase; /* Rx Buffer descriptor base address */
> - __be16 tbase; /* Tx Buffer descriptor base address */
> - u8 rfcr; /* Rx function code */
> - u8 tfcr; /* Tx function code */
> - __be16 mrblr; /* Max receive buffer length */
> - __be32 rstate; /* Internal */
> - __be32 rdp; /* Internal */
> - __be16 rbptr; /* Internal */
> - __be16 rbc; /* Internal */
> - __be32 rxtmp; /* Internal */
> - __be32 tstate; /* Internal */
> - __be32 tdp; /* Internal */
> - __be16 tbptr; /* Internal */
> - __be16 tbc; /* Internal */
> - __be32 txtmp; /* Internal */
> - __be32 res; /* Tx temp. */
> - __be16 rpbase; /* Relocation pointer (CPM1 only) */
> - __be16 res1; /* Reserved */
> -};
> -
> -/*
> - * USB Controller pram common to QE and CPM.
> - */
> -struct usb_ctlr {
> - u8 usb_usmod;
> - u8 usb_usadr;
> - u8 usb_uscom;
> - u8 res1[1];
> - __be16 usb_usep[4];
> - u8 res2[4];
> - __be16 usb_usber;
> - u8 res3[2];
> - __be16 usb_usbmr;
> - u8 res4[1];
> - u8 usb_usbs;
> - /* Fields down below are QE-only */
> - __be16 usb_ussft;
> - u8 res5[2];
> - __be16 usb_usfrn;
> - u8 res6[0x22];
> -} __attribute__ ((packed));
> -
> -/*
> - * Function code bits, usually generic to devices.
> - */
> -#ifdef CONFIG_CPM1
> -#define CPMFCR_GBL ((u_char)0x00) /* Flag doesn't exist in CPM1 */
> -#define CPMFCR_TC2 ((u_char)0x00) /* Flag doesn't exist in CPM1 */
> -#define CPMFCR_DTB ((u_char)0x00) /* Flag doesn't exist in CPM1 */
> -#define CPMFCR_BDB ((u_char)0x00) /* Flag doesn't exist in CPM1 */
> -#else
> -#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
> -#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
> -#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
> -#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
> -#endif
> -#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
> -
> -/* Opcodes common to CPM1 and CPM2
> -*/
> -#define CPM_CR_INIT_TRX ((ushort)0x0000)
> -#define CPM_CR_INIT_RX ((ushort)0x0001)
> -#define CPM_CR_INIT_TX ((ushort)0x0002)
> -#define CPM_CR_HUNT_MODE ((ushort)0x0003)
> -#define CPM_CR_STOP_TX ((ushort)0x0004)
> -#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
> -#define CPM_CR_RESTART_TX ((ushort)0x0006)
> -#define CPM_CR_CLOSE_RX_BD ((ushort)0x0007)
> -#define CPM_CR_SET_GADDR ((ushort)0x0008)
> -#define CPM_CR_SET_TIMER ((ushort)0x0008)
> -#define CPM_CR_STOP_IDMA ((ushort)0x000b)
> -
> -/* Buffer descriptors used by many of the CPM protocols. */
> -typedef struct cpm_buf_desc {
> - ushort cbd_sc; /* Status and Control */
> - ushort cbd_datlen; /* Data length in buffer */
> - uint cbd_bufaddr; /* Buffer address in host memory */
> -} cbd_t;
> -
> -/* Buffer descriptor control/status used by serial
> - */
> -
> -#define BD_SC_EMPTY (0x8000) /* Receive is empty */
> -#define BD_SC_READY (0x8000) /* Transmit is ready */
> -#define BD_SC_WRAP (0x2000) /* Last buffer descriptor */
> -#define BD_SC_INTRPT (0x1000) /* Interrupt on change */
> -#define BD_SC_LAST (0x0800) /* Last buffer in frame */
> -#define BD_SC_TC (0x0400) /* Transmit CRC */
> -#define BD_SC_CM (0x0200) /* Continuous mode */
> -#define BD_SC_ID (0x0100) /* Rec'd too many idles */
> -#define BD_SC_P (0x0100) /* xmt preamble */
> -#define BD_SC_BR (0x0020) /* Break received */
> -#define BD_SC_FR (0x0010) /* Framing error */
> -#define BD_SC_PR (0x0008) /* Parity error */
> -#define BD_SC_NAK (0x0004) /* NAK - did not respond */
> -#define BD_SC_OV (0x0002) /* Overrun */
> -#define BD_SC_UN (0x0002) /* Underrun */
> -#define BD_SC_CD (0x0001) /* */
> -#define BD_SC_CL (0x0001) /* Collision */
> -
> -/* Buffer descriptor control/status used by Ethernet receive.
> - * Common to SCC and FCC.
> - */
> -#define BD_ENET_RX_EMPTY (0x8000)
> -#define BD_ENET_RX_WRAP (0x2000)
> -#define BD_ENET_RX_INTR (0x1000)
> -#define BD_ENET_RX_LAST (0x0800)
> -#define BD_ENET_RX_FIRST (0x0400)
> -#define BD_ENET_RX_MISS (0x0100)
> -#define BD_ENET_RX_BC (0x0080) /* FCC Only */
> -#define BD_ENET_RX_MC (0x0040) /* FCC Only */
> -#define BD_ENET_RX_LG (0x0020)
> -#define BD_ENET_RX_NO (0x0010)
> -#define BD_ENET_RX_SH (0x0008)
> -#define BD_ENET_RX_CR (0x0004)
> -#define BD_ENET_RX_OV (0x0002)
> -#define BD_ENET_RX_CL (0x0001)
> -#define BD_ENET_RX_STATS (0x01ff) /* All status bits */
> -
> -/* Buffer descriptor control/status used by Ethernet transmit.
> - * Common to SCC and FCC.
> - */
> -#define BD_ENET_TX_READY (0x8000)
> -#define BD_ENET_TX_PAD (0x4000)
> -#define BD_ENET_TX_WRAP (0x2000)
> -#define BD_ENET_TX_INTR (0x1000)
> -#define BD_ENET_TX_LAST (0x0800)
> -#define BD_ENET_TX_TC (0x0400)
> -#define BD_ENET_TX_DEF (0x0200)
> -#define BD_ENET_TX_HB (0x0100)
> -#define BD_ENET_TX_LC (0x0080)
> -#define BD_ENET_TX_RL (0x0040)
> -#define BD_ENET_TX_RCMASK (0x003c)
> -#define BD_ENET_TX_UN (0x0002)
> -#define BD_ENET_TX_CSL (0x0001)
> -#define BD_ENET_TX_STATS (0x03ff) /* All status bits */
> -
> -/* Buffer descriptor control/status used by Transparent mode SCC.
> - */
> -#define BD_SCC_TX_LAST (0x0800)
> -
> -/* Buffer descriptor control/status used by I2C.
> - */
> -#define BD_I2C_START (0x0400)
> -
> -#ifdef CONFIG_CPM
> -int cpm_command(u32 command, u8 opcode);
> -#else
> -static inline int cpm_command(u32 command, u8 opcode)
> -{
> - return -ENOSYS;
> -}
> -#endif /* CONFIG_CPM */
> -
> -int cpm2_gpiochip_add32(struct device *dev);
> -
> -#endif
> +#include <soc/fsl/cpm.h>
> diff --git a/include/soc/fsl/cpm.h b/include/soc/fsl/cpm.h
> new file mode 100644
> index 000000000000..4c24ea8209bb
> --- /dev/null
> +++ b/include/soc/fsl/cpm.h
> @@ -0,0 +1,171 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef __CPM_H
> +#define __CPM_H
> +
> +#include <linux/compiler.h>
> +#include <linux/types.h>
> +#include <linux/errno.h>
> +#include <linux/of.h>
> +#include <soc/fsl/qe/qe.h>
> +
> +/*
> + * SPI Parameter RAM common to QE and CPM.
> + */
> +struct spi_pram {
> + __be16 rbase; /* Rx Buffer descriptor base address */
> + __be16 tbase; /* Tx Buffer descriptor base address */
> + u8 rfcr; /* Rx function code */
> + u8 tfcr; /* Tx function code */
> + __be16 mrblr; /* Max receive buffer length */
> + __be32 rstate; /* Internal */
> + __be32 rdp; /* Internal */
> + __be16 rbptr; /* Internal */
> + __be16 rbc; /* Internal */
> + __be32 rxtmp; /* Internal */
> + __be32 tstate; /* Internal */
> + __be32 tdp; /* Internal */
> + __be16 tbptr; /* Internal */
> + __be16 tbc; /* Internal */
> + __be32 txtmp; /* Internal */
> + __be32 res; /* Tx temp. */
> + __be16 rpbase; /* Relocation pointer (CPM1 only) */
> + __be16 res1; /* Reserved */
> +};
> +
> +/*
> + * USB Controller pram common to QE and CPM.
> + */
> +struct usb_ctlr {
> + u8 usb_usmod;
> + u8 usb_usadr;
> + u8 usb_uscom;
> + u8 res1[1];
> + __be16 usb_usep[4];
> + u8 res2[4];
> + __be16 usb_usber;
> + u8 res3[2];
> + __be16 usb_usbmr;
> + u8 res4[1];
> + u8 usb_usbs;
> + /* Fields down below are QE-only */
> + __be16 usb_ussft;
> + u8 res5[2];
> + __be16 usb_usfrn;
> + u8 res6[0x22];
> +} __attribute__ ((packed));
> +
> +/*
> + * Function code bits, usually generic to devices.
> + */
> +#ifdef CONFIG_CPM1
> +#define CPMFCR_GBL ((u_char)0x00) /* Flag doesn't exist in CPM1 */
> +#define CPMFCR_TC2 ((u_char)0x00) /* Flag doesn't exist in CPM1 */
> +#define CPMFCR_DTB ((u_char)0x00) /* Flag doesn't exist in CPM1 */
> +#define CPMFCR_BDB ((u_char)0x00) /* Flag doesn't exist in CPM1 */
> +#else
> +#define CPMFCR_GBL ((u_char)0x20) /* Set memory snooping */
> +#define CPMFCR_TC2 ((u_char)0x04) /* Transfer code 2 value */
> +#define CPMFCR_DTB ((u_char)0x02) /* Use local bus for data when set */
> +#define CPMFCR_BDB ((u_char)0x01) /* Use local bus for BD when set */
> +#endif
> +#define CPMFCR_EB ((u_char)0x10) /* Set big endian byte order */
> +
> +/* Opcodes common to CPM1 and CPM2
> +*/
> +#define CPM_CR_INIT_TRX ((ushort)0x0000)
> +#define CPM_CR_INIT_RX ((ushort)0x0001)
> +#define CPM_CR_INIT_TX ((ushort)0x0002)
> +#define CPM_CR_HUNT_MODE ((ushort)0x0003)
> +#define CPM_CR_STOP_TX ((ushort)0x0004)
> +#define CPM_CR_GRA_STOP_TX ((ushort)0x0005)
> +#define CPM_CR_RESTART_TX ((ushort)0x0006)
> +#define CPM_CR_CLOSE_RX_BD ((ushort)0x0007)
> +#define CPM_CR_SET_GADDR ((ushort)0x0008)
> +#define CPM_CR_SET_TIMER ((ushort)0x0008)
> +#define CPM_CR_STOP_IDMA ((ushort)0x000b)
> +
> +/* Buffer descriptors used by many of the CPM protocols. */
> +typedef struct cpm_buf_desc {
> + ushort cbd_sc; /* Status and Control */
> + ushort cbd_datlen; /* Data length in buffer */
> + uint cbd_bufaddr; /* Buffer address in host memory */
> +} cbd_t;
> +
> +/* Buffer descriptor control/status used by serial
> + */
> +
> +#define BD_SC_EMPTY (0x8000) /* Receive is empty */
> +#define BD_SC_READY (0x8000) /* Transmit is ready */
> +#define BD_SC_WRAP (0x2000) /* Last buffer descriptor */
> +#define BD_SC_INTRPT (0x1000) /* Interrupt on change */
> +#define BD_SC_LAST (0x0800) /* Last buffer in frame */
> +#define BD_SC_TC (0x0400) /* Transmit CRC */
> +#define BD_SC_CM (0x0200) /* Continuous mode */
> +#define BD_SC_ID (0x0100) /* Rec'd too many idles */
> +#define BD_SC_P (0x0100) /* xmt preamble */
> +#define BD_SC_BR (0x0020) /* Break received */
> +#define BD_SC_FR (0x0010) /* Framing error */
> +#define BD_SC_PR (0x0008) /* Parity error */
> +#define BD_SC_NAK (0x0004) /* NAK - did not respond */
> +#define BD_SC_OV (0x0002) /* Overrun */
> +#define BD_SC_UN (0x0002) /* Underrun */
> +#define BD_SC_CD (0x0001) /* */
> +#define BD_SC_CL (0x0001) /* Collision */
> +
> +/* Buffer descriptor control/status used by Ethernet receive.
> + * Common to SCC and FCC.
> + */
> +#define BD_ENET_RX_EMPTY (0x8000)
> +#define BD_ENET_RX_WRAP (0x2000)
> +#define BD_ENET_RX_INTR (0x1000)
> +#define BD_ENET_RX_LAST (0x0800)
> +#define BD_ENET_RX_FIRST (0x0400)
> +#define BD_ENET_RX_MISS (0x0100)
> +#define BD_ENET_RX_BC (0x0080) /* FCC Only */
> +#define BD_ENET_RX_MC (0x0040) /* FCC Only */
> +#define BD_ENET_RX_LG (0x0020)
> +#define BD_ENET_RX_NO (0x0010)
> +#define BD_ENET_RX_SH (0x0008)
> +#define BD_ENET_RX_CR (0x0004)
> +#define BD_ENET_RX_OV (0x0002)
> +#define BD_ENET_RX_CL (0x0001)
> +#define BD_ENET_RX_STATS (0x01ff) /* All status bits */
> +
> +/* Buffer descriptor control/status used by Ethernet transmit.
> + * Common to SCC and FCC.
> + */
> +#define BD_ENET_TX_READY (0x8000)
> +#define BD_ENET_TX_PAD (0x4000)
> +#define BD_ENET_TX_WRAP (0x2000)
> +#define BD_ENET_TX_INTR (0x1000)
> +#define BD_ENET_TX_LAST (0x0800)
> +#define BD_ENET_TX_TC (0x0400)
> +#define BD_ENET_TX_DEF (0x0200)
> +#define BD_ENET_TX_HB (0x0100)
> +#define BD_ENET_TX_LC (0x0080)
> +#define BD_ENET_TX_RL (0x0040)
> +#define BD_ENET_TX_RCMASK (0x003c)
> +#define BD_ENET_TX_UN (0x0002)
> +#define BD_ENET_TX_CSL (0x0001)
> +#define BD_ENET_TX_STATS (0x03ff) /* All status bits */
> +
> +/* Buffer descriptor control/status used by Transparent mode SCC.
> + */
> +#define BD_SCC_TX_LAST (0x0800)
> +
> +/* Buffer descriptor control/status used by I2C.
> + */
> +#define BD_I2C_START (0x0400)
> +
> +#ifdef CONFIG_CPM
> +int cpm_command(u32 command, u8 opcode);
> +#else
> +static inline int cpm_command(u32 command, u8 opcode)
> +{
> + return -ENOSYS;
> +}
> +#endif /* CONFIG_CPM */
> +
> +int cpm2_gpiochip_add32(struct device *dev);
> +
> +#endif
>
^ permalink raw reply [flat|nested] 120+ messages in thread
* Re: [PATCH v3 26/36] soc: fsl: move cpm.h from powerpc/include/asm to include/soc/fsl
2019-11-01 16:18 ` Christophe Leroy
@ 2019-11-01 16:59 ` Scott Wood
0 siblings, 0 replies; 120+ messages in thread
From: Scott Wood @ 2019-11-01 16:59 UTC (permalink / raw)
To: Christophe Leroy, Rasmus Villemoes, Qiang Zhao, Li Yang
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel
On Fri, 2019-11-01 at 17:18 +0100, Christophe Leroy wrote:
>
> Le 01/11/2019 à 13:42, Rasmus Villemoes a écrit :
> > Some drivers, e.g. ucc_uart, need definitions from cpm.h. In order to
> > allow building those drivers for non-ppc based SOCs, move the header
> > to include/soc/fsl. For now, leave a trivial wrapper at the old
> > location so drivers can be updated one by one.
>
> I'm not sure that's the correct way to go.
>
> As far as I know, CPM is specific to powerpc (or maybe common to some
> motorola 68000). So only powerpc specific drivers should need it.
>
> If cpm.h includes items that are needed for QE, those items should go in
> another .h
>
> Of course, it doesn't mean we can't move cpm.h in include/soc/fsl, but
> anyway only platforms having CPM1 or CPM2 should include it.
QE is basically CPM3 so it's not surprising that cpm.h would be needed. I
wonder how much less unnecessary code duplication there would have been if
marketing hadn't decided to change the name.
-Scott
^ permalink raw reply [flat|nested] 120+ messages in thread
* [PATCH v3 27/36] soc/fsl/qe/qe.h: update include path for cpm.h
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (25 preceding siblings ...)
2019-11-01 12:42 ` [PATCH v3 26/36] soc: fsl: move cpm.h from powerpc/include/asm to include/soc/fsl Rasmus Villemoes
@ 2019-11-01 12:42 ` Rasmus Villemoes
2019-11-01 12:42 ` [PATCH v3 28/36] serial: ucc_uart: explicitly include soc/fsl/cpm.h Rasmus Villemoes
` (8 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:42 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes
asm/cpm.h under arch/powerpc is now just a wrapper for including
soc/fsl/cpm.h. In order to make the qe.h header usable on other
architectures, use the latter path directly.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
include/soc/fsl/qe/qe.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/soc/fsl/qe/qe.h b/include/soc/fsl/qe/qe.h
index 9cac04c692fd..521fa3a177e0 100644
--- a/include/soc/fsl/qe/qe.h
+++ b/include/soc/fsl/qe/qe.h
@@ -17,7 +17,7 @@
#include <linux/spinlock.h>
#include <linux/errno.h>
#include <linux/err.h>
-#include <asm/cpm.h>
+#include <soc/fsl/cpm.h>
#include <soc/fsl/qe/immap_qe.h>
#include <linux/of.h>
#include <linux/of_address.h>
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 28/36] serial: ucc_uart: explicitly include soc/fsl/cpm.h
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (26 preceding siblings ...)
2019-11-01 12:42 ` [PATCH v3 27/36] soc/fsl/qe/qe.h: update include path for cpm.h Rasmus Villemoes
@ 2019-11-01 12:42 ` Rasmus Villemoes
2019-11-01 16:19 ` Christophe Leroy
2019-11-01 12:42 ` [PATCH v3 29/36] serial: ucc_uart: replace ppc-specific IO accessors Rasmus Villemoes
` (7 subsequent siblings)
35 siblings, 1 reply; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:42 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes, linux-serial
This driver uses #defines from soc/fsl/cpm.h, so instead of relying on
some other header pulling that in, do that explicitly. This is
preparation for allowing this driver to build on ARM.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/tty/serial/ucc_uart.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c
index a0555ae2b1ef..7e802616cba8 100644
--- a/drivers/tty/serial/ucc_uart.c
+++ b/drivers/tty/serial/ucc_uart.c
@@ -32,6 +32,7 @@
#include <soc/fsl/qe/ucc_slow.h>
#include <linux/firmware.h>
+#include <soc/fsl/cpm.h>
#include <asm/reg.h>
/*
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* Re: [PATCH v3 28/36] serial: ucc_uart: explicitly include soc/fsl/cpm.h
2019-11-01 12:42 ` [PATCH v3 28/36] serial: ucc_uart: explicitly include soc/fsl/cpm.h Rasmus Villemoes
@ 2019-11-01 16:19 ` Christophe Leroy
2019-11-04 7:38 ` Rasmus Villemoes
0 siblings, 1 reply; 120+ messages in thread
From: Christophe Leroy @ 2019-11-01 16:19 UTC (permalink / raw)
To: Rasmus Villemoes, Qiang Zhao, Li Yang
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood, linux-serial
Le 01/11/2019 à 13:42, Rasmus Villemoes a écrit :
> This driver uses #defines from soc/fsl/cpm.h, so instead of relying on
> some other header pulling that in, do that explicitly. This is
> preparation for allowing this driver to build on ARM.
>
UCC are only on QE.
CPM has SCCs. instead.
So this driver shouldn't need cpm.h
Christophe
> Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
> ---
> drivers/tty/serial/ucc_uart.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c
> index a0555ae2b1ef..7e802616cba8 100644
> --- a/drivers/tty/serial/ucc_uart.c
> +++ b/drivers/tty/serial/ucc_uart.c
> @@ -32,6 +32,7 @@
> #include <soc/fsl/qe/ucc_slow.h>
>
> #include <linux/firmware.h>
> +#include <soc/fsl/cpm.h>
> #include <asm/reg.h>
>
> /*
>
^ permalink raw reply [flat|nested] 120+ messages in thread
* Re: [PATCH v3 28/36] serial: ucc_uart: explicitly include soc/fsl/cpm.h
2019-11-01 16:19 ` Christophe Leroy
@ 2019-11-04 7:38 ` Rasmus Villemoes
0 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-04 7:38 UTC (permalink / raw)
To: Christophe Leroy, Qiang Zhao, Li Yang
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood, linux-serial
On 01/11/2019 17.19, Christophe Leroy wrote:
> Le 01/11/2019 à 13:42, Rasmus Villemoes a écrit :
>> This driver uses #defines from soc/fsl/cpm.h, so instead of relying on
>> some other header pulling that in, do that explicitly. This is
>> preparation for allowing this driver to build on ARM.
>>
>
> UCC are only on QE.
> CPM has SCCs. instead.
> So this driver shouldn't need cpm.h
But it does. At the very least for the BD_SC_* defines, possibly others
things. It's possible one could split off the common part to a separate
header, but that sort of cleanup/refactoring is beyond what I'd be
comfortable including in this series.
Rasmus
^ permalink raw reply [flat|nested] 120+ messages in thread
* [PATCH v3 29/36] serial: ucc_uart: replace ppc-specific IO accessors
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (27 preceding siblings ...)
2019-11-01 12:42 ` [PATCH v3 28/36] serial: ucc_uart: explicitly include soc/fsl/cpm.h Rasmus Villemoes
@ 2019-11-01 12:42 ` Rasmus Villemoes
2019-11-01 12:42 ` [PATCH v3 30/36] serial: ucc_uart: factor out soft_uart initialization Rasmus Villemoes
` (6 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:42 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes, linux-serial
Some ARM-based SOCs (e.g. LS1021A) also have a QUICC engine. As
preparation for allowing this driver to build on ARM, replace the
ppc-specific in_be16() etc. by the qe_io* helpers. Done via
coccinelle.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/tty/serial/ucc_uart.c | 210 +++++++++++++++++-----------------
1 file changed, 102 insertions(+), 108 deletions(-)
diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c
index 7e802616cba8..8a378ee5d34f 100644
--- a/drivers/tty/serial/ucc_uart.c
+++ b/drivers/tty/serial/ucc_uart.c
@@ -258,11 +258,11 @@ static unsigned int qe_uart_tx_empty(struct uart_port *port)
struct qe_bd *bdp = qe_port->tx_bd_base;
while (1) {
- if (in_be16(&bdp->status) & BD_SC_READY)
+ if (qe_ioread16be(&bdp->status) & BD_SC_READY)
/* This BD is not done, so return "not done" */
return 0;
- if (in_be16(&bdp->status) & BD_SC_WRAP)
+ if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
/*
* This BD is done and it's the last one, so return
* "done"
@@ -308,7 +308,7 @@ static void qe_uart_stop_tx(struct uart_port *port)
struct uart_qe_port *qe_port =
container_of(port, struct uart_qe_port, port);
- clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
+ qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
}
/*
@@ -343,10 +343,10 @@ static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
p = qe2cpu_addr(bdp->buf, qe_port);
*p++ = port->x_char;
- out_be16(&bdp->length, 1);
- setbits16(&bdp->status, BD_SC_READY);
+ qe_iowrite16be(1, &bdp->length);
+ qe_setbits_be16(&bdp->status, BD_SC_READY);
/* Get next BD. */
- if (in_be16(&bdp->status) & BD_SC_WRAP)
+ if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
bdp = qe_port->tx_bd_base;
else
bdp++;
@@ -365,7 +365,7 @@ static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
/* Pick next descriptor and fill from buffer */
bdp = qe_port->tx_cur;
- while (!(in_be16(&bdp->status) & BD_SC_READY) &&
+ while (!(qe_ioread16be(&bdp->status) & BD_SC_READY) &&
(xmit->tail != xmit->head)) {
count = 0;
p = qe2cpu_addr(bdp->buf, qe_port);
@@ -378,11 +378,11 @@ static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
break;
}
- out_be16(&bdp->length, count);
- setbits16(&bdp->status, BD_SC_READY);
+ qe_iowrite16be(count, &bdp->length);
+ qe_setbits_be16(&bdp->status, BD_SC_READY);
/* Get next BD. */
- if (in_be16(&bdp->status) & BD_SC_WRAP)
+ if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
bdp = qe_port->tx_bd_base;
else
bdp++;
@@ -415,12 +415,12 @@ static void qe_uart_start_tx(struct uart_port *port)
container_of(port, struct uart_qe_port, port);
/* If we currently are transmitting, then just return */
- if (in_be16(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)
+ if (qe_ioread16be(&qe_port->uccp->uccm) & UCC_UART_UCCE_TX)
return;
/* Otherwise, pump the port and start transmission */
if (qe_uart_tx_pump(qe_port))
- setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
+ qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_TX);
}
/*
@@ -431,7 +431,7 @@ static void qe_uart_stop_rx(struct uart_port *port)
struct uart_qe_port *qe_port =
container_of(port, struct uart_qe_port, port);
- clrbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
+ qe_clrbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
}
/* Start or stop sending break signal
@@ -470,14 +470,14 @@ static void qe_uart_int_rx(struct uart_qe_port *qe_port)
*/
bdp = qe_port->rx_cur;
while (1) {
- status = in_be16(&bdp->status);
+ status = qe_ioread16be(&bdp->status);
/* If this one is empty, then we assume we've read them all */
if (status & BD_SC_EMPTY)
break;
/* get number of characters, and check space in RX buffer */
- i = in_be16(&bdp->length);
+ i = qe_ioread16be(&bdp->length);
/* If we don't have enough room in RX buffer for the entire BD,
* then we try later, which will be the next RX interrupt.
@@ -508,9 +508,10 @@ static void qe_uart_int_rx(struct uart_qe_port *qe_port)
}
/* This BD is ready to be used again. Clear status. get next */
- clrsetbits_be16(&bdp->status, BD_SC_BR | BD_SC_FR | BD_SC_PR |
- BD_SC_OV | BD_SC_ID, BD_SC_EMPTY);
- if (in_be16(&bdp->status) & BD_SC_WRAP)
+ qe_clrsetbits_be16(&bdp->status,
+ BD_SC_BR | BD_SC_FR | BD_SC_PR | BD_SC_OV | BD_SC_ID,
+ BD_SC_EMPTY);
+ if (qe_ioread16be(&bdp->status) & BD_SC_WRAP)
bdp = qe_port->rx_bd_base;
else
bdp++;
@@ -569,8 +570,8 @@ static irqreturn_t qe_uart_int(int irq, void *data)
u16 events;
/* Clear the interrupts */
- events = in_be16(&uccp->ucce);
- out_be16(&uccp->ucce, events);
+ events = qe_ioread16be(&uccp->ucce);
+ qe_iowrite16be(events, &uccp->ucce);
if (events & UCC_UART_UCCE_BRKE)
uart_handle_break(&qe_port->port);
@@ -601,17 +602,17 @@ static void qe_uart_initbd(struct uart_qe_port *qe_port)
bdp = qe_port->rx_bd_base;
qe_port->rx_cur = qe_port->rx_bd_base;
for (i = 0; i < (qe_port->rx_nrfifos - 1); i++) {
- out_be16(&bdp->status, BD_SC_EMPTY | BD_SC_INTRPT);
- out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
- out_be16(&bdp->length, 0);
+ qe_iowrite16be(BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);
+ qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
+ qe_iowrite16be(0, &bdp->length);
bd_virt += qe_port->rx_fifosize;
bdp++;
}
/* */
- out_be16(&bdp->status, BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT);
- out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
- out_be16(&bdp->length, 0);
+ qe_iowrite16be(BD_SC_WRAP | BD_SC_EMPTY | BD_SC_INTRPT, &bdp->status);
+ qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
+ qe_iowrite16be(0, &bdp->length);
/* Set the physical address of the host memory
* buffers in the buffer descriptors, and the
@@ -622,21 +623,21 @@ static void qe_uart_initbd(struct uart_qe_port *qe_port)
qe_port->tx_cur = qe_port->tx_bd_base;
bdp = qe_port->tx_bd_base;
for (i = 0; i < (qe_port->tx_nrfifos - 1); i++) {
- out_be16(&bdp->status, BD_SC_INTRPT);
- out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
- out_be16(&bdp->length, 0);
+ qe_iowrite16be(BD_SC_INTRPT, &bdp->status);
+ qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
+ qe_iowrite16be(0, &bdp->length);
bd_virt += qe_port->tx_fifosize;
bdp++;
}
/* Loopback requires the preamble bit to be set on the first TX BD */
#ifdef LOOPBACK
- setbits16(&qe_port->tx_cur->status, BD_SC_P);
+ qe_setbits_be16(&qe_port->tx_cur->status, BD_SC_P);
#endif
- out_be16(&bdp->status, BD_SC_WRAP | BD_SC_INTRPT);
- out_be32(&bdp->buf, cpu2qe_addr(bd_virt, qe_port));
- out_be16(&bdp->length, 0);
+ qe_iowrite16be(BD_SC_WRAP | BD_SC_INTRPT, &bdp->status);
+ qe_iowrite32be(cpu2qe_addr(bd_virt, qe_port), &bdp->buf);
+ qe_iowrite16be(0, &bdp->length);
}
/*
@@ -658,78 +659,74 @@ static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
/* Program the UCC UART parameter RAM */
- out_8(&uccup->common.rbmr, UCC_BMR_GBL | UCC_BMR_BO_BE);
- out_8(&uccup->common.tbmr, UCC_BMR_GBL | UCC_BMR_BO_BE);
- out_be16(&uccup->common.mrblr, qe_port->rx_fifosize);
- out_be16(&uccup->maxidl, 0x10);
- out_be16(&uccup->brkcr, 1);
- out_be16(&uccup->parec, 0);
- out_be16(&uccup->frmec, 0);
- out_be16(&uccup->nosec, 0);
- out_be16(&uccup->brkec, 0);
- out_be16(&uccup->uaddr[0], 0);
- out_be16(&uccup->uaddr[1], 0);
- out_be16(&uccup->toseq, 0);
+ qe_iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.rbmr);
+ qe_iowrite8(UCC_BMR_GBL | UCC_BMR_BO_BE, &uccup->common.tbmr);
+ qe_iowrite16be(qe_port->rx_fifosize, &uccup->common.mrblr);
+ qe_iowrite16be(0x10, &uccup->maxidl);
+ qe_iowrite16be(1, &uccup->brkcr);
+ qe_iowrite16be(0, &uccup->parec);
+ qe_iowrite16be(0, &uccup->frmec);
+ qe_iowrite16be(0, &uccup->nosec);
+ qe_iowrite16be(0, &uccup->brkec);
+ qe_iowrite16be(0, &uccup->uaddr[0]);
+ qe_iowrite16be(0, &uccup->uaddr[1]);
+ qe_iowrite16be(0, &uccup->toseq);
for (i = 0; i < 8; i++)
- out_be16(&uccup->cchars[i], 0xC000);
- out_be16(&uccup->rccm, 0xc0ff);
+ qe_iowrite16be(0xC000, &uccup->cchars[i]);
+ qe_iowrite16be(0xc0ff, &uccup->rccm);
/* Configure the GUMR registers for UART */
if (soft_uart) {
/* Soft-UART requires a 1X multiplier for TX */
- clrsetbits_be32(&uccp->gumr_l,
- UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
- UCC_SLOW_GUMR_L_RDCR_MASK,
- UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 |
- UCC_SLOW_GUMR_L_RDCR_16);
-
- clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
- UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);
+ qe_clrsetbits_be32(&uccp->gumr_l,
+ UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
+ UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_1 | UCC_SLOW_GUMR_L_RDCR_16);
+
+ qe_clrsetbits_be32(&uccp->gumr_h, UCC_SLOW_GUMR_H_RFW,
+ UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX);
} else {
- clrsetbits_be32(&uccp->gumr_l,
- UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
- UCC_SLOW_GUMR_L_RDCR_MASK,
- UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 |
- UCC_SLOW_GUMR_L_RDCR_16);
-
- clrsetbits_be32(&uccp->gumr_h,
- UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX,
- UCC_SLOW_GUMR_H_RFW);
+ qe_clrsetbits_be32(&uccp->gumr_l,
+ UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
+ UCC_SLOW_GUMR_L_MODE_UART | UCC_SLOW_GUMR_L_TDCR_16 | UCC_SLOW_GUMR_L_RDCR_16);
+
+ qe_clrsetbits_be32(&uccp->gumr_h,
+ UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX,
+ UCC_SLOW_GUMR_H_RFW);
}
#ifdef LOOPBACK
- clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
- UCC_SLOW_GUMR_L_DIAG_LOOP);
- clrsetbits_be32(&uccp->gumr_h,
- UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_RSYN,
- UCC_SLOW_GUMR_H_CDS);
+ qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
+ UCC_SLOW_GUMR_L_DIAG_LOOP);
+ qe_clrsetbits_be32(&uccp->gumr_h,
+ UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_RSYN,
+ UCC_SLOW_GUMR_H_CDS);
#endif
/* Disable rx interrupts and clear all pending events. */
- out_be16(&uccp->uccm, 0);
- out_be16(&uccp->ucce, 0xffff);
- out_be16(&uccp->udsr, 0x7e7e);
+ qe_iowrite16be(0, &uccp->uccm);
+ qe_iowrite16be(0xffff, &uccp->ucce);
+ qe_iowrite16be(0x7e7e, &uccp->udsr);
/* Initialize UPSMR */
- out_be16(&uccp->upsmr, 0);
+ qe_iowrite16be(0, &uccp->upsmr);
if (soft_uart) {
- out_be16(&uccup->supsmr, 0x30);
- out_be16(&uccup->res92, 0);
- out_be32(&uccup->rx_state, 0);
- out_be32(&uccup->rx_cnt, 0);
- out_8(&uccup->rx_bitmark, 0);
- out_8(&uccup->rx_length, 10);
- out_be32(&uccup->dump_ptr, 0x4000);
- out_8(&uccup->rx_temp_dlst_qe, 0);
- out_be32(&uccup->rx_frame_rem, 0);
- out_8(&uccup->rx_frame_rem_size, 0);
+ qe_iowrite16be(0x30, &uccup->supsmr);
+ qe_iowrite16be(0, &uccup->res92);
+ qe_iowrite32be(0, &uccup->rx_state);
+ qe_iowrite32be(0, &uccup->rx_cnt);
+ qe_iowrite8(0, &uccup->rx_bitmark);
+ qe_iowrite8(10, &uccup->rx_length);
+ qe_iowrite32be(0x4000, &uccup->dump_ptr);
+ qe_iowrite8(0, &uccup->rx_temp_dlst_qe);
+ qe_iowrite32be(0, &uccup->rx_frame_rem);
+ qe_iowrite8(0, &uccup->rx_frame_rem_size);
/* Soft-UART requires TX to be 1X */
- out_8(&uccup->tx_mode,
- UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1);
- out_be16(&uccup->tx_state, 0);
- out_8(&uccup->resD4, 0);
- out_be16(&uccup->resD5, 0);
+ qe_iowrite8(UCC_UART_TX_STATE_UART | UCC_UART_TX_STATE_X1,
+ &uccup->tx_mode);
+ qe_iowrite16be(0, &uccup->tx_state);
+ qe_iowrite8(0, &uccup->resD4);
+ qe_iowrite16be(0, &uccup->resD5);
/* Set UART mode.
* Enable receive and transmit.
@@ -743,22 +740,19 @@ static void qe_uart_init_ucc(struct uart_qe_port *qe_port)
* ...
* 6.Receiver must use 16x over sampling
*/
- clrsetbits_be32(&uccp->gumr_l,
- UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK |
- UCC_SLOW_GUMR_L_RDCR_MASK,
- UCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_16 |
- UCC_SLOW_GUMR_L_RDCR_16);
+ qe_clrsetbits_be32(&uccp->gumr_l,
+ UCC_SLOW_GUMR_L_MODE_MASK | UCC_SLOW_GUMR_L_TDCR_MASK | UCC_SLOW_GUMR_L_RDCR_MASK,
+ UCC_SLOW_GUMR_L_MODE_QMC | UCC_SLOW_GUMR_L_TDCR_16 | UCC_SLOW_GUMR_L_RDCR_16);
- clrsetbits_be32(&uccp->gumr_h,
- UCC_SLOW_GUMR_H_RFW | UCC_SLOW_GUMR_H_RSYN,
- UCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX |
- UCC_SLOW_GUMR_H_TTX | UCC_SLOW_GUMR_H_TFL);
+ qe_clrsetbits_be32(&uccp->gumr_h,
+ UCC_SLOW_GUMR_H_RFW | UCC_SLOW_GUMR_H_RSYN,
+ UCC_SLOW_GUMR_H_SUART | UCC_SLOW_GUMR_H_TRX | UCC_SLOW_GUMR_H_TTX | UCC_SLOW_GUMR_H_TFL);
#ifdef LOOPBACK
- clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
- UCC_SLOW_GUMR_L_DIAG_LOOP);
- clrbits32(&uccp->gumr_h, UCC_SLOW_GUMR_H_CTSP |
- UCC_SLOW_GUMR_H_CDS);
+ qe_clrsetbits_be32(&uccp->gumr_l, UCC_SLOW_GUMR_L_DIAG_MASK,
+ UCC_SLOW_GUMR_L_DIAG_LOOP);
+ qe_clrbits_be32(&uccp->gumr_h,
+ UCC_SLOW_GUMR_H_CTSP | UCC_SLOW_GUMR_H_CDS);
#endif
cecr_subblock = ucc_slow_get_qe_cr_subblock(qe_port->ucc_num);
@@ -801,7 +795,7 @@ static int qe_uart_startup(struct uart_port *port)
}
/* Startup rx-int */
- setbits16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
+ qe_setbits_be16(&qe_port->uccp->uccm, UCC_UART_UCCE_RX);
ucc_slow_enable(qe_port->us_private, COMM_DIR_RX_AND_TX);
return 0;
@@ -837,7 +831,7 @@ static void qe_uart_shutdown(struct uart_port *port)
/* Stop uarts */
ucc_slow_disable(qe_port->us_private, COMM_DIR_RX_AND_TX);
- clrbits16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX);
+ qe_clrbits_be16(&uccp->uccm, UCC_UART_UCCE_TX | UCC_UART_UCCE_RX);
/* Shut them really down and reinit buffer descriptors */
ucc_slow_graceful_stop_tx(qe_port->us_private);
@@ -857,9 +851,9 @@ static void qe_uart_set_termios(struct uart_port *port,
struct ucc_slow __iomem *uccp = qe_port->uccp;
unsigned int baud;
unsigned long flags;
- u16 upsmr = in_be16(&uccp->upsmr);
+ u16 upsmr = qe_ioread16be(&uccp->upsmr);
struct ucc_uart_pram __iomem *uccup = qe_port->uccup;
- u16 supsmr = in_be16(&uccup->supsmr);
+ u16 supsmr = qe_ioread16be(&uccup->supsmr);
u8 char_length = 2; /* 1 + CL + PEN + 1 + SL */
/* Character length programmed into the mode register is the
@@ -957,10 +951,10 @@ static void qe_uart_set_termios(struct uart_port *port,
/* Update the per-port timeout. */
uart_update_timeout(port, termios->c_cflag, baud);
- out_be16(&uccp->upsmr, upsmr);
+ qe_iowrite16be(upsmr, &uccp->upsmr);
if (soft_uart) {
- out_be16(&uccup->supsmr, supsmr);
- out_8(&uccup->rx_length, char_length);
+ qe_iowrite16be(supsmr, &uccup->supsmr);
+ qe_iowrite8(char_length, &uccup->rx_length);
/* Soft-UART requires a 1X multiplier for TX */
qe_setbrg(qe_port->us_info.rx_clock, baud, 16);
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 30/36] serial: ucc_uart: factor out soft_uart initialization
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (28 preceding siblings ...)
2019-11-01 12:42 ` [PATCH v3 29/36] serial: ucc_uart: replace ppc-specific IO accessors Rasmus Villemoes
@ 2019-11-01 12:42 ` Rasmus Villemoes
2019-11-01 12:42 ` [PATCH v3 31/36] serial: ucc_uart: stub out soft_uart_init for !CONFIG_PPC32 Rasmus Villemoes
` (5 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:42 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes, linux-serial
The "soft uart" mechanism is a workaround for a silicon bug which (as
far as I know) only affects some PPC-based SOCs.
The code that determines which microcode blob to request relies on
some powerpc-specific bits (e.g. the mfspr(SPRN_SVR) and hence also
the asm/reg.h header). This makes it a little awkward to allow this
driver to be built for non-PPC based SOCs with a QE, even if they are
not affected by that silicon bug and thus don't need any of the Soft
UART logic.
There's no way around guarding those bits with some ifdeffery, so to
keep that isolated, factor out the
do-we-need-soft-uart-and-if-so-handle-the-firmware to a separate
function, which we can then easily stub out for non-PPC.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/tty/serial/ucc_uart.c | 110 ++++++++++++++++++----------------
1 file changed, 58 insertions(+), 52 deletions(-)
diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c
index 8a378ee5d34f..f286e91714cb 100644
--- a/drivers/tty/serial/ucc_uart.c
+++ b/drivers/tty/serial/ucc_uart.c
@@ -1183,70 +1183,76 @@ static void uart_firmware_cont(const struct firmware *fw, void *context)
release_firmware(fw);
}
-static int ucc_uart_probe(struct platform_device *ofdev)
+static int soft_uart_init(struct platform_device *ofdev)
{
struct device_node *np = ofdev->dev.of_node;
- const unsigned int *iprop; /* Integer OF properties */
- const char *sprop; /* String OF properties */
- struct uart_qe_port *qe_port = NULL;
- struct resource res;
+ struct qe_firmware_info *qe_fw_info;
int ret;
- /*
- * Determine if we need Soft-UART mode
- */
if (of_find_property(np, "soft-uart", NULL)) {
dev_dbg(&ofdev->dev, "using Soft-UART mode\n");
soft_uart = 1;
+ } else {
+ return 0;
}
- /*
- * If we are using Soft-UART, determine if we need to upload the
- * firmware, too.
- */
- if (soft_uart) {
- struct qe_firmware_info *qe_fw_info;
-
- qe_fw_info = qe_get_firmware_info();
-
- /* Check if the firmware has been uploaded. */
- if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) {
- firmware_loaded = 1;
- } else {
- char filename[32];
- unsigned int soc;
- unsigned int rev_h;
- unsigned int rev_l;
-
- soc = soc_info(&rev_h, &rev_l);
- if (!soc) {
- dev_err(&ofdev->dev, "unknown CPU model\n");
- return -ENXIO;
- }
- sprintf(filename, "fsl_qe_ucode_uart_%u_%u%u.bin",
- soc, rev_h, rev_l);
-
- dev_info(&ofdev->dev, "waiting for firmware %s\n",
- filename);
+ qe_fw_info = qe_get_firmware_info();
- /*
- * We call request_firmware_nowait instead of
- * request_firmware so that the driver can load and
- * initialize the ports without holding up the rest of
- * the kernel. If hotplug support is enabled in the
- * kernel, then we use it.
- */
- ret = request_firmware_nowait(THIS_MODULE,
- FW_ACTION_HOTPLUG, filename, &ofdev->dev,
- GFP_KERNEL, &ofdev->dev, uart_firmware_cont);
- if (ret) {
- dev_err(&ofdev->dev,
- "could not load firmware %s\n",
- filename);
- return ret;
- }
+ /* Check if the firmware has been uploaded. */
+ if (qe_fw_info && strstr(qe_fw_info->id, "Soft-UART")) {
+ firmware_loaded = 1;
+ } else {
+ char filename[32];
+ unsigned int soc;
+ unsigned int rev_h;
+ unsigned int rev_l;
+
+ soc = soc_info(&rev_h, &rev_l);
+ if (!soc) {
+ dev_err(&ofdev->dev, "unknown CPU model\n");
+ return -ENXIO;
+ }
+ sprintf(filename, "fsl_qe_ucode_uart_%u_%u%u.bin",
+ soc, rev_h, rev_l);
+
+ dev_info(&ofdev->dev, "waiting for firmware %s\n",
+ filename);
+
+ /*
+ * We call request_firmware_nowait instead of
+ * request_firmware so that the driver can load and
+ * initialize the ports without holding up the rest of
+ * the kernel. If hotplug support is enabled in the
+ * kernel, then we use it.
+ */
+ ret = request_firmware_nowait(THIS_MODULE,
+ FW_ACTION_HOTPLUG, filename, &ofdev->dev,
+ GFP_KERNEL, &ofdev->dev, uart_firmware_cont);
+ if (ret) {
+ dev_err(&ofdev->dev,
+ "could not load firmware %s\n",
+ filename);
+ return ret;
}
}
+ return 0;
+}
+
+static int ucc_uart_probe(struct platform_device *ofdev)
+{
+ struct device_node *np = ofdev->dev.of_node;
+ const unsigned int *iprop; /* Integer OF properties */
+ const char *sprop; /* String OF properties */
+ struct uart_qe_port *qe_port = NULL;
+ struct resource res;
+ int ret;
+
+ /*
+ * Determine if we need Soft-UART mode
+ */
+ ret = soft_uart_init(ofdev);
+ if (ret)
+ return ret;
qe_port = kzalloc(sizeof(struct uart_qe_port), GFP_KERNEL);
if (!qe_port) {
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 31/36] serial: ucc_uart: stub out soft_uart_init for !CONFIG_PPC32
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (29 preceding siblings ...)
2019-11-01 12:42 ` [PATCH v3 30/36] serial: ucc_uart: factor out soft_uart initialization Rasmus Villemoes
@ 2019-11-01 12:42 ` Rasmus Villemoes
2019-11-01 16:27 ` Christophe Leroy
2019-11-01 12:42 ` [PATCH v3 32/36] serial: ucc_uart: use of_property_read_u32() in ucc_uart_probe() Rasmus Villemoes
` (4 subsequent siblings)
35 siblings, 1 reply; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:42 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes, linux-serial
The Soft UART hack is only needed for some PPC-based SOCs. To allow
building this driver for non-PPC, guard soft_uart_init() and its
helpers by CONFIG_PPC32, and use a no-op soft_uart_init() otherwise.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/tty/serial/ucc_uart.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c
index f286e91714cb..313697842e24 100644
--- a/drivers/tty/serial/ucc_uart.c
+++ b/drivers/tty/serial/ucc_uart.c
@@ -33,7 +33,10 @@
#include <linux/firmware.h>
#include <soc/fsl/cpm.h>
-#include <asm/reg.h>
+
+#ifdef CONFIG_PPC32
+#include <asm/reg.h> /* mfspr, SPRN_SVR */
+#endif
/*
* The GUMR flag for Soft UART. This would normally be defined in qe.h,
@@ -1096,6 +1099,8 @@ static const struct uart_ops qe_uart_pops = {
.verify_port = qe_uart_verify_port,
};
+
+#ifdef CONFIG_PPC32
/*
* Obtain the SOC model number and revision level
*
@@ -1238,6 +1243,16 @@ static int soft_uart_init(struct platform_device *ofdev)
return 0;
}
+#else /* !CONFIG_PPC32 */
+
+static int soft_uart_init(struct platform_device *ofdev)
+{
+ return 0;
+}
+
+#endif
+
+
static int ucc_uart_probe(struct platform_device *ofdev)
{
struct device_node *np = ofdev->dev.of_node;
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* Re: [PATCH v3 31/36] serial: ucc_uart: stub out soft_uart_init for !CONFIG_PPC32
2019-11-01 12:42 ` [PATCH v3 31/36] serial: ucc_uart: stub out soft_uart_init for !CONFIG_PPC32 Rasmus Villemoes
@ 2019-11-01 16:27 ` Christophe Leroy
2019-11-04 8:03 ` Rasmus Villemoes
0 siblings, 1 reply; 120+ messages in thread
From: Christophe Leroy @ 2019-11-01 16:27 UTC (permalink / raw)
To: Rasmus Villemoes, Qiang Zhao, Li Yang
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood, linux-serial
Le 01/11/2019 à 13:42, Rasmus Villemoes a écrit :
> The Soft UART hack is only needed for some PPC-based SOCs. To allow
> building this driver for non-PPC, guard soft_uart_init() and its
> helpers by CONFIG_PPC32, and use a no-op soft_uart_init() otherwise.
I don't like too much ifdefs in C files, especially arch specific ifdefs
in generic drivers.
How do we get the QE version on ARM ?
Wouldn't it be cleaner to create a helper for getting the QE version,
which would be defined in an arch specific header file, calling
mfspr(SPRN_SVR) on powerpc and whatever needed on arm ?
Christophe
>
> Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
> ---
> drivers/tty/serial/ucc_uart.c | 17 ++++++++++++++++-
> 1 file changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c
> index f286e91714cb..313697842e24 100644
> --- a/drivers/tty/serial/ucc_uart.c
> +++ b/drivers/tty/serial/ucc_uart.c
> @@ -33,7 +33,10 @@
>
> #include <linux/firmware.h>
> #include <soc/fsl/cpm.h>
> -#include <asm/reg.h>
> +
> +#ifdef CONFIG_PPC32
> +#include <asm/reg.h> /* mfspr, SPRN_SVR */
> +#endif
>
> /*
> * The GUMR flag for Soft UART. This would normally be defined in qe.h,
> @@ -1096,6 +1099,8 @@ static const struct uart_ops qe_uart_pops = {
> .verify_port = qe_uart_verify_port,
> };
>
> +
> +#ifdef CONFIG_PPC32
> /*
> * Obtain the SOC model number and revision level
> *
> @@ -1238,6 +1243,16 @@ static int soft_uart_init(struct platform_device *ofdev)
> return 0;
> }
>
> +#else /* !CONFIG_PPC32 */
> +
> +static int soft_uart_init(struct platform_device *ofdev)
> +{
> + return 0;
> +}
> +
> +#endif
> +
> +
> static int ucc_uart_probe(struct platform_device *ofdev)
> {
> struct device_node *np = ofdev->dev.of_node;
>
^ permalink raw reply [flat|nested] 120+ messages in thread
* Re: [PATCH v3 31/36] serial: ucc_uart: stub out soft_uart_init for !CONFIG_PPC32
2019-11-01 16:27 ` Christophe Leroy
@ 2019-11-04 8:03 ` Rasmus Villemoes
0 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-04 8:03 UTC (permalink / raw)
To: Christophe Leroy, Qiang Zhao, Li Yang
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood, linux-serial
On 01/11/2019 17.27, Christophe Leroy wrote:
>
>
> Le 01/11/2019 à 13:42, Rasmus Villemoes a écrit :
>> The Soft UART hack is only needed for some PPC-based SOCs. To allow
>> building this driver for non-PPC, guard soft_uart_init() and its
>> helpers by CONFIG_PPC32, and use a no-op soft_uart_init() otherwise.
>
> I don't like too much ifdefs in C files, especially arch specific ifdefs
> in generic drivers.
Me neither. However,
> How do we get the QE version on ARM ?
>
> Wouldn't it be cleaner to create a helper for getting the QE version,
> which would be defined in an arch specific header file, calling
> mfspr(SPRN_SVR) on powerpc and whatever needed on arm ?
First, that would mean we'd have to introduce "depends on PPC32 || ARM"
rather than drop "depends on PPC32". Second, the way the SOC version is
being used to construct the name of the microcode blob seems very
ppc-specific, so I don't see how one can reasonably define an interface
that would work for all architectures. But it's also kind of moot since
the ARM SOCs don't need this workaround.
IMO, having to add qe-specific code to arch/ is a cure worse than the
disease. I'd much rather add arch-specific code to qe.
Rasmus
^ permalink raw reply [flat|nested] 120+ messages in thread
* [PATCH v3 32/36] serial: ucc_uart: use of_property_read_u32() in ucc_uart_probe()
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (30 preceding siblings ...)
2019-11-01 12:42 ` [PATCH v3 31/36] serial: ucc_uart: stub out soft_uart_init for !CONFIG_PPC32 Rasmus Villemoes
@ 2019-11-01 12:42 ` Rasmus Villemoes
2019-11-01 12:42 ` [PATCH v3 33/36] serial: ucc_uart: access __be32 field using be32_to_cpu Rasmus Villemoes
` (3 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:42 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes, linux-serial
For this to work correctly on little-endian hosts, don't access the
device-tree properties directly in native endianness, but use the
of_property_read_u32() helper.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/tty/serial/ucc_uart.c | 41 +++++++++++++++--------------------
1 file changed, 17 insertions(+), 24 deletions(-)
diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c
index 313697842e24..f5ea84928a3b 100644
--- a/drivers/tty/serial/ucc_uart.c
+++ b/drivers/tty/serial/ucc_uart.c
@@ -1256,10 +1256,10 @@ static int soft_uart_init(struct platform_device *ofdev)
static int ucc_uart_probe(struct platform_device *ofdev)
{
struct device_node *np = ofdev->dev.of_node;
- const unsigned int *iprop; /* Integer OF properties */
const char *sprop; /* String OF properties */
struct uart_qe_port *qe_port = NULL;
struct resource res;
+ u32 val;
int ret;
/*
@@ -1290,23 +1290,19 @@ static int ucc_uart_probe(struct platform_device *ofdev)
/* Get the UCC number (device ID) */
/* UCCs are numbered 1-7 */
- iprop = of_get_property(np, "cell-index", NULL);
- if (!iprop) {
- iprop = of_get_property(np, "device-id", NULL);
- if (!iprop) {
- dev_err(&ofdev->dev, "UCC is unspecified in "
- "device tree\n");
- ret = -EINVAL;
- goto out_free;
- }
+ if (of_property_read_u32(np, "cell-index", &val) &&
+ of_property_read_u32(np, "device-id", &val)) {
+ dev_err(&ofdev->dev, "UCC is unspecified in device tree\n");
+ ret = -EINVAL;
+ goto out_free;
}
- if ((*iprop < 1) || (*iprop > UCC_MAX_NUM)) {
- dev_err(&ofdev->dev, "no support for UCC%u\n", *iprop);
+ if (val < 1 || val > UCC_MAX_NUM) {
+ dev_err(&ofdev->dev, "no support for UCC%u\n", val);
ret = -ENODEV;
goto out_free;
}
- qe_port->ucc_num = *iprop - 1;
+ qe_port->ucc_num = val - 1;
/*
* In the future, we should not require the BRG to be specified in the
@@ -1350,13 +1346,12 @@ static int ucc_uart_probe(struct platform_device *ofdev)
}
/* Get the port number, numbered 0-3 */
- iprop = of_get_property(np, "port-number", NULL);
- if (!iprop) {
+ if (of_property_read_u32(np, "port-number", &val)) {
dev_err(&ofdev->dev, "missing port-number in device tree\n");
ret = -EINVAL;
goto out_free;
}
- qe_port->port.line = *iprop;
+ qe_port->port.line = val;
if (qe_port->port.line >= UCC_MAX_UART) {
dev_err(&ofdev->dev, "port-number must be 0-%u\n",
UCC_MAX_UART - 1);
@@ -1386,31 +1381,29 @@ static int ucc_uart_probe(struct platform_device *ofdev)
}
}
- iprop = of_get_property(np, "brg-frequency", NULL);
- if (!iprop) {
+ if (of_property_read_u32(np, "brg-frequency", &val)) {
dev_err(&ofdev->dev,
"missing brg-frequency in device tree\n");
ret = -EINVAL;
goto out_np;
}
- if (*iprop)
- qe_port->port.uartclk = *iprop;
+ if (val)
+ qe_port->port.uartclk = val;
else {
/*
* Older versions of U-Boot do not initialize the brg-frequency
* property, so in this case we assume the BRG frequency is
* half the QE bus frequency.
*/
- iprop = of_get_property(np, "bus-frequency", NULL);
- if (!iprop) {
+ if (of_property_read_u32(np, "bus-frequency", &val)) {
dev_err(&ofdev->dev,
"missing QE bus-frequency in device tree\n");
ret = -EINVAL;
goto out_np;
}
- if (*iprop)
- qe_port->port.uartclk = *iprop / 2;
+ if (val)
+ qe_port->port.uartclk = val / 2;
else {
dev_err(&ofdev->dev,
"invalid QE bus-frequency in device tree\n");
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 33/36] serial: ucc_uart: access __be32 field using be32_to_cpu
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (31 preceding siblings ...)
2019-11-01 12:42 ` [PATCH v3 32/36] serial: ucc_uart: use of_property_read_u32() in ucc_uart_probe() Rasmus Villemoes
@ 2019-11-01 12:42 ` Rasmus Villemoes
2019-11-01 12:42 ` [PATCH v3 34/36] net: ethernet: freescale: make UCC_GETH explicitly depend on PPC32 Rasmus Villemoes
` (2 subsequent siblings)
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:42 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes, linux-serial
The buf member of struct qe_bd is a __be32, so to make this work on
little-endian hosts, use be32_to_cpu when reading it.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/tty/serial/ucc_uart.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c
index f5ea84928a3b..a5330582b610 100644
--- a/drivers/tty/serial/ucc_uart.c
+++ b/drivers/tty/serial/ucc_uart.c
@@ -343,7 +343,7 @@ static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
/* Pick next descriptor and fill from buffer */
bdp = qe_port->tx_cur;
- p = qe2cpu_addr(bdp->buf, qe_port);
+ p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
*p++ = port->x_char;
qe_iowrite16be(1, &bdp->length);
@@ -371,7 +371,7 @@ static int qe_uart_tx_pump(struct uart_qe_port *qe_port)
while (!(qe_ioread16be(&bdp->status) & BD_SC_READY) &&
(xmit->tail != xmit->head)) {
count = 0;
- p = qe2cpu_addr(bdp->buf, qe_port);
+ p = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
while (count < qe_port->tx_fifosize) {
*p++ = xmit->buf[xmit->tail];
xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
@@ -491,7 +491,7 @@ static void qe_uart_int_rx(struct uart_qe_port *qe_port)
}
/* get pointer */
- cp = qe2cpu_addr(bdp->buf, qe_port);
+ cp = qe2cpu_addr(be32_to_cpu(bdp->buf), qe_port);
/* loop through the buffer */
while (i-- > 0) {
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 34/36] net: ethernet: freescale: make UCC_GETH explicitly depend on PPC32
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (32 preceding siblings ...)
2019-11-01 12:42 ` [PATCH v3 33/36] serial: ucc_uart: access __be32 field using be32_to_cpu Rasmus Villemoes
@ 2019-11-01 12:42 ` Rasmus Villemoes
2019-11-01 12:42 ` [PATCH v3 35/36] net/wan: make FSL_UCC_HDLC " Rasmus Villemoes
2019-11-01 12:42 ` [PATCH v3 36/36] soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE Rasmus Villemoes
35 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:42 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes, netdev
Currently, QUICC_ENGINE depends on PPC32, so this in itself does not
change anything. In order to allow removing the PPC32 dependency from
QUICC_ENGINE and avoid allmodconfig build failures, add this explicit
dependency.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/net/ethernet/freescale/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/freescale/Kconfig b/drivers/net/ethernet/freescale/Kconfig
index 6a7e8993119f..2bd7ace0a953 100644
--- a/drivers/net/ethernet/freescale/Kconfig
+++ b/drivers/net/ethernet/freescale/Kconfig
@@ -74,7 +74,7 @@ config FSL_XGMAC_MDIO
config UCC_GETH
tristate "Freescale QE Gigabit Ethernet"
- depends on QUICC_ENGINE
+ depends on QUICC_ENGINE && PPC32
select FSL_PQ_MDIO
select PHYLIB
---help---
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* [PATCH v3 35/36] net/wan: make FSL_UCC_HDLC explicitly depend on PPC32
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (33 preceding siblings ...)
2019-11-01 12:42 ` [PATCH v3 34/36] net: ethernet: freescale: make UCC_GETH explicitly depend on PPC32 Rasmus Villemoes
@ 2019-11-01 12:42 ` Rasmus Villemoes
2019-11-01 16:29 ` Christophe Leroy
2019-11-01 12:42 ` [PATCH v3 36/36] soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE Rasmus Villemoes
35 siblings, 1 reply; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:42 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes, netdev
Currently, FSL_UCC_HDLC depends on QUICC_ENGINE, which in turn depends
on PPC32. As preparation for removing the latter and thus allowing the
core QE code to be built for other architectures, make FSL_UCC_HDLC
explicitly depend on PPC32.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/net/wan/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig
index dd1a147f2971..78785d790bcc 100644
--- a/drivers/net/wan/Kconfig
+++ b/drivers/net/wan/Kconfig
@@ -270,7 +270,7 @@ config FARSYNC
config FSL_UCC_HDLC
tristate "Freescale QUICC Engine HDLC support"
depends on HDLC
- depends on QUICC_ENGINE
+ depends on QUICC_ENGINE && PPC32
help
Driver for Freescale QUICC Engine HDLC controller. The driver
supports HDLC in NMSI and TDM mode.
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* Re: [PATCH v3 35/36] net/wan: make FSL_UCC_HDLC explicitly depend on PPC32
2019-11-01 12:42 ` [PATCH v3 35/36] net/wan: make FSL_UCC_HDLC " Rasmus Villemoes
@ 2019-11-01 16:29 ` Christophe Leroy
2019-11-01 22:31 ` Leo Li
0 siblings, 1 reply; 120+ messages in thread
From: Christophe Leroy @ 2019-11-01 16:29 UTC (permalink / raw)
To: Rasmus Villemoes, Qiang Zhao, Li Yang
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood, netdev
Le 01/11/2019 à 13:42, Rasmus Villemoes a écrit :
> Currently, FSL_UCC_HDLC depends on QUICC_ENGINE, which in turn depends
> on PPC32. As preparation for removing the latter and thus allowing the
> core QE code to be built for other architectures, make FSL_UCC_HDLC
> explicitly depend on PPC32.
Is that really powerpc specific ? Can't the ARM QE perform HDLC on UCC ?
Christophe
>
> Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
> ---
> drivers/net/wan/Kconfig | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig
> index dd1a147f2971..78785d790bcc 100644
> --- a/drivers/net/wan/Kconfig
> +++ b/drivers/net/wan/Kconfig
> @@ -270,7 +270,7 @@ config FARSYNC
> config FSL_UCC_HDLC
> tristate "Freescale QUICC Engine HDLC support"
> depends on HDLC
> - depends on QUICC_ENGINE
> + depends on QUICC_ENGINE && PPC32
> help
> Driver for Freescale QUICC Engine HDLC controller. The driver
> supports HDLC in NMSI and TDM mode.
>
^ permalink raw reply [flat|nested] 120+ messages in thread
* RE: [PATCH v3 35/36] net/wan: make FSL_UCC_HDLC explicitly depend on PPC32
2019-11-01 16:29 ` Christophe Leroy
@ 2019-11-01 22:31 ` Leo Li
2019-11-04 8:38 ` Rasmus Villemoes
0 siblings, 1 reply; 120+ messages in thread
From: Leo Li @ 2019-11-01 22:31 UTC (permalink / raw)
To: Christophe Leroy, Rasmus Villemoes, Qiang Zhao
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood, netdev
> -----Original Message-----
> From: Christophe Leroy <christophe.leroy@c-s.fr>
> Sent: Friday, November 1, 2019 11:30 AM
> To: Rasmus Villemoes <linux@rasmusvillemoes.dk>; Qiang Zhao
> <qiang.zhao@nxp.com>; Leo Li <leoyang.li@nxp.com>
> Cc: linuxppc-dev@lists.ozlabs.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; Scott Wood <oss@buserror.net>;
> netdev@vger.kernel.org
> Subject: Re: [PATCH v3 35/36] net/wan: make FSL_UCC_HDLC explicitly
> depend on PPC32
>
>
>
> Le 01/11/2019 à 13:42, Rasmus Villemoes a écrit :
> > Currently, FSL_UCC_HDLC depends on QUICC_ENGINE, which in turn
> depends
> > on PPC32. As preparation for removing the latter and thus allowing the
> > core QE code to be built for other architectures, make FSL_UCC_HDLC
> > explicitly depend on PPC32.
>
> Is that really powerpc specific ? Can't the ARM QE perform HDLC on UCC ?
No. Actually the HDLC and TDM are the major reason to integrate a QE on the ARM based Layerscape SoCs.
Since Rasmus doesn't have the hardware to test this feature Qiang Zhao probably can help verify the functionality of TDM and we can drop this patch.
Regards,
Leo
>
> Christophe
>
> >
> > Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
> > ---
> > drivers/net/wan/Kconfig | 2 +-
> > 1 file changed, 1 insertion(+), 1 deletion(-)
> >
> > diff --git a/drivers/net/wan/Kconfig b/drivers/net/wan/Kconfig index
> > dd1a147f2971..78785d790bcc 100644
> > --- a/drivers/net/wan/Kconfig
> > +++ b/drivers/net/wan/Kconfig
> > @@ -270,7 +270,7 @@ config FARSYNC
> > config FSL_UCC_HDLC
> > tristate "Freescale QUICC Engine HDLC support"
> > depends on HDLC
> > - depends on QUICC_ENGINE
> > + depends on QUICC_ENGINE && PPC32
> > help
> > Driver for Freescale QUICC Engine HDLC controller. The driver
> > supports HDLC in NMSI and TDM mode.
> >
^ permalink raw reply [flat|nested] 120+ messages in thread
* Re: [PATCH v3 35/36] net/wan: make FSL_UCC_HDLC explicitly depend on PPC32
2019-11-01 22:31 ` Leo Li
@ 2019-11-04 8:38 ` Rasmus Villemoes
2019-11-04 20:56 ` Li Yang
2019-11-05 6:16 ` Qiang Zhao
0 siblings, 2 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-04 8:38 UTC (permalink / raw)
To: Leo Li, Christophe Leroy, Qiang Zhao
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood, netdev
On 01/11/2019 23.31, Leo Li wrote:
>
>
>> -----Original Message-----
>> From: Christophe Leroy <christophe.leroy@c-s.fr>
>> Sent: Friday, November 1, 2019 11:30 AM
>> To: Rasmus Villemoes <linux@rasmusvillemoes.dk>; Qiang Zhao
>> <qiang.zhao@nxp.com>; Leo Li <leoyang.li@nxp.com>
>> Cc: linuxppc-dev@lists.ozlabs.org; linux-arm-kernel@lists.infradead.org;
>> linux-kernel@vger.kernel.org; Scott Wood <oss@buserror.net>;
>> netdev@vger.kernel.org
>> Subject: Re: [PATCH v3 35/36] net/wan: make FSL_UCC_HDLC explicitly
>> depend on PPC32
>>
>>
>>
>> Le 01/11/2019 à 13:42, Rasmus Villemoes a écrit :
>>> Currently, FSL_UCC_HDLC depends on QUICC_ENGINE, which in turn
>> depends
>>> on PPC32. As preparation for removing the latter and thus allowing the
>>> core QE code to be built for other architectures, make FSL_UCC_HDLC
>>> explicitly depend on PPC32.
>>
>> Is that really powerpc specific ? Can't the ARM QE perform HDLC on UCC ?
I think the driver would build on ARM. Whether it works I don't know. I
know it does not build on 64 bit hosts (see kbuild report for v2,23/23).
> No. Actually the HDLC and TDM are the major reason to integrate a QE on the ARM based Layerscape SoCs.
[citation needed].
> Since Rasmus doesn't have the hardware to test this feature Qiang Zhao probably can help verify the functionality of TDM and we can drop this patch.
No, this patch cannot be dropped. Please see the kbuild complaints for
v2,23/23 about use of IS_ERR_VALUE on not-sizeof(long) entities. I see
kbuild has complained about the same thing for v3 since apparently the
same thing appears in ucc_slow.c. So I'll fix that.
Moreover, as you say and know, I do not have the hardware to test it, so
I'm not going to even attempt to fix up fsl_ucc_hdlc.c. If Qiang Zhao or
somebody else can verify that it works just fine on ARM and fixes the
allmodconfig problem(s), he/she is more than welcome to sign off on a
patch that removes the CONFIG_PPC32 dependency or replaces it with
something else.
Rasmus
^ permalink raw reply [flat|nested] 120+ messages in thread
* Re: [PATCH v3 35/36] net/wan: make FSL_UCC_HDLC explicitly depend on PPC32
2019-11-04 8:38 ` Rasmus Villemoes
@ 2019-11-04 20:56 ` Li Yang
2019-11-05 22:46 ` Rasmus Villemoes
2019-11-05 6:16 ` Qiang Zhao
1 sibling, 1 reply; 120+ messages in thread
From: Li Yang @ 2019-11-04 20:56 UTC (permalink / raw)
To: Rasmus Villemoes
Cc: Christophe Leroy, Qiang Zhao, linuxppc-dev, linux-arm-kernel,
linux-kernel, Scott Wood, netdev
On Mon, Nov 4, 2019 at 2:39 AM Rasmus Villemoes
<linux@rasmusvillemoes.dk> wrote:
>
> On 01/11/2019 23.31, Leo Li wrote:
> >
> >
> >> -----Original Message-----
> >> From: Christophe Leroy <christophe.leroy@c-s.fr>
> >> Sent: Friday, November 1, 2019 11:30 AM
> >> To: Rasmus Villemoes <linux@rasmusvillemoes.dk>; Qiang Zhao
> >> <qiang.zhao@nxp.com>; Leo Li <leoyang.li@nxp.com>
> >> Cc: linuxppc-dev@lists.ozlabs.org; linux-arm-kernel@lists.infradead.org;
> >> linux-kernel@vger.kernel.org; Scott Wood <oss@buserror.net>;
> >> netdev@vger.kernel.org
> >> Subject: Re: [PATCH v3 35/36] net/wan: make FSL_UCC_HDLC explicitly
> >> depend on PPC32
> >>
> >>
> >>
> >> Le 01/11/2019 à 13:42, Rasmus Villemoes a écrit :
> >>> Currently, FSL_UCC_HDLC depends on QUICC_ENGINE, which in turn
> >> depends
> >>> on PPC32. As preparation for removing the latter and thus allowing the
> >>> core QE code to be built for other architectures, make FSL_UCC_HDLC
> >>> explicitly depend on PPC32.
> >>
> >> Is that really powerpc specific ? Can't the ARM QE perform HDLC on UCC ?
>
> I think the driver would build on ARM. Whether it works I don't know. I
> know it does not build on 64 bit hosts (see kbuild report for v2,23/23).
The problem for arm64 can be easy to fix. Actually I don't think it
is neccessarily to be compiled on all architectures except powerpc,
arm and arm64. I am surprised that you made the core QE code compile
for all architecture(although still have some kbuild warnings)
>
> > No. Actually the HDLC and TDM are the major reason to integrate a QE on the ARM based Layerscape SoCs.
>
> [citation needed].
I got this message from our marketing team. Also it is reflected on
marketing materials like
https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/layerscape-communication-process/qoriq-layerscape-1043a-and-1023a-multicore-communications-processors:LS1043A
"The QorIQ LS1043A ... integrated QUICC Engine® for legacy glue-less
HDLC, TDM or Profibus support."
>
> > Since Rasmus doesn't have the hardware to test this feature Qiang Zhao probably can help verify the functionality of TDM and we can drop this patch.
>
> No, this patch cannot be dropped. Please see the kbuild complaints for
> v2,23/23 about use of IS_ERR_VALUE on not-sizeof(long) entities. I see
> kbuild has complained about the same thing for v3 since apparently the
> same thing appears in ucc_slow.c. So I'll fix that.
When I made this comment I didn't notice you have removed all the
architectural dependencies for CONFIG_QUICC_ENGINE. If the
QUICC_ENGINE is only buidable on powerpc, arm and arm64, this change
will not be needed.
BTW, I'm not sure if it is a good idea to make it selectable on these
unrelavent architectures. Real architectural dependencies and
COMPILE_TEST dependency will be better if we really want to test the
buildability on other platforms.
Regards,
Leo
^ permalink raw reply [flat|nested] 120+ messages in thread
* Re: [PATCH v3 35/36] net/wan: make FSL_UCC_HDLC explicitly depend on PPC32
2019-11-04 20:56 ` Li Yang
@ 2019-11-05 22:46 ` Rasmus Villemoes
2019-11-05 23:46 ` Li Yang
0 siblings, 1 reply; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-05 22:46 UTC (permalink / raw)
To: Li Yang
Cc: Christophe Leroy, Qiang Zhao, linuxppc-dev, linux-arm-kernel,
linux-kernel, Scott Wood, netdev
On 04/11/2019 21.56, Li Yang wrote:
>> No, this patch cannot be dropped. Please see the kbuild complaints for
>> v2,23/23 about use of IS_ERR_VALUE on not-sizeof(long) entities. I see
>> kbuild has complained about the same thing for v3 since apparently the
>> same thing appears in ucc_slow.c. So I'll fix that.
>
> When I made this comment I didn't notice you have removed all the
> architectural dependencies for CONFIG_QUICC_ENGINE. If the
> QUICC_ENGINE is only buidable on powerpc, arm and arm64, this change
> will not be needed.
>
> BTW, I'm not sure if it is a good idea to make it selectable on these
> unrelavent architectures. Real architectural dependencies and
> COMPILE_TEST dependency will be better if we really want to test the
> buildability on other platforms.
Well, making QUICC_ENGINE depend on PPC32 || ARM would certainly make
things easier for me. Once you include ARM64 or any other 64 bit
architecture the buildbot complaints start rolling in from the
IS_ERR_VALUEs. And ARM64 should be supported as well, so there really
isn't much difference between dropping all arch restrictions and listing
the relevant archs in the Kconfig dependencies.
Rasmus
^ permalink raw reply [flat|nested] 120+ messages in thread
* Re: [PATCH v3 35/36] net/wan: make FSL_UCC_HDLC explicitly depend on PPC32
2019-11-05 22:46 ` Rasmus Villemoes
@ 2019-11-05 23:46 ` Li Yang
0 siblings, 0 replies; 120+ messages in thread
From: Li Yang @ 2019-11-05 23:46 UTC (permalink / raw)
To: Rasmus Villemoes
Cc: Christophe Leroy, Qiang Zhao, linuxppc-dev, linux-arm-kernel,
linux-kernel, Scott Wood, netdev
On Tue, Nov 5, 2019 at 4:47 PM Rasmus Villemoes
<linux@rasmusvillemoes.dk> wrote:
>
> On 04/11/2019 21.56, Li Yang wrote:
>
> >> No, this patch cannot be dropped. Please see the kbuild complaints for
> >> v2,23/23 about use of IS_ERR_VALUE on not-sizeof(long) entities. I see
> >> kbuild has complained about the same thing for v3 since apparently the
> >> same thing appears in ucc_slow.c. So I'll fix that.
> >
> > When I made this comment I didn't notice you have removed all the
> > architectural dependencies for CONFIG_QUICC_ENGINE. If the
> > QUICC_ENGINE is only buidable on powerpc, arm and arm64, this change
> > will not be needed.
> >
> > BTW, I'm not sure if it is a good idea to make it selectable on these
> > unrelavent architectures. Real architectural dependencies and
> > COMPILE_TEST dependency will be better if we really want to test the
> > buildability on other platforms.
>
> Well, making QUICC_ENGINE depend on PPC32 || ARM would certainly make
> things easier for me. Once you include ARM64 or any other 64 bit
> architecture the buildbot complaints start rolling in from the
> IS_ERR_VALUEs. And ARM64 should be supported as well, so there really
> isn't much difference between dropping all arch restrictions and listing
> the relevant archs in the Kconfig dependencies.
I agree that it will be good to have the driver compile for all
architectures for compile test. But list all the relevant
architectures and CONFIG_COMPILE_TEST as dependencies will make it not
really selected for these irrelevant architectures in real system.
Regards,
Leo
^ permalink raw reply [flat|nested] 120+ messages in thread
* RE: [PATCH v3 35/36] net/wan: make FSL_UCC_HDLC explicitly depend on PPC32
2019-11-04 8:38 ` Rasmus Villemoes
2019-11-04 20:56 ` Li Yang
@ 2019-11-05 6:16 ` Qiang Zhao
2019-11-06 7:56 ` Rasmus Villemoes
1 sibling, 1 reply; 120+ messages in thread
From: Qiang Zhao @ 2019-11-05 6:16 UTC (permalink / raw)
To: Rasmus Villemoes, Leo Li, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood, netdev
On 01/11/2019 23:31, Rasmus Villemoes wrote :
> -----Original Message-----
> From: Rasmus Villemoes <linux@rasmusvillemoes.dk>
> Sent: 2019年11月4日 16:38
> To: Leo Li <leoyang.li@nxp.com>; Christophe Leroy <christophe.leroy@c-s.fr>;
> Qiang Zhao <qiang.zhao@nxp.com>
> Cc: linuxppc-dev@lists.ozlabs.org; linux-arm-kernel@lists.infradead.org;
> linux-kernel@vger.kernel.org; Scott Wood <oss@buserror.net>;
> netdev@vger.kernel.org
> Subject: Re: [PATCH v3 35/36] net/wan: make FSL_UCC_HDLC explicitly depend
> on PPC32
>
> On 01/11/2019 23.31, Leo Li wrote:
> >
> >
> >> -----Original Message-----
> >> From: Christophe Leroy <christophe.leroy@c-s.fr>
> >> Sent: Friday, November 1, 2019 11:30 AM
> >> To: Rasmus Villemoes <linux@rasmusvillemoes.dk>; Qiang Zhao
> >> <qiang.zhao@nxp.com>; Leo Li <leoyang.li@nxp.com>
> >> Cc: linuxppc-dev@lists.ozlabs.org;
> >> linux-arm-kernel@lists.infradead.org;
> >> linux-kernel@vger.kernel.org; Scott Wood <oss@buserror.net>;
> >> netdev@vger.kernel.org
> >> Subject: Re: [PATCH v3 35/36] net/wan: make FSL_UCC_HDLC explicitly
> >> depend on PPC32
> >>
> >>
> >>
> >> Le 01/11/2019 à 13:42, Rasmus Villemoes a écrit :
> >>> Currently, FSL_UCC_HDLC depends on QUICC_ENGINE, which in turn
> >> depends
> >>> on PPC32. As preparation for removing the latter and thus allowing
> >>> the core QE code to be built for other architectures, make
> >>> FSL_UCC_HDLC explicitly depend on PPC32.
> >>
> >> Is that really powerpc specific ? Can't the ARM QE perform HDLC on UCC ?
>
> I think the driver would build on ARM. Whether it works I don't know. I know it
> does not build on 64 bit hosts (see kbuild report for v2,23/23).
>
> > No. Actually the HDLC and TDM are the major reason to integrate a QE on
> the ARM based Layerscape SoCs.
>
> [citation needed].
>
> > Since Rasmus doesn't have the hardware to test this feature Qiang Zhao
> probably can help verify the functionality of TDM and we can drop this patch.
>
> No, this patch cannot be dropped. Please see the kbuild complaints for
> v2,23/23 about use of IS_ERR_VALUE on not-sizeof(long) entities. I see kbuild
> has complained about the same thing for v3 since apparently the same thing
> appears in ucc_slow.c. So I'll fix that.
>
> Moreover, as you say and know, I do not have the hardware to test it, so I'm
> not going to even attempt to fix up fsl_ucc_hdlc.c. If Qiang Zhao or somebody
> else can verify that it works just fine on ARM and fixes the allmodconfig
> problem(s), he/she is more than welcome to sign off on a patch that removes
> the CONFIG_PPC32 dependency or replaces it with something else.
>
I tested your v3 patches on ls1043ardb which is arm64 for fsl_ucc_hdlc, it can work,
Only it will put a compile warning, I also made a patch to fix it.
I can send a patch to remove PPC32 dependency when I send my patch to support ARM64.
Or I add my patch in your patchset.
Best Regards
Qiang Zhao
^ permalink raw reply [flat|nested] 120+ messages in thread
* Re: [PATCH v3 35/36] net/wan: make FSL_UCC_HDLC explicitly depend on PPC32
2019-11-05 6:16 ` Qiang Zhao
@ 2019-11-06 7:56 ` Rasmus Villemoes
0 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-06 7:56 UTC (permalink / raw)
To: Qiang Zhao, Leo Li, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood, netdev
On 05/11/2019 07.16, Qiang Zhao wrote:
>
> I tested your v3 patches on ls1043ardb which is arm64 for fsl_ucc_hdlc, it can work,
> Only it will put a compile warning, I also made a patch to fix it.
> I can send a patch to remove PPC32 dependency when I send my patch to support ARM64.
> Or I add my patch in your patchset.
Please send your patch (without whatever Kconfig hunk you needed to add)
with a proper changelog etc. If it looks reasonable (to me, reviewers of
the whole thing obviously also need to agree), I'll include it in my
series and drop adding the PPC32 addition to FSL_UCC_HDLC. Otherwise
I'll keep that and then you can later drop the PPC32 dependency.
Rasmus
^ permalink raw reply [flat|nested] 120+ messages in thread
* [PATCH v3 36/36] soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE
2019-11-01 12:41 ` [PATCH v3 00/36] QUICC Engine support on ARM Rasmus Villemoes
` (34 preceding siblings ...)
2019-11-01 12:42 ` [PATCH v3 35/36] net/wan: make FSL_UCC_HDLC " Rasmus Villemoes
@ 2019-11-01 12:42 ` Rasmus Villemoes
2019-11-02 17:39 ` kbuild test robot
` (3 more replies)
35 siblings, 4 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-01 12:42 UTC (permalink / raw)
To: Qiang Zhao, Li Yang, Christophe Leroy
Cc: linuxppc-dev, linux-arm-kernel, linux-kernel, Scott Wood,
Rasmus Villemoes
The core QE code now also builds for ARM, so replace the FSL_SOC &&
PPC32 dependencies by the more lax requirements OF && HAS_IOMEM.
Signed-off-by: Rasmus Villemoes <linux@rasmusvillemoes.dk>
---
drivers/soc/fsl/qe/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/soc/fsl/qe/Kconfig b/drivers/soc/fsl/qe/Kconfig
index cfa4b2939992..0c5b8b8e46b6 100644
--- a/drivers/soc/fsl/qe/Kconfig
+++ b/drivers/soc/fsl/qe/Kconfig
@@ -5,7 +5,7 @@
config QUICC_ENGINE
bool "QUICC Engine (QE) framework support"
- depends on FSL_SOC && PPC32
+ depends on OF && HAS_IOMEM
select GENERIC_ALLOCATOR
select CRC32
help
--
2.23.0
^ permalink raw reply related [flat|nested] 120+ messages in thread
* Re: [PATCH v3 36/36] soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE
2019-11-01 12:42 ` [PATCH v3 36/36] soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE Rasmus Villemoes
@ 2019-11-02 17:39 ` kbuild test robot
2019-11-14 23:26 ` kbuild test robot
` (2 subsequent siblings)
3 siblings, 0 replies; 120+ messages in thread
From: kbuild test robot @ 2019-11-02 17:39 UTC (permalink / raw)
To: Rasmus Villemoes
Cc: kbuild-all, Qiang Zhao, Li Yang, Christophe Leroy, linuxppc-dev,
linux-arm-kernel, linux-kernel, Scott Wood, Rasmus Villemoes
[-- Attachment #1: Type: text/plain, Size: 42210 bytes --]
Hi Rasmus,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on v5.4-rc5 next-20191031]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Rasmus-Villemoes/QUICC-Engine-support-on-ARM/20191102-234436
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 1204c70d9dcba31164f78ad5d8c88c42335d51f8
config: ia64-allmodconfig (attached as .config)
compiler: ia64-linux-gcc (GCC) 7.4.0
reproduce:
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# save the attached .config to linux build tree
GCC_VERSION=7.4.0 make.cross ARCH=ia64
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
All warnings (new ones prefixed by >>):
In file included from include/linux/kernel.h:11:0,
from drivers/soc/fsl/qe/ucc_slow.c:11:
drivers/soc/fsl/qe/ucc_slow.c: In function 'ucc_slow_init':
include/linux/err.h:22:49: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
#define IS_ERR_VALUE(x) unlikely((unsigned long)(void *)(x) >= (unsigned long)-MAX_ERRNO)
^
include/linux/compiler.h:78:42: note: in definition of macro 'unlikely'
# define unlikely(x) __builtin_expect(!!(x), 0)
^
>> drivers/soc/fsl/qe/ucc_slow.c:182:6: note: in expansion of macro 'IS_ERR_VALUE'
if (IS_ERR_VALUE(uccs->us_pram_offset)) {
^~~~~~~~~~~~
include/linux/err.h:22:49: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
#define IS_ERR_VALUE(x) unlikely((unsigned long)(void *)(x) >= (unsigned long)-MAX_ERRNO)
^
include/linux/compiler.h:78:42: note: in definition of macro 'unlikely'
# define unlikely(x) __builtin_expect(!!(x), 0)
^
drivers/soc/fsl/qe/ucc_slow.c:209:6: note: in expansion of macro 'IS_ERR_VALUE'
if (IS_ERR_VALUE(uccs->rx_base_offset)) {
^~~~~~~~~~~~
include/linux/err.h:22:49: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast]
#define IS_ERR_VALUE(x) unlikely((unsigned long)(void *)(x) >= (unsigned long)-MAX_ERRNO)
^
include/linux/compiler.h:78:42: note: in definition of macro 'unlikely'
# define unlikely(x) __builtin_expect(!!(x), 0)
^
drivers/soc/fsl/qe/ucc_slow.c:220:6: note: in expansion of macro 'IS_ERR_VALUE'
if (IS_ERR_VALUE(uccs->tx_base_offset)) {
^~~~~~~~~~~~
vim +/IS_ERR_VALUE +182 drivers/soc/fsl/qe/ucc_slow.c
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 @11 #include <linux/kernel.h>
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 12 #include <linux/errno.h>
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 13 #include <linux/slab.h>
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 14 #include <linux/stddef.h>
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 15 #include <linux/interrupt.h>
4c35630ccda56e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-05-08 16 #include <linux/err.h>
4b16f8e2d6d642 arch/powerpc/sysdev/qe_lib/ucc_slow.c Paul Gortmaker 2011-07-22 17 #include <linux/export.h>
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 18
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 19 #include <asm/io.h>
7aa1aa6ecec2af drivers/soc/fsl/qe/ucc_slow.c Zhao Qiang 2015-11-30 20 #include <soc/fsl/qe/immap_qe.h>
7aa1aa6ecec2af drivers/soc/fsl/qe/ucc_slow.c Zhao Qiang 2015-11-30 21 #include <soc/fsl/qe/qe.h>
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 22
7aa1aa6ecec2af drivers/soc/fsl/qe/ucc_slow.c Zhao Qiang 2015-11-30 23 #include <soc/fsl/qe/ucc.h>
7aa1aa6ecec2af drivers/soc/fsl/qe/ucc_slow.c Zhao Qiang 2015-11-30 24 #include <soc/fsl/qe/ucc_slow.h>
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 25
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 26 u32 ucc_slow_get_qe_cr_subblock(int uccs_num)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 27 {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 28 switch (uccs_num) {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 29 case 0: return QE_CR_SUBBLOCK_UCCSLOW1;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 30 case 1: return QE_CR_SUBBLOCK_UCCSLOW2;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 31 case 2: return QE_CR_SUBBLOCK_UCCSLOW3;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 32 case 3: return QE_CR_SUBBLOCK_UCCSLOW4;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 33 case 4: return QE_CR_SUBBLOCK_UCCSLOW5;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 34 case 5: return QE_CR_SUBBLOCK_UCCSLOW6;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 35 case 6: return QE_CR_SUBBLOCK_UCCSLOW7;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 36 case 7: return QE_CR_SUBBLOCK_UCCSLOW8;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 37 default: return QE_CR_SUBBLOCK_INVALID;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 38 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 39 }
845cf505cebd15 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2008-01-09 40 EXPORT_SYMBOL(ucc_slow_get_qe_cr_subblock);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 41
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 42 void ucc_slow_graceful_stop_tx(struct ucc_slow_private * uccs)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 43 {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 44 struct ucc_slow_info *us_info = uccs->us_info;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 45 u32 id;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 46
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 47 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 48 qe_issue_cmd(QE_GRACEFUL_STOP_TX, id,
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 49 QE_CR_PROTOCOL_UNSPECIFIED, 0);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 50 }
845cf505cebd15 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2008-01-09 51 EXPORT_SYMBOL(ucc_slow_graceful_stop_tx);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 52
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 53 void ucc_slow_stop_tx(struct ucc_slow_private * uccs)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 54 {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 55 struct ucc_slow_info *us_info = uccs->us_info;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 56 u32 id;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 57
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 58 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 59 qe_issue_cmd(QE_STOP_TX, id, QE_CR_PROTOCOL_UNSPECIFIED, 0);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 60 }
845cf505cebd15 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2008-01-09 61 EXPORT_SYMBOL(ucc_slow_stop_tx);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 62
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 63 void ucc_slow_restart_tx(struct ucc_slow_private * uccs)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 64 {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 65 struct ucc_slow_info *us_info = uccs->us_info;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 66 u32 id;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 67
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 68 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 69 qe_issue_cmd(QE_RESTART_TX, id, QE_CR_PROTOCOL_UNSPECIFIED, 0);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 70 }
845cf505cebd15 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2008-01-09 71 EXPORT_SYMBOL(ucc_slow_restart_tx);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 72
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 73 void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 74 {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 75 struct ucc_slow *us_regs;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 76 u32 gumr_l;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 77
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 78 us_regs = uccs->us_regs;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 79
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 80 /* Enable reception and/or transmission on this UCC. */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 81 gumr_l = qe_ioread32be(&us_regs->gumr_l);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 82 if (mode & COMM_DIR_TX) {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 83 gumr_l |= UCC_SLOW_GUMR_L_ENT;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 84 uccs->enabled_tx = 1;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 85 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 86 if (mode & COMM_DIR_RX) {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 87 gumr_l |= UCC_SLOW_GUMR_L_ENR;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 88 uccs->enabled_rx = 1;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 89 }
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 90 qe_iowrite32be(gumr_l, &us_regs->gumr_l);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 91 }
845cf505cebd15 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2008-01-09 92 EXPORT_SYMBOL(ucc_slow_enable);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 93
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 94 void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 95 {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 96 struct ucc_slow *us_regs;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 97 u32 gumr_l;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 98
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 99 us_regs = uccs->us_regs;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 100
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 101 /* Disable reception and/or transmission on this UCC. */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 102 gumr_l = qe_ioread32be(&us_regs->gumr_l);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 103 if (mode & COMM_DIR_TX) {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 104 gumr_l &= ~UCC_SLOW_GUMR_L_ENT;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 105 uccs->enabled_tx = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 106 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 107 if (mode & COMM_DIR_RX) {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 108 gumr_l &= ~UCC_SLOW_GUMR_L_ENR;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 109 uccs->enabled_rx = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 110 }
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 111 qe_iowrite32be(gumr_l, &us_regs->gumr_l);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 112 }
845cf505cebd15 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2008-01-09 113 EXPORT_SYMBOL(ucc_slow_disable);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 114
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 115 /* Initialize the UCC for Slow operations
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 116 *
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 117 * The caller should initialize the following us_info
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 118 */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 119 int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 120 {
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 121 struct ucc_slow_private *uccs;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 122 u32 i;
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 123 struct ucc_slow __iomem *us_regs;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 124 u32 gumr;
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 125 struct qe_bd *bd;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 126 u32 id;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 127 u32 command;
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 128 int ret = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 129
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 130 if (!us_info)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 131 return -EINVAL;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 132
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 133 /* check if the UCC port number is in range. */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 134 if ((us_info->ucc_num < 0) || (us_info->ucc_num > UCC_MAX_NUM - 1)) {
e48b1b452ff630 arch/powerpc/sysdev/qe_lib/ucc_slow.c Harvey Harrison 2008-03-29 135 printk(KERN_ERR "%s: illegal UCC number\n", __func__);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 136 return -EINVAL;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 137 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 138
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 139 /*
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 140 * Set mrblr
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 141 * Check that 'max_rx_buf_length' is properly aligned (4), unless
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 142 * rfw is 1, meaning that QE accepts one byte at a time, unlike normal
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 143 * case when QE accepts 32 bits at a time.
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 144 */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 145 if ((!us_info->rfw) &&
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 146 (us_info->max_rx_buf_length & (UCC_SLOW_MRBLR_ALIGNMENT - 1))) {
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 147 printk(KERN_ERR "max_rx_buf_length not aligned.\n");
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 148 return -EINVAL;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 149 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 150
f8485350c22b25 arch/powerpc/sysdev/qe_lib/ucc_slow.c Yan Burman 2006-12-02 151 uccs = kzalloc(sizeof(struct ucc_slow_private), GFP_KERNEL);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 152 if (!uccs) {
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 153 printk(KERN_ERR "%s: Cannot allocate private data\n",
e48b1b452ff630 arch/powerpc/sysdev/qe_lib/ucc_slow.c Harvey Harrison 2008-03-29 154 __func__);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 155 return -ENOMEM;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 156 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 157
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 158 /* Fill slow UCC structure */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 159 uccs->us_info = us_info;
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 160 /* Set the PHY base address */
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 161 uccs->us_regs = ioremap(us_info->regs, sizeof(struct ucc_slow));
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 162 if (uccs->us_regs == NULL) {
e48b1b452ff630 arch/powerpc/sysdev/qe_lib/ucc_slow.c Harvey Harrison 2008-03-29 163 printk(KERN_ERR "%s: Cannot map UCC registers\n", __func__);
61a4e9e91dd391 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2008-08-20 164 kfree(uccs);
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 165 return -ENOMEM;
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 166 }
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 167
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 168 uccs->saved_uccm = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 169 uccs->p_rx_frame = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 170 us_regs = uccs->us_regs;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 171 uccs->p_ucce = (u16 *) & (us_regs->ucce);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 172 uccs->p_uccm = (u16 *) & (us_regs->uccm);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 173 #ifdef STATISTICS
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 174 uccs->rx_frames = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 175 uccs->tx_frames = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 176 uccs->rx_discarded = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 177 #endif /* STATISTICS */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 178
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 179 /* Get PRAM base */
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 180 uccs->us_pram_offset =
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 181 qe_muram_alloc(UCC_SLOW_PRAM_SIZE, ALIGNMENT_OF_UCC_SLOW_PRAM);
4c35630ccda56e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-05-08 @182 if (IS_ERR_VALUE(uccs->us_pram_offset)) {
e48b1b452ff630 arch/powerpc/sysdev/qe_lib/ucc_slow.c Harvey Harrison 2008-03-29 183 printk(KERN_ERR "%s: cannot allocate MURAM for PRAM", __func__);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 184 ucc_slow_free(uccs);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 185 return -ENOMEM;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 186 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 187 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 188 qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, id, us_info->protocol,
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 189 uccs->us_pram_offset);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 190
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 191 uccs->us_pram = qe_muram_addr(uccs->us_pram_offset);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 192
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 193 /* Set UCC to slow type */
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 194 ret = ucc_set_type(us_info->ucc_num, UCC_SPEED_TYPE_SLOW);
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 195 if (ret) {
e48b1b452ff630 arch/powerpc/sysdev/qe_lib/ucc_slow.c Harvey Harrison 2008-03-29 196 printk(KERN_ERR "%s: cannot set UCC type", __func__);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 197 ucc_slow_free(uccs);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 198 return ret;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 199 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 200
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 201 qe_iowrite16be(us_info->max_rx_buf_length, &uccs->us_pram->mrblr);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 202
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 203 INIT_LIST_HEAD(&uccs->confQ);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 204
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 205 /* Allocate BDs. */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 206 uccs->rx_base_offset =
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 207 qe_muram_alloc(us_info->rx_bd_ring_len * sizeof(struct qe_bd),
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 208 QE_ALIGNMENT_OF_BD);
4c35630ccda56e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-05-08 209 if (IS_ERR_VALUE(uccs->rx_base_offset)) {
e48b1b452ff630 arch/powerpc/sysdev/qe_lib/ucc_slow.c Harvey Harrison 2008-03-29 210 printk(KERN_ERR "%s: cannot allocate %u RX BDs\n", __func__,
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 211 us_info->rx_bd_ring_len);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 212 uccs->rx_base_offset = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 213 ucc_slow_free(uccs);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 214 return -ENOMEM;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 215 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 216
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 217 uccs->tx_base_offset =
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 218 qe_muram_alloc(us_info->tx_bd_ring_len * sizeof(struct qe_bd),
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 219 QE_ALIGNMENT_OF_BD);
4c35630ccda56e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-05-08 220 if (IS_ERR_VALUE(uccs->tx_base_offset)) {
e48b1b452ff630 arch/powerpc/sysdev/qe_lib/ucc_slow.c Harvey Harrison 2008-03-29 221 printk(KERN_ERR "%s: cannot allocate TX BDs", __func__);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 222 uccs->tx_base_offset = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 223 ucc_slow_free(uccs);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 224 return -ENOMEM;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 225 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 226
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 227 /* Init Tx bds */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 228 bd = uccs->confBd = uccs->tx_bd = qe_muram_addr(uccs->tx_base_offset);
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 229 for (i = 0; i < us_info->tx_bd_ring_len - 1; i++) {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 230 /* clear bd buffer */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 231 qe_iowrite32be(0, &bd->buf);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 232 /* set bd status and length */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 233 qe_iowrite32be(0, (u32 *)bd);
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 234 bd++;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 235 }
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 236 /* for last BD set Wrap bit */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 237 qe_iowrite32be(0, &bd->buf);
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 238 qe_iowrite32be(cpu_to_be32(T_W), (u32 *)bd);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 239
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 240 /* Init Rx bds */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 241 bd = uccs->rx_bd = qe_muram_addr(uccs->rx_base_offset);
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 242 for (i = 0; i < us_info->rx_bd_ring_len - 1; i++) {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 243 /* set bd status and length */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 244 qe_iowrite32be(0, (u32 *)bd);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 245 /* clear bd buffer */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 246 qe_iowrite32be(0, &bd->buf);
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 247 bd++;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 248 }
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 249 /* for last BD set Wrap bit */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 250 qe_iowrite32be(cpu_to_be32(R_W), (u32 *)bd);
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 251 qe_iowrite32be(0, &bd->buf);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 252
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 253 /* Set GUMR (For more details see the hardware spec.). */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 254 /* gumr_h */
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 255 gumr = us_info->tcrc;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 256 if (us_info->cdp)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 257 gumr |= UCC_SLOW_GUMR_H_CDP;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 258 if (us_info->ctsp)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 259 gumr |= UCC_SLOW_GUMR_H_CTSP;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 260 if (us_info->cds)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 261 gumr |= UCC_SLOW_GUMR_H_CDS;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 262 if (us_info->ctss)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 263 gumr |= UCC_SLOW_GUMR_H_CTSS;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 264 if (us_info->tfl)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 265 gumr |= UCC_SLOW_GUMR_H_TFL;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 266 if (us_info->rfw)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 267 gumr |= UCC_SLOW_GUMR_H_RFW;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 268 if (us_info->txsy)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 269 gumr |= UCC_SLOW_GUMR_H_TXSY;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 270 if (us_info->rtsm)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 271 gumr |= UCC_SLOW_GUMR_H_RTSM;
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 272 qe_iowrite32be(gumr, &us_regs->gumr_h);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 273
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 274 /* gumr_l */
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 275 gumr = us_info->tdcr | us_info->rdcr | us_info->tenc | us_info->renc |
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 276 us_info->diag | us_info->mode;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 277 if (us_info->tci)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 278 gumr |= UCC_SLOW_GUMR_L_TCI;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 279 if (us_info->rinv)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 280 gumr |= UCC_SLOW_GUMR_L_RINV;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 281 if (us_info->tinv)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 282 gumr |= UCC_SLOW_GUMR_L_TINV;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 283 if (us_info->tend)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 284 gumr |= UCC_SLOW_GUMR_L_TEND;
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 285 qe_iowrite32be(gumr, &us_regs->gumr_l);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 286
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 287 /* Function code registers */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 288
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 289 /* if the data is in cachable memory, the 'global' */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 290 /* in the function code should be set. */
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 291 uccs->us_pram->tbmr = UCC_BMR_BO_BE;
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 292 uccs->us_pram->rbmr = UCC_BMR_BO_BE;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 293
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 294 /* rbase, tbase are offsets from MURAM base */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 295 qe_iowrite16be(uccs->rx_base_offset, &uccs->us_pram->rbase);
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 296 qe_iowrite16be(uccs->tx_base_offset, &uccs->us_pram->tbase);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 297
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 298 /* Mux clocking */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 299 /* Grant Support */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 300 ucc_set_qe_mux_grant(us_info->ucc_num, us_info->grant_support);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 301 /* Breakpoint Support */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 302 ucc_set_qe_mux_bkpt(us_info->ucc_num, us_info->brkpt_support);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 303 /* Set Tsa or NMSI mode. */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 304 ucc_set_qe_mux_tsa(us_info->ucc_num, us_info->tsa);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 305 /* If NMSI (not Tsa), set Tx and Rx clock. */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 306 if (!us_info->tsa) {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 307 /* Rx clock routing */
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 308 if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->rx_clock,
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 309 COMM_DIR_RX)) {
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 310 printk(KERN_ERR "%s: illegal value for RX clock\n",
e48b1b452ff630 arch/powerpc/sysdev/qe_lib/ucc_slow.c Harvey Harrison 2008-03-29 311 __func__);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 312 ucc_slow_free(uccs);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 313 return -EINVAL;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 314 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 315 /* Tx clock routing */
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 316 if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->tx_clock,
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 317 COMM_DIR_TX)) {
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 318 printk(KERN_ERR "%s: illegal value for TX clock\n",
e48b1b452ff630 arch/powerpc/sysdev/qe_lib/ucc_slow.c Harvey Harrison 2008-03-29 319 __func__);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 320 ucc_slow_free(uccs);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 321 return -EINVAL;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 322 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 323 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 324
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 325 /* Set interrupt mask register at UCC level. */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 326 qe_iowrite16be(us_info->uccm_mask, &us_regs->uccm);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 327
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 328 /* First, clear anything pending at UCC level,
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 329 * otherwise, old garbage may come through
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 330 * as soon as the dam is opened. */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 331
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 332 /* Writing '1' clears */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 333 qe_iowrite16be(0xffff, &us_regs->ucce);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 334
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 335 /* Issue QE Init command */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 336 if (us_info->init_tx && us_info->init_rx)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 337 command = QE_INIT_TX_RX;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 338 else if (us_info->init_tx)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 339 command = QE_INIT_TX;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 340 else
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 341 command = QE_INIT_RX; /* We know at least one is TRUE */
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 342
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 343 qe_issue_cmd(command, id, us_info->protocol, 0);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 344
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 345 *uccs_ret = uccs;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 346 return 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 347 }
845cf505cebd15 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2008-01-09 348 EXPORT_SYMBOL(ucc_slow_init);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 349
:::::: The code at line 182 was first introduced by commit
:::::: 4c35630ccda56ed494f6102d2e147fefe14b78d2 [POWERPC] Change rheap functions to use ulongs instead of pointers
:::::: TO: Timur Tabi <timur@freescale.com>
:::::: CC: Kumar Gala <galak@kernel.crashing.org>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
[-- Attachment #2: .config.gz --]
[-- Type: application/gzip, Size: 54935 bytes --]
^ permalink raw reply [flat|nested] 120+ messages in thread
* Re: [PATCH v3 36/36] soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE
2019-11-01 12:42 ` [PATCH v3 36/36] soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE Rasmus Villemoes
2019-11-02 17:39 ` kbuild test robot
@ 2019-11-14 23:26 ` kbuild test robot
2019-11-14 23:26 ` [RFC PATCH] soc: fsl: qe: qe_uart_set_mctrl() can be static kbuild test robot
2019-11-15 13:31 ` [PATCH v3 36/36] soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE kbuild test robot
3 siblings, 0 replies; 120+ messages in thread
From: kbuild test robot @ 2019-11-14 23:26 UTC (permalink / raw)
To: Rasmus Villemoes
Cc: kbuild-all, Qiang Zhao, Li Yang, Christophe Leroy, linuxppc-dev,
linux-arm-kernel, linux-kernel, Scott Wood, Rasmus Villemoes
Hi Rasmus,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on v5.4-rc7 next-20191114]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Rasmus-Villemoes/QUICC-Engine-support-on-ARM/20191102-234436
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 1204c70d9dcba31164f78ad5d8c88c42335d51f8
reproduce:
# apt-get install sparse
# sparse version: v0.6.1-31-gfd3528a-dirty
make ARCH=x86_64 allmodconfig
make C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__'
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
sparse warnings: (new ones prefixed by >>)
>> drivers/soc/fsl/qe/ucc_slow.c:78:17: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected struct ucc_slow *us_regs @@ got struct ucc_slow [nstruct ucc_slow *us_regs @@
>> drivers/soc/fsl/qe/ucc_slow.c:78:17: sparse: expected struct ucc_slow *us_regs
>> drivers/soc/fsl/qe/ucc_slow.c:78:17: sparse: got struct ucc_slow [noderef] <asn:2> *us_regs
>> drivers/soc/fsl/qe/ucc_slow.c:81:18: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
>> drivers/soc/fsl/qe/ucc_slow.c:81:18: sparse: expected void [noderef] <asn:2> *
>> drivers/soc/fsl/qe/ucc_slow.c:81:18: sparse: got restricted __be32 *
drivers/soc/fsl/qe/ucc_slow.c:90:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/soc/fsl/qe/ucc_slow.c:90:9: sparse: expected void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:90:9: sparse: got restricted __be32 *
drivers/soc/fsl/qe/ucc_slow.c:99:17: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected struct ucc_slow *us_regs @@ got struct ucc_slow [nstruct ucc_slow *us_regs @@
drivers/soc/fsl/qe/ucc_slow.c:99:17: sparse: expected struct ucc_slow *us_regs
drivers/soc/fsl/qe/ucc_slow.c:99:17: sparse: got struct ucc_slow [noderef] <asn:2> *us_regs
drivers/soc/fsl/qe/ucc_slow.c:102:18: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/soc/fsl/qe/ucc_slow.c:102:18: sparse: expected void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:102:18: sparse: got restricted __be32 *
drivers/soc/fsl/qe/ucc_slow.c:111:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/soc/fsl/qe/ucc_slow.c:111:9: sparse: expected void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:111:9: sparse: got restricted __be32 *
>> drivers/soc/fsl/qe/ucc_slow.c:169:28: sparse: sparse: Using plain integer as NULL pointer
>> drivers/soc/fsl/qe/ucc_slow.c:171:25: sparse: sparse: cast removes address space '<asn:2>' of expression
drivers/soc/fsl/qe/ucc_slow.c:172:25: sparse: sparse: cast removes address space '<asn:2>' of expression
>> drivers/soc/fsl/qe/ucc_slow.c:191:23: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected struct ucc_slow_pram *us_pram @@ got vostruct ucc_slow_pram *us_pram @@
>> drivers/soc/fsl/qe/ucc_slow.c:191:23: sparse: expected struct ucc_slow_pram *us_pram
>> drivers/soc/fsl/qe/ucc_slow.c:191:23: sparse: got void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:201:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/soc/fsl/qe/ucc_slow.c:201:9: sparse: expected void [noderef] <asn:2> *
>> drivers/soc/fsl/qe/ucc_slow.c:201:9: sparse: got restricted __be16 *
>> drivers/soc/fsl/qe/ucc_slow.c:228:41: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected struct qe_bd *tx_bd @@ got void [nodestruct qe_bd *tx_bd @@
>> drivers/soc/fsl/qe/ucc_slow.c:228:41: sparse: expected struct qe_bd *tx_bd
drivers/soc/fsl/qe/ucc_slow.c:228:41: sparse: got void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:231:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/soc/fsl/qe/ucc_slow.c:231:17: sparse: expected void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:231:17: sparse: got restricted __be32 *
>> drivers/soc/fsl/qe/ucc_slow.c:233:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got uvoid [noderef] <asn:2> * @@
drivers/soc/fsl/qe/ucc_slow.c:233:17: sparse: expected void [noderef] <asn:2> *
>> drivers/soc/fsl/qe/ucc_slow.c:233:17: sparse: got unsigned int [usertype] *
drivers/soc/fsl/qe/ucc_slow.c:237:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/soc/fsl/qe/ucc_slow.c:237:9: sparse: expected void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:237:9: sparse: got restricted __be32 *
>> drivers/soc/fsl/qe/ucc_slow.c:238:9: sparse: sparse: incorrect type in argument 1 (different base types) @@ expected unsigned int [usertype] @@ got restrunsigned int [usertype] @@
>> drivers/soc/fsl/qe/ucc_slow.c:238:9: sparse: expected unsigned int [usertype]
>> drivers/soc/fsl/qe/ucc_slow.c:238:9: sparse: got restricted __be32 [usertype]
drivers/soc/fsl/qe/ucc_slow.c:238:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got uvoid [noderef] <asn:2> * @@
drivers/soc/fsl/qe/ucc_slow.c:238:9: sparse: expected void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:238:9: sparse: got unsigned int [usertype] *
>> drivers/soc/fsl/qe/ucc_slow.c:241:26: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected struct qe_bd *rx_bd @@ got void [nodestruct qe_bd *rx_bd @@
>> drivers/soc/fsl/qe/ucc_slow.c:241:26: sparse: expected struct qe_bd *rx_bd
drivers/soc/fsl/qe/ucc_slow.c:241:26: sparse: got void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:244:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got uvoid [noderef] <asn:2> * @@
drivers/soc/fsl/qe/ucc_slow.c:244:17: sparse: expected void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:244:17: sparse: got unsigned int [usertype] *
drivers/soc/fsl/qe/ucc_slow.c:246:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/soc/fsl/qe/ucc_slow.c:246:17: sparse: expected void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:246:17: sparse: got restricted __be32 *
drivers/soc/fsl/qe/ucc_slow.c:250:9: sparse: sparse: incorrect type in argument 1 (different base types) @@ expected unsigned int [usertype] @@ got restrunsigned int [usertype] @@
drivers/soc/fsl/qe/ucc_slow.c:250:9: sparse: expected unsigned int [usertype]
drivers/soc/fsl/qe/ucc_slow.c:250:9: sparse: got restricted __be32 [usertype]
drivers/soc/fsl/qe/ucc_slow.c:250:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got uvoid [noderef] <asn:2> * @@
drivers/soc/fsl/qe/ucc_slow.c:250:9: sparse: expected void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:250:9: sparse: got unsigned int [usertype] *
drivers/soc/fsl/qe/ucc_slow.c:251:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/soc/fsl/qe/ucc_slow.c:251:9: sparse: expected void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:251:9: sparse: got restricted __be32 *
>> drivers/soc/fsl/qe/ucc_slow.c:275:39: sparse: sparse: mixing different enum types:
>> drivers/soc/fsl/qe/ucc_slow.c:275:39: sparse: unsigned int enum ucc_slow_tx_oversampling_rate
>> drivers/soc/fsl/qe/ucc_slow.c:275:39: sparse: unsigned int enum ucc_slow_rx_oversampling_rate
drivers/soc/fsl/qe/ucc_slow.c:295:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/soc/fsl/qe/ucc_slow.c:295:9: sparse: expected void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:295:9: sparse: got restricted __be16 *
drivers/soc/fsl/qe/ucc_slow.c:296:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/soc/fsl/qe/ucc_slow.c:296:9: sparse: expected void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:296:9: sparse: got restricted __be16 *
--
>> drivers/tty/serial/ucc_uart.c:264:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
>> drivers/tty/serial/ucc_uart.c:264:21: sparse: expected void [noderef] <asn:2> *
>> drivers/tty/serial/ucc_uart.c:264:21: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:268:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:268:21: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:268:21: sparse: got restricted __be16 *
>> drivers/tty/serial/ucc_uart.c:286:6: sparse: sparse: symbol 'qe_uart_set_mctrl' was not declared. Should it be static?
drivers/tty/serial/ucc_uart.c:349:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:349:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:349:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:350:17: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:350:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:350:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:350:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:350:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:350:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:352:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:352:21: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:352:21: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:371:18: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:371:18: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:371:18: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:384:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:384:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:384:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:385:17: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:385:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:385:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:385:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:385:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:385:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:388:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:388:21: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:388:21: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:476:26: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:476:26: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:476:26: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:483:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:483:21: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:483:21: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:514:17: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:514:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:514:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:514:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:514:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:514:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:517:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:517:21: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:517:21: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:608:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:608:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:608:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:609:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:609:17: sparse: expected void [noderef] <asn:2> *
>> drivers/tty/serial/ucc_uart.c:609:17: sparse: got restricted __be32 *
drivers/tty/serial/ucc_uart.c:610:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:610:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:610:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:616:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:616:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:616:9: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:617:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:617:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:617:9: sparse: got restricted __be32 *
drivers/tty/serial/ucc_uart.c:618:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:618:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:618:9: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:629:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:629:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:629:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:630:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:630:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:630:17: sparse: got restricted __be32 *
drivers/tty/serial/ucc_uart.c:631:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:631:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:631:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:641:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:641:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:641:9: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:642:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:642:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:642:9: sparse: got restricted __be32 *
drivers/tty/serial/ucc_uart.c:643:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:643:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:643:9: sparse: got restricted __be16 *
>> drivers/tty/serial/ucc_uart.c:657:46: sparse: sparse: incorrect type in initializer (different address spaces) @@ expected struct ucc_uart_pram *uccup @@ got struct ucc_uart_prstruct ucc_uart_pram *uccup @@
>> drivers/tty/serial/ucc_uart.c:657:46: sparse: expected struct ucc_uart_pram *uccup
>> drivers/tty/serial/ucc_uart.c:657:46: sparse: got struct ucc_uart_pram [noderef] <asn:2> *uccup
>> drivers/tty/serial/ucc_uart.c:665:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got eref] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:665:9: sparse: expected void [noderef] <asn:2> *
>> drivers/tty/serial/ucc_uart.c:665:9: sparse: got unsigned char *
drivers/tty/serial/ucc_uart.c:666:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got eref] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:666:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:666:9: sparse: got unsigned char *
drivers/tty/serial/ucc_uart.c:667:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:667:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:667:9: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:668:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:668:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:668:9: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:669:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:669:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:669:9: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:670:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:670:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:670:9: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:671:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:671:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:671:9: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:672:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:672:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:672:9: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:673:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:673:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:673:9: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:674:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:674:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:674:9: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:675:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:675:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:675:9: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:676:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:676:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:676:9: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:678:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:678:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:678:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:679:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:679:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:679:9: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:717:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:717:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:717:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:718:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:718:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:718:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:719:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:719:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:719:17: sparse: got restricted __be32 *
drivers/tty/serial/ucc_uart.c:720:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:720:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:720:17: sparse: got restricted __be32 *
drivers/tty/serial/ucc_uart.c:721:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got eref] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:721:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:721:17: sparse: got unsigned char *
drivers/tty/serial/ucc_uart.c:722:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got eref] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:722:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:722:17: sparse: got unsigned char *
drivers/tty/serial/ucc_uart.c:723:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:723:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:723:17: sparse: got restricted __be32 *
drivers/tty/serial/ucc_uart.c:724:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got eref] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:724:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:724:17: sparse: got unsigned char *
drivers/tty/serial/ucc_uart.c:725:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:725:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:725:17: sparse: got restricted __be32 *
drivers/tty/serial/ucc_uart.c:726:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got eref] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:726:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:726:17: sparse: got unsigned char *
drivers/tty/serial/ucc_uart.c:728:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got eref] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:728:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:728:17: sparse: got unsigned char *
drivers/tty/serial/ucc_uart.c:730:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:730:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:730:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:731:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got eref] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:731:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:731:17: sparse: got unsigned char *
drivers/tty/serial/ucc_uart.c:732:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:732:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:732:17: sparse: got restricted __be16 *
>> drivers/tty/serial/ucc_uart.c:1004:24: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected struct ucc_uart_pram [noderef] <asn:2> *uccup @@ got am [noderef] <asn:2> *uccup @@
>> drivers/tty/serial/ucc_uart.c:1004:24: sparse: expected struct ucc_uart_pram [noderef] <asn:2> *uccup
>> drivers/tty/serial/ucc_uart.c:1004:24: sparse: got struct ucc_uart_pram *
Please review and possibly fold the followup patch.
vim +78 drivers/soc/fsl/qe/ucc_slow.c
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 72
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 73 void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 74 {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 75 struct ucc_slow *us_regs;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 76 u32 gumr_l;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 77
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 @78 us_regs = uccs->us_regs;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 79
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 80 /* Enable reception and/or transmission on this UCC. */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 @81 gumr_l = qe_ioread32be(&us_regs->gumr_l);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 82 if (mode & COMM_DIR_TX) {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 83 gumr_l |= UCC_SLOW_GUMR_L_ENT;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 84 uccs->enabled_tx = 1;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 85 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 86 if (mode & COMM_DIR_RX) {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 87 gumr_l |= UCC_SLOW_GUMR_L_ENR;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 88 uccs->enabled_rx = 1;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 89 }
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 90 qe_iowrite32be(gumr_l, &us_regs->gumr_l);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 91 }
845cf505cebd15 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2008-01-09 92 EXPORT_SYMBOL(ucc_slow_enable);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 93
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 94 void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 95 {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 96 struct ucc_slow *us_regs;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 97 u32 gumr_l;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 98
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 @99 us_regs = uccs->us_regs;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 100
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 101 /* Disable reception and/or transmission on this UCC. */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 @102 gumr_l = qe_ioread32be(&us_regs->gumr_l);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 103 if (mode & COMM_DIR_TX) {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 104 gumr_l &= ~UCC_SLOW_GUMR_L_ENT;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 105 uccs->enabled_tx = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 106 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 107 if (mode & COMM_DIR_RX) {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 108 gumr_l &= ~UCC_SLOW_GUMR_L_ENR;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 109 uccs->enabled_rx = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 110 }
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 @111 qe_iowrite32be(gumr_l, &us_regs->gumr_l);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 112 }
845cf505cebd15 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2008-01-09 113 EXPORT_SYMBOL(ucc_slow_disable);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 114
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 115 /* Initialize the UCC for Slow operations
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 116 *
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 117 * The caller should initialize the following us_info
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 118 */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 119 int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 120 {
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 121 struct ucc_slow_private *uccs;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 122 u32 i;
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 123 struct ucc_slow __iomem *us_regs;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 124 u32 gumr;
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 125 struct qe_bd *bd;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 126 u32 id;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 127 u32 command;
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 128 int ret = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 129
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 130 if (!us_info)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 131 return -EINVAL;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 132
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 133 /* check if the UCC port number is in range. */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 134 if ((us_info->ucc_num < 0) || (us_info->ucc_num > UCC_MAX_NUM - 1)) {
e48b1b452ff630 arch/powerpc/sysdev/qe_lib/ucc_slow.c Harvey Harrison 2008-03-29 135 printk(KERN_ERR "%s: illegal UCC number\n", __func__);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 136 return -EINVAL;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 137 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 138
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 139 /*
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 140 * Set mrblr
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 141 * Check that 'max_rx_buf_length' is properly aligned (4), unless
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 142 * rfw is 1, meaning that QE accepts one byte at a time, unlike normal
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 143 * case when QE accepts 32 bits at a time.
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 144 */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 145 if ((!us_info->rfw) &&
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 146 (us_info->max_rx_buf_length & (UCC_SLOW_MRBLR_ALIGNMENT - 1))) {
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 147 printk(KERN_ERR "max_rx_buf_length not aligned.\n");
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 148 return -EINVAL;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 149 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 150
f8485350c22b25 arch/powerpc/sysdev/qe_lib/ucc_slow.c Yan Burman 2006-12-02 151 uccs = kzalloc(sizeof(struct ucc_slow_private), GFP_KERNEL);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 152 if (!uccs) {
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 153 printk(KERN_ERR "%s: Cannot allocate private data\n",
e48b1b452ff630 arch/powerpc/sysdev/qe_lib/ucc_slow.c Harvey Harrison 2008-03-29 154 __func__);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 155 return -ENOMEM;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 156 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 157
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 158 /* Fill slow UCC structure */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 159 uccs->us_info = us_info;
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 160 /* Set the PHY base address */
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 161 uccs->us_regs = ioremap(us_info->regs, sizeof(struct ucc_slow));
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 162 if (uccs->us_regs == NULL) {
e48b1b452ff630 arch/powerpc/sysdev/qe_lib/ucc_slow.c Harvey Harrison 2008-03-29 163 printk(KERN_ERR "%s: Cannot map UCC registers\n", __func__);
61a4e9e91dd391 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2008-08-20 164 kfree(uccs);
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 165 return -ENOMEM;
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 166 }
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 167
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 168 uccs->saved_uccm = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 @169 uccs->p_rx_frame = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 170 us_regs = uccs->us_regs;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 @171 uccs->p_ucce = (u16 *) & (us_regs->ucce);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 172 uccs->p_uccm = (u16 *) & (us_regs->uccm);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 173 #ifdef STATISTICS
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 174 uccs->rx_frames = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 175 uccs->tx_frames = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 176 uccs->rx_discarded = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 177 #endif /* STATISTICS */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 178
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 179 /* Get PRAM base */
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 180 uccs->us_pram_offset =
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 181 qe_muram_alloc(UCC_SLOW_PRAM_SIZE, ALIGNMENT_OF_UCC_SLOW_PRAM);
4c35630ccda56e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-05-08 182 if (IS_ERR_VALUE(uccs->us_pram_offset)) {
e48b1b452ff630 arch/powerpc/sysdev/qe_lib/ucc_slow.c Harvey Harrison 2008-03-29 183 printk(KERN_ERR "%s: cannot allocate MURAM for PRAM", __func__);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 184 ucc_slow_free(uccs);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 185 return -ENOMEM;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 186 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 187 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 188 qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, id, us_info->protocol,
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 189 uccs->us_pram_offset);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 190
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 @191 uccs->us_pram = qe_muram_addr(uccs->us_pram_offset);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 192
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 193 /* Set UCC to slow type */
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 194 ret = ucc_set_type(us_info->ucc_num, UCC_SPEED_TYPE_SLOW);
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 195 if (ret) {
e48b1b452ff630 arch/powerpc/sysdev/qe_lib/ucc_slow.c Harvey Harrison 2008-03-29 196 printk(KERN_ERR "%s: cannot set UCC type", __func__);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 197 ucc_slow_free(uccs);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 198 return ret;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 199 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 200
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 @201 qe_iowrite16be(us_info->max_rx_buf_length, &uccs->us_pram->mrblr);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 202
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 203 INIT_LIST_HEAD(&uccs->confQ);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 204
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 205 /* Allocate BDs. */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 206 uccs->rx_base_offset =
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 207 qe_muram_alloc(us_info->rx_bd_ring_len * sizeof(struct qe_bd),
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 208 QE_ALIGNMENT_OF_BD);
4c35630ccda56e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-05-08 209 if (IS_ERR_VALUE(uccs->rx_base_offset)) {
e48b1b452ff630 arch/powerpc/sysdev/qe_lib/ucc_slow.c Harvey Harrison 2008-03-29 210 printk(KERN_ERR "%s: cannot allocate %u RX BDs\n", __func__,
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 211 us_info->rx_bd_ring_len);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 212 uccs->rx_base_offset = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 213 ucc_slow_free(uccs);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 214 return -ENOMEM;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 215 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 216
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 217 uccs->tx_base_offset =
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 218 qe_muram_alloc(us_info->tx_bd_ring_len * sizeof(struct qe_bd),
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 219 QE_ALIGNMENT_OF_BD);
4c35630ccda56e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-05-08 220 if (IS_ERR_VALUE(uccs->tx_base_offset)) {
e48b1b452ff630 arch/powerpc/sysdev/qe_lib/ucc_slow.c Harvey Harrison 2008-03-29 221 printk(KERN_ERR "%s: cannot allocate TX BDs", __func__);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 222 uccs->tx_base_offset = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 223 ucc_slow_free(uccs);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 224 return -ENOMEM;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 225 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 226
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 227 /* Init Tx bds */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 @228 bd = uccs->confBd = uccs->tx_bd = qe_muram_addr(uccs->tx_base_offset);
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 229 for (i = 0; i < us_info->tx_bd_ring_len - 1; i++) {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 230 /* clear bd buffer */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 @231 qe_iowrite32be(0, &bd->buf);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 232 /* set bd status and length */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 @233 qe_iowrite32be(0, (u32 *)bd);
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 234 bd++;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 235 }
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 236 /* for last BD set Wrap bit */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 @237 qe_iowrite32be(0, &bd->buf);
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 @238 qe_iowrite32be(cpu_to_be32(T_W), (u32 *)bd);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 239
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 240 /* Init Rx bds */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 @241 bd = uccs->rx_bd = qe_muram_addr(uccs->rx_base_offset);
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 242 for (i = 0; i < us_info->rx_bd_ring_len - 1; i++) {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 243 /* set bd status and length */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 244 qe_iowrite32be(0, (u32 *)bd);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 245 /* clear bd buffer */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 246 qe_iowrite32be(0, &bd->buf);
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 247 bd++;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 248 }
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 249 /* for last BD set Wrap bit */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 @250 qe_iowrite32be(cpu_to_be32(R_W), (u32 *)bd);
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 251 qe_iowrite32be(0, &bd->buf);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 252
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 253 /* Set GUMR (For more details see the hardware spec.). */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 254 /* gumr_h */
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 255 gumr = us_info->tcrc;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 256 if (us_info->cdp)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 257 gumr |= UCC_SLOW_GUMR_H_CDP;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 258 if (us_info->ctsp)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 259 gumr |= UCC_SLOW_GUMR_H_CTSP;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 260 if (us_info->cds)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 261 gumr |= UCC_SLOW_GUMR_H_CDS;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 262 if (us_info->ctss)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 263 gumr |= UCC_SLOW_GUMR_H_CTSS;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 264 if (us_info->tfl)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 265 gumr |= UCC_SLOW_GUMR_H_TFL;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 266 if (us_info->rfw)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 267 gumr |= UCC_SLOW_GUMR_H_RFW;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 268 if (us_info->txsy)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 269 gumr |= UCC_SLOW_GUMR_H_TXSY;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 270 if (us_info->rtsm)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 271 gumr |= UCC_SLOW_GUMR_H_RTSM;
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 272 qe_iowrite32be(gumr, &us_regs->gumr_h);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 273
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 274 /* gumr_l */
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 @275 gumr = us_info->tdcr | us_info->rdcr | us_info->tenc | us_info->renc |
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 276 us_info->diag | us_info->mode;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 277 if (us_info->tci)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 278 gumr |= UCC_SLOW_GUMR_L_TCI;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 279 if (us_info->rinv)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 280 gumr |= UCC_SLOW_GUMR_L_RINV;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 281 if (us_info->tinv)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 282 gumr |= UCC_SLOW_GUMR_L_TINV;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 283 if (us_info->tend)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 284 gumr |= UCC_SLOW_GUMR_L_TEND;
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 285 qe_iowrite32be(gumr, &us_regs->gumr_l);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 286
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 287 /* Function code registers */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 288
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 289 /* if the data is in cachable memory, the 'global' */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 290 /* in the function code should be set. */
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 291 uccs->us_pram->tbmr = UCC_BMR_BO_BE;
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 292 uccs->us_pram->rbmr = UCC_BMR_BO_BE;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 293
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 294 /* rbase, tbase are offsets from MURAM base */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 295 qe_iowrite16be(uccs->rx_base_offset, &uccs->us_pram->rbase);
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 296 qe_iowrite16be(uccs->tx_base_offset, &uccs->us_pram->tbase);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 297
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 298 /* Mux clocking */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 299 /* Grant Support */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 300 ucc_set_qe_mux_grant(us_info->ucc_num, us_info->grant_support);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 301 /* Breakpoint Support */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 302 ucc_set_qe_mux_bkpt(us_info->ucc_num, us_info->brkpt_support);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 303 /* Set Tsa or NMSI mode. */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 304 ucc_set_qe_mux_tsa(us_info->ucc_num, us_info->tsa);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 305 /* If NMSI (not Tsa), set Tx and Rx clock. */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 306 if (!us_info->tsa) {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 307 /* Rx clock routing */
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 308 if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->rx_clock,
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 309 COMM_DIR_RX)) {
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 310 printk(KERN_ERR "%s: illegal value for RX clock\n",
e48b1b452ff630 arch/powerpc/sysdev/qe_lib/ucc_slow.c Harvey Harrison 2008-03-29 311 __func__);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 312 ucc_slow_free(uccs);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 313 return -EINVAL;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 314 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 315 /* Tx clock routing */
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 316 if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->tx_clock,
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 317 COMM_DIR_TX)) {
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 318 printk(KERN_ERR "%s: illegal value for TX clock\n",
e48b1b452ff630 arch/powerpc/sysdev/qe_lib/ucc_slow.c Harvey Harrison 2008-03-29 319 __func__);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 320 ucc_slow_free(uccs);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 321 return -EINVAL;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 322 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 323 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 324
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 325 /* Set interrupt mask register at UCC level. */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 326 qe_iowrite16be(us_info->uccm_mask, &us_regs->uccm);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 327
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 328 /* First, clear anything pending at UCC level,
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 329 * otherwise, old garbage may come through
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 330 * as soon as the dam is opened. */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 331
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 332 /* Writing '1' clears */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 333 qe_iowrite16be(0xffff, &us_regs->ucce);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 334
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 335 /* Issue QE Init command */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 336 if (us_info->init_tx && us_info->init_rx)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 337 command = QE_INIT_TX_RX;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 338 else if (us_info->init_tx)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 339 command = QE_INIT_TX;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 340 else
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 341 command = QE_INIT_RX; /* We know at least one is TRUE */
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 342
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 343 qe_issue_cmd(command, id, us_info->protocol, 0);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 344
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 345 *uccs_ret = uccs;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 346 return 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 347 }
845cf505cebd15 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2008-01-09 348 EXPORT_SYMBOL(ucc_slow_init);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 349
:::::: The code at line 78 was first introduced by commit
:::::: 9865853851313e0d94a4acde42d6f9d8070bb376 [POWERPC] Add QUICC Engine (QE) infrastructure
:::::: TO: Li Yang <leoli@freescale.com>
:::::: CC: Paul Mackerras <paulus@samba.org>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org Intel Corporation
^ permalink raw reply [flat|nested] 120+ messages in thread
* [RFC PATCH] soc: fsl: qe: qe_uart_set_mctrl() can be static
2019-11-01 12:42 ` [PATCH v3 36/36] soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE Rasmus Villemoes
2019-11-02 17:39 ` kbuild test robot
2019-11-14 23:26 ` kbuild test robot
@ 2019-11-14 23:26 ` kbuild test robot
2019-11-15 13:31 ` [PATCH v3 36/36] soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE kbuild test robot
3 siblings, 0 replies; 120+ messages in thread
From: kbuild test robot @ 2019-11-14 23:26 UTC (permalink / raw)
To: Rasmus Villemoes
Cc: kbuild-all, Qiang Zhao, Li Yang, Christophe Leroy, linuxppc-dev,
linux-arm-kernel, linux-kernel, Scott Wood, Rasmus Villemoes
Fixes: 116af8542b17 ("soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE")
Signed-off-by: kbuild test robot <lkp@intel.com>
---
ucc_uart.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/tty/serial/ucc_uart.c b/drivers/tty/serial/ucc_uart.c
index a5330582b6103..58891be29e1cf 100644
--- a/drivers/tty/serial/ucc_uart.c
+++ b/drivers/tty/serial/ucc_uart.c
@@ -283,7 +283,7 @@ static unsigned int qe_uart_tx_empty(struct uart_port *port)
* don't need that support. This function must exist, however, otherwise
* the kernel will panic.
*/
-void qe_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
+static void qe_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
{
}
^ permalink raw reply related [flat|nested] 120+ messages in thread
* Re: [PATCH v3 36/36] soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE
2019-11-01 12:42 ` [PATCH v3 36/36] soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE Rasmus Villemoes
` (2 preceding siblings ...)
2019-11-14 23:26 ` [RFC PATCH] soc: fsl: qe: qe_uart_set_mctrl() can be static kbuild test robot
@ 2019-11-15 13:31 ` kbuild test robot
2019-11-15 13:42 ` Rasmus Villemoes
3 siblings, 1 reply; 120+ messages in thread
From: kbuild test robot @ 2019-11-15 13:31 UTC (permalink / raw)
To: Rasmus Villemoes
Cc: kbuild-all, Qiang Zhao, Li Yang, Christophe Leroy, linuxppc-dev,
linux-arm-kernel, linux-kernel, Scott Wood, Rasmus Villemoes
Hi Rasmus,
Thank you for the patch! Perhaps something to improve:
[auto build test WARNING on linus/master]
[also build test WARNING on v5.4-rc7 next-20191114]
[if your patch is applied to the wrong git tree, please drop us a note to help
improve the system. BTW, we also suggest to use '--base' option to specify the
base tree in git format-patch, please see https://stackoverflow.com/a/37406982]
url: https://github.com/0day-ci/linux/commits/Rasmus-Villemoes/QUICC-Engine-support-on-ARM/20191102-234436
base: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git 1204c70d9dcba31164f78ad5d8c88c42335d51f8
reproduce:
# apt-get install sparse
# sparse version: v0.6.1-32-g233d4e1-dirty
make ARCH=x86_64 allmodconfig
make C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__'
If you fix the issue, kindly add following tag
Reported-by: kbuild test robot <lkp@intel.com>
sparse warnings: (new ones prefixed by >>)
>> drivers/soc/fsl/qe/ucc_slow.c:78:17: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected struct ucc_slow *us_regs @@ got struct ucc_slow [nstruct ucc_slow *us_regs @@
>> drivers/soc/fsl/qe/ucc_slow.c:78:17: sparse: expected struct ucc_slow *us_regs
>> drivers/soc/fsl/qe/ucc_slow.c:78:17: sparse: got struct ucc_slow [noderef] <asn:2> *us_regs
>> drivers/soc/fsl/qe/ucc_slow.c:81:18: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
>> drivers/soc/fsl/qe/ucc_slow.c:81:18: sparse: expected void [noderef] <asn:2> *
>> drivers/soc/fsl/qe/ucc_slow.c:81:18: sparse: got restricted __be32 *
drivers/soc/fsl/qe/ucc_slow.c:90:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/soc/fsl/qe/ucc_slow.c:90:9: sparse: expected void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:90:9: sparse: got restricted __be32 *
drivers/soc/fsl/qe/ucc_slow.c:99:17: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected struct ucc_slow *us_regs @@ got struct ucc_slow [nstruct ucc_slow *us_regs @@
drivers/soc/fsl/qe/ucc_slow.c:99:17: sparse: expected struct ucc_slow *us_regs
drivers/soc/fsl/qe/ucc_slow.c:99:17: sparse: got struct ucc_slow [noderef] <asn:2> *us_regs
drivers/soc/fsl/qe/ucc_slow.c:102:18: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/soc/fsl/qe/ucc_slow.c:102:18: sparse: expected void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:102:18: sparse: got restricted __be32 *
drivers/soc/fsl/qe/ucc_slow.c:111:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/soc/fsl/qe/ucc_slow.c:111:9: sparse: expected void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:111:9: sparse: got restricted __be32 *
>> drivers/soc/fsl/qe/ucc_slow.c:169:28: sparse: sparse: Using plain integer as NULL pointer
>> drivers/soc/fsl/qe/ucc_slow.c:171:25: sparse: sparse: cast removes address space '<asn:2>' of expression
drivers/soc/fsl/qe/ucc_slow.c:172:25: sparse: sparse: cast removes address space '<asn:2>' of expression
>> drivers/soc/fsl/qe/ucc_slow.c:191:23: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected struct ucc_slow_pram *us_pram @@ got vostruct ucc_slow_pram *us_pram @@
>> drivers/soc/fsl/qe/ucc_slow.c:191:23: sparse: expected struct ucc_slow_pram *us_pram
>> drivers/soc/fsl/qe/ucc_slow.c:191:23: sparse: got void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:201:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/soc/fsl/qe/ucc_slow.c:201:9: sparse: expected void [noderef] <asn:2> *
>> drivers/soc/fsl/qe/ucc_slow.c:201:9: sparse: got restricted __be16 *
>> drivers/soc/fsl/qe/ucc_slow.c:228:41: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected struct qe_bd *tx_bd @@ got void [nodestruct qe_bd *tx_bd @@
>> drivers/soc/fsl/qe/ucc_slow.c:228:41: sparse: expected struct qe_bd *tx_bd
drivers/soc/fsl/qe/ucc_slow.c:228:41: sparse: got void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:231:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/soc/fsl/qe/ucc_slow.c:231:17: sparse: expected void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:231:17: sparse: got restricted __be32 *
>> drivers/soc/fsl/qe/ucc_slow.c:233:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got uvoid [noderef] <asn:2> * @@
drivers/soc/fsl/qe/ucc_slow.c:233:17: sparse: expected void [noderef] <asn:2> *
>> drivers/soc/fsl/qe/ucc_slow.c:233:17: sparse: got unsigned int [usertype] *
drivers/soc/fsl/qe/ucc_slow.c:237:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/soc/fsl/qe/ucc_slow.c:237:9: sparse: expected void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:237:9: sparse: got restricted __be32 *
>> drivers/soc/fsl/qe/ucc_slow.c:238:9: sparse: sparse: incorrect type in argument 1 (different base types) @@ expected unsigned int [usertype] @@ got restrunsigned int [usertype] @@
>> drivers/soc/fsl/qe/ucc_slow.c:238:9: sparse: expected unsigned int [usertype]
>> drivers/soc/fsl/qe/ucc_slow.c:238:9: sparse: got restricted __be32 [usertype]
drivers/soc/fsl/qe/ucc_slow.c:238:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got uvoid [noderef] <asn:2> * @@
drivers/soc/fsl/qe/ucc_slow.c:238:9: sparse: expected void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:238:9: sparse: got unsigned int [usertype] *
>> drivers/soc/fsl/qe/ucc_slow.c:241:26: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected struct qe_bd *rx_bd @@ got void [nodestruct qe_bd *rx_bd @@
>> drivers/soc/fsl/qe/ucc_slow.c:241:26: sparse: expected struct qe_bd *rx_bd
drivers/soc/fsl/qe/ucc_slow.c:241:26: sparse: got void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:244:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got uvoid [noderef] <asn:2> * @@
drivers/soc/fsl/qe/ucc_slow.c:244:17: sparse: expected void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:244:17: sparse: got unsigned int [usertype] *
drivers/soc/fsl/qe/ucc_slow.c:246:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/soc/fsl/qe/ucc_slow.c:246:17: sparse: expected void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:246:17: sparse: got restricted __be32 *
drivers/soc/fsl/qe/ucc_slow.c:250:9: sparse: sparse: incorrect type in argument 1 (different base types) @@ expected unsigned int [usertype] @@ got restrunsigned int [usertype] @@
drivers/soc/fsl/qe/ucc_slow.c:250:9: sparse: expected unsigned int [usertype]
drivers/soc/fsl/qe/ucc_slow.c:250:9: sparse: got restricted __be32 [usertype]
drivers/soc/fsl/qe/ucc_slow.c:250:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got uvoid [noderef] <asn:2> * @@
drivers/soc/fsl/qe/ucc_slow.c:250:9: sparse: expected void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:250:9: sparse: got unsigned int [usertype] *
drivers/soc/fsl/qe/ucc_slow.c:251:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/soc/fsl/qe/ucc_slow.c:251:9: sparse: expected void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:251:9: sparse: got restricted __be32 *
>> drivers/soc/fsl/qe/ucc_slow.c:275:39: sparse: sparse: mixing different enum types:
>> drivers/soc/fsl/qe/ucc_slow.c:275:39: sparse: unsigned int enum ucc_slow_tx_oversampling_rate
>> drivers/soc/fsl/qe/ucc_slow.c:275:39: sparse: unsigned int enum ucc_slow_rx_oversampling_rate
drivers/soc/fsl/qe/ucc_slow.c:295:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/soc/fsl/qe/ucc_slow.c:295:9: sparse: expected void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:295:9: sparse: got restricted __be16 *
drivers/soc/fsl/qe/ucc_slow.c:296:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/soc/fsl/qe/ucc_slow.c:296:9: sparse: expected void [noderef] <asn:2> *
drivers/soc/fsl/qe/ucc_slow.c:296:9: sparse: got restricted __be16 *
--
>> drivers/tty/serial/ucc_uart.c:264:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
>> drivers/tty/serial/ucc_uart.c:264:21: sparse: expected void [noderef] <asn:2> *
>> drivers/tty/serial/ucc_uart.c:264:21: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:268:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:268:21: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:268:21: sparse: got restricted __be16 *
>> drivers/tty/serial/ucc_uart.c:286:6: sparse: sparse: symbol 'qe_uart_set_mctrl' was not declared. Should it be static?
drivers/tty/serial/ucc_uart.c:349:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:349:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:349:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:350:17: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:350:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:350:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:350:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:350:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:350:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:352:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:352:21: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:352:21: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:371:18: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:371:18: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:371:18: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:384:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:384:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:384:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:385:17: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:385:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:385:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:385:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:385:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:385:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:388:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:388:21: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:388:21: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:476:26: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:476:26: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:476:26: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:483:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:483:21: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:483:21: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:514:17: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:514:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:514:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:514:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:514:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:514:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:517:21: sparse: sparse: incorrect type in argument 1 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:517:21: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:517:21: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:608:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:608:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:608:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:609:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:609:17: sparse: expected void [noderef] <asn:2> *
>> drivers/tty/serial/ucc_uart.c:609:17: sparse: got restricted __be32 *
drivers/tty/serial/ucc_uart.c:610:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:610:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:610:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:616:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:616:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:616:9: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:617:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:617:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:617:9: sparse: got restricted __be32 *
drivers/tty/serial/ucc_uart.c:618:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:618:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:618:9: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:629:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:629:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:629:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:630:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:630:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:630:17: sparse: got restricted __be32 *
drivers/tty/serial/ucc_uart.c:631:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:631:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:631:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:641:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:641:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:641:9: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:642:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:642:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:642:9: sparse: got restricted __be32 *
drivers/tty/serial/ucc_uart.c:643:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:643:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:643:9: sparse: got restricted __be16 *
>> drivers/tty/serial/ucc_uart.c:657:46: sparse: sparse: incorrect type in initializer (different address spaces) @@ expected struct ucc_uart_pram *uccup @@ got struct ucc_uart_prstruct ucc_uart_pram *uccup @@
>> drivers/tty/serial/ucc_uart.c:657:46: sparse: expected struct ucc_uart_pram *uccup
>> drivers/tty/serial/ucc_uart.c:657:46: sparse: got struct ucc_uart_pram [noderef] <asn:2> *uccup
>> drivers/tty/serial/ucc_uart.c:665:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got eref] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:665:9: sparse: expected void [noderef] <asn:2> *
>> drivers/tty/serial/ucc_uart.c:665:9: sparse: got unsigned char *
drivers/tty/serial/ucc_uart.c:666:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got eref] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:666:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:666:9: sparse: got unsigned char *
drivers/tty/serial/ucc_uart.c:667:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:667:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:667:9: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:668:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:668:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:668:9: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:669:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:669:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:669:9: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:670:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:670:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:670:9: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:671:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:671:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:671:9: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:672:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:672:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:672:9: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:673:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:673:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:673:9: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:674:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:674:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:674:9: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:675:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:675:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:675:9: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:676:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:676:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:676:9: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:678:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:678:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:678:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:679:9: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:679:9: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:679:9: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:717:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:717:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:717:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:718:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:718:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:718:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:719:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:719:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:719:17: sparse: got restricted __be32 *
drivers/tty/serial/ucc_uart.c:720:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:720:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:720:17: sparse: got restricted __be32 *
drivers/tty/serial/ucc_uart.c:721:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got eref] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:721:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:721:17: sparse: got unsigned char *
drivers/tty/serial/ucc_uart.c:722:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got eref] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:722:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:722:17: sparse: got unsigned char *
drivers/tty/serial/ucc_uart.c:723:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:723:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:723:17: sparse: got restricted __be32 *
drivers/tty/serial/ucc_uart.c:724:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got eref] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:724:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:724:17: sparse: got unsigned char *
drivers/tty/serial/ucc_uart.c:725:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:725:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:725:17: sparse: got restricted __be32 *
drivers/tty/serial/ucc_uart.c:726:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got eref] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:726:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:726:17: sparse: got unsigned char *
drivers/tty/serial/ucc_uart.c:728:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got eref] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:728:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:728:17: sparse: got unsigned char *
drivers/tty/serial/ucc_uart.c:730:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:730:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:730:17: sparse: got restricted __be16 *
drivers/tty/serial/ucc_uart.c:731:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got eref] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:731:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:731:17: sparse: got unsigned char *
drivers/tty/serial/ucc_uart.c:732:17: sparse: sparse: incorrect type in argument 2 (different address spaces) @@ expected void [noderef] <asn:2> * @@ got [noderef] <asn:2> * @@
drivers/tty/serial/ucc_uart.c:732:17: sparse: expected void [noderef] <asn:2> *
drivers/tty/serial/ucc_uart.c:732:17: sparse: got restricted __be16 *
>> drivers/tty/serial/ucc_uart.c:1004:24: sparse: sparse: incorrect type in assignment (different address spaces) @@ expected struct ucc_uart_pram [noderef] <asn:2> *uccup @@ got am [noderef] <asn:2> *uccup @@
>> drivers/tty/serial/ucc_uart.c:1004:24: sparse: expected struct ucc_uart_pram [noderef] <asn:2> *uccup
>> drivers/tty/serial/ucc_uart.c:1004:24: sparse: got struct ucc_uart_pram *
vim +78 drivers/soc/fsl/qe/ucc_slow.c
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 72
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 73 void ucc_slow_enable(struct ucc_slow_private * uccs, enum comm_dir mode)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 74 {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 75 struct ucc_slow *us_regs;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 76 u32 gumr_l;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 77
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 @78 us_regs = uccs->us_regs;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 79
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 80 /* Enable reception and/or transmission on this UCC. */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 @81 gumr_l = qe_ioread32be(&us_regs->gumr_l);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 82 if (mode & COMM_DIR_TX) {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 83 gumr_l |= UCC_SLOW_GUMR_L_ENT;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 84 uccs->enabled_tx = 1;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 85 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 86 if (mode & COMM_DIR_RX) {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 87 gumr_l |= UCC_SLOW_GUMR_L_ENR;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 88 uccs->enabled_rx = 1;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 89 }
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 90 qe_iowrite32be(gumr_l, &us_regs->gumr_l);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 91 }
845cf505cebd15 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2008-01-09 92 EXPORT_SYMBOL(ucc_slow_enable);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 93
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 94 void ucc_slow_disable(struct ucc_slow_private * uccs, enum comm_dir mode)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 95 {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 96 struct ucc_slow *us_regs;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 97 u32 gumr_l;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 98
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 @99 us_regs = uccs->us_regs;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 100
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 101 /* Disable reception and/or transmission on this UCC. */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 @102 gumr_l = qe_ioread32be(&us_regs->gumr_l);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 103 if (mode & COMM_DIR_TX) {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 104 gumr_l &= ~UCC_SLOW_GUMR_L_ENT;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 105 uccs->enabled_tx = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 106 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 107 if (mode & COMM_DIR_RX) {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 108 gumr_l &= ~UCC_SLOW_GUMR_L_ENR;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 109 uccs->enabled_rx = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 110 }
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 @111 qe_iowrite32be(gumr_l, &us_regs->gumr_l);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 112 }
845cf505cebd15 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2008-01-09 113 EXPORT_SYMBOL(ucc_slow_disable);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 114
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 115 /* Initialize the UCC for Slow operations
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 116 *
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 117 * The caller should initialize the following us_info
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 118 */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 119 int ucc_slow_init(struct ucc_slow_info * us_info, struct ucc_slow_private ** uccs_ret)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 120 {
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 121 struct ucc_slow_private *uccs;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 122 u32 i;
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 123 struct ucc_slow __iomem *us_regs;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 124 u32 gumr;
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 125 struct qe_bd *bd;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 126 u32 id;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 127 u32 command;
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 128 int ret = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 129
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 130 if (!us_info)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 131 return -EINVAL;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 132
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 133 /* check if the UCC port number is in range. */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 134 if ((us_info->ucc_num < 0) || (us_info->ucc_num > UCC_MAX_NUM - 1)) {
e48b1b452ff630 arch/powerpc/sysdev/qe_lib/ucc_slow.c Harvey Harrison 2008-03-29 135 printk(KERN_ERR "%s: illegal UCC number\n", __func__);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 136 return -EINVAL;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 137 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 138
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 139 /*
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 140 * Set mrblr
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 141 * Check that 'max_rx_buf_length' is properly aligned (4), unless
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 142 * rfw is 1, meaning that QE accepts one byte at a time, unlike normal
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 143 * case when QE accepts 32 bits at a time.
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 144 */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 145 if ((!us_info->rfw) &&
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 146 (us_info->max_rx_buf_length & (UCC_SLOW_MRBLR_ALIGNMENT - 1))) {
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 147 printk(KERN_ERR "max_rx_buf_length not aligned.\n");
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 148 return -EINVAL;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 149 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 150
f8485350c22b25 arch/powerpc/sysdev/qe_lib/ucc_slow.c Yan Burman 2006-12-02 151 uccs = kzalloc(sizeof(struct ucc_slow_private), GFP_KERNEL);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 152 if (!uccs) {
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 153 printk(KERN_ERR "%s: Cannot allocate private data\n",
e48b1b452ff630 arch/powerpc/sysdev/qe_lib/ucc_slow.c Harvey Harrison 2008-03-29 154 __func__);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 155 return -ENOMEM;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 156 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 157
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 158 /* Fill slow UCC structure */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 159 uccs->us_info = us_info;
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 160 /* Set the PHY base address */
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 161 uccs->us_regs = ioremap(us_info->regs, sizeof(struct ucc_slow));
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 162 if (uccs->us_regs == NULL) {
e48b1b452ff630 arch/powerpc/sysdev/qe_lib/ucc_slow.c Harvey Harrison 2008-03-29 163 printk(KERN_ERR "%s: Cannot map UCC registers\n", __func__);
61a4e9e91dd391 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2008-08-20 164 kfree(uccs);
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 165 return -ENOMEM;
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 166 }
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 167
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 168 uccs->saved_uccm = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 @169 uccs->p_rx_frame = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 170 us_regs = uccs->us_regs;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 @171 uccs->p_ucce = (u16 *) & (us_regs->ucce);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 172 uccs->p_uccm = (u16 *) & (us_regs->uccm);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 173 #ifdef STATISTICS
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 174 uccs->rx_frames = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 175 uccs->tx_frames = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 176 uccs->rx_discarded = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 177 #endif /* STATISTICS */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 178
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 179 /* Get PRAM base */
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 180 uccs->us_pram_offset =
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 181 qe_muram_alloc(UCC_SLOW_PRAM_SIZE, ALIGNMENT_OF_UCC_SLOW_PRAM);
4c35630ccda56e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-05-08 182 if (IS_ERR_VALUE(uccs->us_pram_offset)) {
e48b1b452ff630 arch/powerpc/sysdev/qe_lib/ucc_slow.c Harvey Harrison 2008-03-29 183 printk(KERN_ERR "%s: cannot allocate MURAM for PRAM", __func__);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 184 ucc_slow_free(uccs);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 185 return -ENOMEM;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 186 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 187 id = ucc_slow_get_qe_cr_subblock(us_info->ucc_num);
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 188 qe_issue_cmd(QE_ASSIGN_PAGE_TO_DEVICE, id, us_info->protocol,
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 189 uccs->us_pram_offset);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 190
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 @191 uccs->us_pram = qe_muram_addr(uccs->us_pram_offset);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 192
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 193 /* Set UCC to slow type */
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 194 ret = ucc_set_type(us_info->ucc_num, UCC_SPEED_TYPE_SLOW);
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 195 if (ret) {
e48b1b452ff630 arch/powerpc/sysdev/qe_lib/ucc_slow.c Harvey Harrison 2008-03-29 196 printk(KERN_ERR "%s: cannot set UCC type", __func__);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 197 ucc_slow_free(uccs);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 198 return ret;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 199 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 200
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 @201 qe_iowrite16be(us_info->max_rx_buf_length, &uccs->us_pram->mrblr);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 202
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 203 INIT_LIST_HEAD(&uccs->confQ);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 204
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 205 /* Allocate BDs. */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 206 uccs->rx_base_offset =
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 207 qe_muram_alloc(us_info->rx_bd_ring_len * sizeof(struct qe_bd),
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 208 QE_ALIGNMENT_OF_BD);
4c35630ccda56e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-05-08 209 if (IS_ERR_VALUE(uccs->rx_base_offset)) {
e48b1b452ff630 arch/powerpc/sysdev/qe_lib/ucc_slow.c Harvey Harrison 2008-03-29 210 printk(KERN_ERR "%s: cannot allocate %u RX BDs\n", __func__,
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 211 us_info->rx_bd_ring_len);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 212 uccs->rx_base_offset = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 213 ucc_slow_free(uccs);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 214 return -ENOMEM;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 215 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 216
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 217 uccs->tx_base_offset =
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 218 qe_muram_alloc(us_info->tx_bd_ring_len * sizeof(struct qe_bd),
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 219 QE_ALIGNMENT_OF_BD);
4c35630ccda56e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-05-08 220 if (IS_ERR_VALUE(uccs->tx_base_offset)) {
e48b1b452ff630 arch/powerpc/sysdev/qe_lib/ucc_slow.c Harvey Harrison 2008-03-29 221 printk(KERN_ERR "%s: cannot allocate TX BDs", __func__);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 222 uccs->tx_base_offset = 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 223 ucc_slow_free(uccs);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 224 return -ENOMEM;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 225 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 226
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 227 /* Init Tx bds */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 @228 bd = uccs->confBd = uccs->tx_bd = qe_muram_addr(uccs->tx_base_offset);
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 229 for (i = 0; i < us_info->tx_bd_ring_len - 1; i++) {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 230 /* clear bd buffer */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 @231 qe_iowrite32be(0, &bd->buf);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 232 /* set bd status and length */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 @233 qe_iowrite32be(0, (u32 *)bd);
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 234 bd++;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 235 }
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 236 /* for last BD set Wrap bit */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 @237 qe_iowrite32be(0, &bd->buf);
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 @238 qe_iowrite32be(cpu_to_be32(T_W), (u32 *)bd);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 239
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 240 /* Init Rx bds */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 @241 bd = uccs->rx_bd = qe_muram_addr(uccs->rx_base_offset);
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 242 for (i = 0; i < us_info->rx_bd_ring_len - 1; i++) {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 243 /* set bd status and length */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 244 qe_iowrite32be(0, (u32 *)bd);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 245 /* clear bd buffer */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 246 qe_iowrite32be(0, &bd->buf);
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 247 bd++;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 248 }
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 249 /* for last BD set Wrap bit */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 @250 qe_iowrite32be(cpu_to_be32(R_W), (u32 *)bd);
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 251 qe_iowrite32be(0, &bd->buf);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 252
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 253 /* Set GUMR (For more details see the hardware spec.). */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 254 /* gumr_h */
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 255 gumr = us_info->tcrc;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 256 if (us_info->cdp)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 257 gumr |= UCC_SLOW_GUMR_H_CDP;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 258 if (us_info->ctsp)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 259 gumr |= UCC_SLOW_GUMR_H_CTSP;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 260 if (us_info->cds)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 261 gumr |= UCC_SLOW_GUMR_H_CDS;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 262 if (us_info->ctss)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 263 gumr |= UCC_SLOW_GUMR_H_CTSS;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 264 if (us_info->tfl)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 265 gumr |= UCC_SLOW_GUMR_H_TFL;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 266 if (us_info->rfw)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 267 gumr |= UCC_SLOW_GUMR_H_RFW;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 268 if (us_info->txsy)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 269 gumr |= UCC_SLOW_GUMR_H_TXSY;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 270 if (us_info->rtsm)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 271 gumr |= UCC_SLOW_GUMR_H_RTSM;
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 272 qe_iowrite32be(gumr, &us_regs->gumr_h);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 273
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 274 /* gumr_l */
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 @275 gumr = us_info->tdcr | us_info->rdcr | us_info->tenc | us_info->renc |
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 276 us_info->diag | us_info->mode;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 277 if (us_info->tci)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 278 gumr |= UCC_SLOW_GUMR_L_TCI;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 279 if (us_info->rinv)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 280 gumr |= UCC_SLOW_GUMR_L_RINV;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 281 if (us_info->tinv)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 282 gumr |= UCC_SLOW_GUMR_L_TINV;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 283 if (us_info->tend)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 284 gumr |= UCC_SLOW_GUMR_L_TEND;
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 285 qe_iowrite32be(gumr, &us_regs->gumr_l);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 286
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 287 /* Function code registers */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 288
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 289 /* if the data is in cachable memory, the 'global' */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 290 /* in the function code should be set. */
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 291 uccs->us_pram->tbmr = UCC_BMR_BO_BE;
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 292 uccs->us_pram->rbmr = UCC_BMR_BO_BE;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 293
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 294 /* rbase, tbase are offsets from MURAM base */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 295 qe_iowrite16be(uccs->rx_base_offset, &uccs->us_pram->rbase);
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 296 qe_iowrite16be(uccs->tx_base_offset, &uccs->us_pram->tbase);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 297
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 298 /* Mux clocking */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 299 /* Grant Support */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 300 ucc_set_qe_mux_grant(us_info->ucc_num, us_info->grant_support);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 301 /* Breakpoint Support */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 302 ucc_set_qe_mux_bkpt(us_info->ucc_num, us_info->brkpt_support);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 303 /* Set Tsa or NMSI mode. */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 304 ucc_set_qe_mux_tsa(us_info->ucc_num, us_info->tsa);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 305 /* If NMSI (not Tsa), set Tx and Rx clock. */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 306 if (!us_info->tsa) {
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 307 /* Rx clock routing */
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 308 if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->rx_clock,
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 309 COMM_DIR_RX)) {
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 310 printk(KERN_ERR "%s: illegal value for RX clock\n",
e48b1b452ff630 arch/powerpc/sysdev/qe_lib/ucc_slow.c Harvey Harrison 2008-03-29 311 __func__);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 312 ucc_slow_free(uccs);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 313 return -EINVAL;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 314 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 315 /* Tx clock routing */
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 316 if (ucc_set_qe_mux_rxtx(us_info->ucc_num, us_info->tx_clock,
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 317 COMM_DIR_TX)) {
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 318 printk(KERN_ERR "%s: illegal value for TX clock\n",
e48b1b452ff630 arch/powerpc/sysdev/qe_lib/ucc_slow.c Harvey Harrison 2008-03-29 319 __func__);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 320 ucc_slow_free(uccs);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 321 return -EINVAL;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 322 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 323 }
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 324
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 325 /* Set interrupt mask register at UCC level. */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 326 qe_iowrite16be(us_info->uccm_mask, &us_regs->uccm);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 327
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 328 /* First, clear anything pending at UCC level,
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 329 * otherwise, old garbage may come through
5af68af5bcd34e arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-02-16 330 * as soon as the dam is opened. */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 331
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 332 /* Writing '1' clears */
eb63c63b289d28 drivers/soc/fsl/qe/ucc_slow.c Rasmus Villemoes 2019-11-01 333 qe_iowrite16be(0xffff, &us_regs->ucce);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 334
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 335 /* Issue QE Init command */
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 336 if (us_info->init_tx && us_info->init_rx)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 337 command = QE_INIT_TX_RX;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 338 else if (us_info->init_tx)
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 339 command = QE_INIT_TX;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 340 else
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 341 command = QE_INIT_RX; /* We know at least one is TRUE */
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 342
6b0b594bb81f86 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2007-10-03 343 qe_issue_cmd(command, id, us_info->protocol, 0);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 344
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 345 *uccs_ret = uccs;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 346 return 0;
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 347 }
845cf505cebd15 arch/powerpc/sysdev/qe_lib/ucc_slow.c Timur Tabi 2008-01-09 348 EXPORT_SYMBOL(ucc_slow_init);
9865853851313e arch/powerpc/sysdev/qe_lib/ucc_slow.c Li Yang 2006-10-03 349
:::::: The code at line 78 was first introduced by commit
:::::: 9865853851313e0d94a4acde42d6f9d8070bb376 [POWERPC] Add QUICC Engine (QE) infrastructure
:::::: TO: Li Yang <leoli@freescale.com>
:::::: CC: Paul Mackerras <paulus@samba.org>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org Intel Corporation
^ permalink raw reply [flat|nested] 120+ messages in thread
* Re: [PATCH v3 36/36] soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE
2019-11-15 13:31 ` [PATCH v3 36/36] soc: fsl: qe: remove PPC32 dependency from CONFIG_QUICC_ENGINE kbuild test robot
@ 2019-11-15 13:42 ` Rasmus Villemoes
0 siblings, 0 replies; 120+ messages in thread
From: Rasmus Villemoes @ 2019-11-15 13:42 UTC (permalink / raw)
To: kbuild test robot
Cc: kbuild-all, Qiang Zhao, Li Yang, Christophe Leroy, linuxppc-dev,
linux-arm-kernel, linux-kernel, Scott Wood
On 15/11/2019 14.31, kbuild test robot wrote:
> Hi Rasmus,
>
> Thank you for the patch! Perhaps something to improve:
Hello kbuild
Thanks for your reports, but this has already been fixed. Is there some
way to indicate to the kbuild bot that it should stop using resources on
a specific patch set? There's really no point in the bot doing lots of
builds and sending out reports for a series that has already been
superseded - and reviewers might easily think that the report concerns
the latest revision. Perhaps something like
kbuild-ignore: <msg id of cover letter of revision N-1>
in the cover-letter of revision N? Or is there some smarter (automatic)
way of doing this?
Rasmus
^ permalink raw reply [flat|nested] 120+ messages in thread