From: Jim Quinlan <james.quinlan@broadcom.com>
To: james.quinlan@broadcom.com
Cc: Jim Quinlan <james.quinlan@broadcom.com>,
Nicolas Saenz Julienne <nsaenzjulienne@suse.de>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
Rob Herring <robh@kernel.org>,
Bjorn Helgaas <bhelgaas@google.com>,
Florian Fainelli <f.fainelli@gmail.com>,
bcm-kernel-feedback-list@broadcom.com (maintainer:BROADCOM
BCM7XXX ARM ARCHITECTURE),
linux-rpi-kernel@lists.infradead.org (moderated list:BROADCOM
BCM2711/BCM2835 ARM ARCHITECTURE),
linux-arm-kernel@lists.infradead.org (moderated list:BROADCOM
BCM2711/BCM2835 ARM ARCHITECTURE),
linux-pci@vger.kernel.org (open list:PCI NATIVE HOST BRIDGE AND
ENDPOINT DRIVERS), linux-kernel@vger.kernel.org (open list)
Subject: [PATCH 3/5] PCI: brcmstb: enable CRS
Date: Thu, 30 Apr 2020 14:55:20 -0400 [thread overview]
Message-ID: <20200430185522.4116-3-james.quinlan@broadcom.com> (raw)
In-Reply-To: <20200430185522.4116-1-james.quinlan@broadcom.com>
From: Jim Quinlan <jquinlan@broadcom.com>
Configuration Retry Request Status is off by default on this
PCIe controller. Turn it on.
Signed-off-by: Jim Quinlan <jquinlan@broadcom.com>
---
drivers/pci/controller/pcie-brcmstb.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/pci/controller/pcie-brcmstb.c b/drivers/pci/controller/pcie-brcmstb.c
index 5b0dec5971b8..2bc913c0262c 100644
--- a/drivers/pci/controller/pcie-brcmstb.c
+++ b/drivers/pci/controller/pcie-brcmstb.c
@@ -34,6 +34,9 @@
#define BRCM_PCIE_CAP_REGS 0x00ac
/* Broadcom STB PCIe Register Offsets */
+#define PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL 0x00c8
+#define PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_MASK 0x10
+
#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1 0x0188
#define PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1_ENDIAN_MODE_BAR2_MASK 0xc
#define PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN 0x0
@@ -827,6 +830,12 @@ static int brcm_pcie_setup(struct brcm_pcie *pcie)
pci_speed_string(pcie_link_speed[cls]), nlw,
ssc_good ? "(SSC)" : "(!SSC)");
+ /* Enable configuration request retry (CRS) */
+ tmp = readl(base + PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL);
+ u32p_replace_bits(&tmp, 1,
+ PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL_RC_CRS_EN_MASK);
+ writel(tmp, base + PCIE_RC_CFG_PCIE_ROOT_CAP_CONTROL);
+
/* PCIe->SCB endian mode for BAR */
tmp = readl(base + PCIE_RC_CFG_VENDOR_VENDOR_SPECIFIC_REG1);
u32p_replace_bits(&tmp, PCIE_RC_CFG_VENDOR_SPCIFIC_REG1_LITTLE_ENDIAN,
--
2.17.1
next prev parent reply other threads:[~2020-04-30 19:01 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-30 18:55 [PATCH 1/5] PCI: brcmstb: don't clk_put() a managed clock Jim Quinlan
2020-04-30 18:55 ` [PATCH 2/5] PCI: brcmstb: fix window register offset from 4 to 8 Jim Quinlan
2020-04-30 19:07 ` Florian Fainelli
2020-04-30 20:43 ` Bjorn Helgaas
2020-04-30 18:55 ` Jim Quinlan [this message]
2020-04-30 19:19 ` [PATCH 3/5] PCI: brcmstb: enable CRS Florian Fainelli
2020-04-30 20:32 ` Bjorn Helgaas
2020-04-30 21:00 ` Jim Quinlan
2020-04-30 18:55 ` [PATCH 4/5] dt-bindings: PCI: brcmstb: New prop 'brcm,aspm-en-l0s' Jim Quinlan
2020-04-30 19:20 ` Florian Fainelli
2020-04-30 18:55 ` [PATCH 5/5] PCI: brcmstb: disable L0s component of ASPM by default Jim Quinlan
2020-04-30 19:21 ` Florian Fainelli
2020-04-30 20:40 ` Bjorn Helgaas
2020-04-30 21:17 ` Jim Quinlan
2020-04-30 19:05 ` [PATCH 1/5] PCI: brcmstb: don't clk_put() a managed clock Florian Fainelli
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