* [PATCH v4 0/3] mmc: Adding support for Microchip Sparx5 SoC
@ 2020-06-18 14:13 Lars Povlsen
2020-06-18 14:13 ` [PATCH v4 1/3] dt-bindings: mmc: Add Sparx5 SDHCI controller bindings Lars Povlsen
` (2 more replies)
0 siblings, 3 replies; 11+ messages in thread
From: Lars Povlsen @ 2020-06-18 14:13 UTC (permalink / raw)
To: Ulf Hansson, Adrian Hunter, SoC Team
Cc: Lars Povlsen, Microchip Linux Driver Support, linux-mmc,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
This is an add-on series to the main SoC Sparx5 series
(Message-ID: <20200615133242.24911-1-lars.povlsen@microchip.com>
It adds eMMC support for Sparx5, by adding a driver for the SoC SDHCI
controller, DT configuration and DT binding documentation.
Changes in v4:
- Disable clock if sdhci_add_host() fails
- Remove dev_err if sdhci_add_host() fails
Changes in v3:
- Add dt-bindings for property "microchip,clock-delay"
- Enforce "microchip,clock-delay" valid range in driver
- Removed a noisy pr_debug() in sdhci_sparx5_adma_write_desc()
Changes in v2:
- Changes in driver as per review comments
- Drop debug code
- Drop sysfs code
- use usleep_range()
- use mmc_hostname() in pr_debug()
- Remove deactivated code
- Minor cosmetics
Lars Povlsen (3):
dt-bindings: mmc: Add Sparx5 SDHCI controller bindings
sdhci: sparx5: Add Sparx5 SoC eMMC driver
arm64: dts: sparx5: Add Sparx5 eMMC support
.../mmc/microchip,dw-sparx5-sdhci.yaml | 65 +++++
arch/arm64/boot/dts/microchip/sparx5.dtsi | 24 ++
.../boot/dts/microchip/sparx5_pcb125.dts | 23 ++
.../boot/dts/microchip/sparx5_pcb134_emmc.dts | 23 ++
.../boot/dts/microchip/sparx5_pcb135_emmc.dts | 23 ++
drivers/mmc/host/Kconfig | 13 +
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/sdhci-of-sparx5.c | 269 ++++++++++++++++++
8 files changed, 441 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml
create mode 100644 drivers/mmc/host/sdhci-of-sparx5.c
--
2.27.0
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v4 1/3] dt-bindings: mmc: Add Sparx5 SDHCI controller bindings
2020-06-18 14:13 [PATCH v4 0/3] mmc: Adding support for Microchip Sparx5 SoC Lars Povlsen
@ 2020-06-18 14:13 ` Lars Povlsen
2020-06-29 21:54 ` Rob Herring
2020-06-18 14:13 ` [PATCH v4 2/3] sdhci: sparx5: Add Sparx5 SoC eMMC driver Lars Povlsen
2020-06-18 14:13 ` [PATCH v4 3/3] arm64: dts: sparx5: Add Sparx5 eMMC support Lars Povlsen
2 siblings, 1 reply; 11+ messages in thread
From: Lars Povlsen @ 2020-06-18 14:13 UTC (permalink / raw)
To: Ulf Hansson, Adrian Hunter, SoC Team, Rob Herring
Cc: Lars Povlsen, Microchip Linux Driver Support, linux-mmc,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
The Sparx5 SDHCI controller is based on the Designware controller IP.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
.../mmc/microchip,dw-sparx5-sdhci.yaml | 65 +++++++++++++++++++
1 file changed, 65 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml
diff --git a/Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml b/Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml
new file mode 100644
index 0000000000000..55883290543b9
--- /dev/null
+++ b/Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml
@@ -0,0 +1,65 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mmc/microchip,dw-sparx5-sdhci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Microchip Sparx5 Mobile Storage Host Controller Binding
+
+allOf:
+ - $ref: "mmc-controller.yaml"
+
+maintainers:
+ - Lars Povlsen <lars.povlsen@microchip.com>
+
+# Everything else is described in the common file
+properties:
+ compatible:
+ const: microchip,dw-sparx5-sdhci
+
+ reg:
+ maxItems: 1
+
+ interrupts:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+ description:
+ Handle to "core" clock for the sdhci controller.
+
+ clock-names:
+ items:
+ - const: core
+
+ microchip,clock-delay:
+ description: Delay clock to card to meet setup time requirements.
+ Each step increase by 1.25ns.
+ $ref: "/schemas/types.yaml#/definitions/uint32"
+ minimum: 1
+ maximum: 15
+
+required:
+ - compatible
+ - reg
+ - interrupts
+ - clocks
+ - clock-names
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/microchip,sparx5.h>
+ sdhci0: mmc@600800000 {
+ compatible = "microchip,dw-sparx5-sdhci";
+ reg = <0x00800000 0x1000>;
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+ clocks = <&clks CLK_ID_AUX1>;
+ clock-names = "core";
+ assigned-clocks = <&clks CLK_ID_AUX1>;
+ assigned-clock-rates = <800000000>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ bus-width = <8>;
+ microchip,clock-delay = <10>;
+ };
--
2.27.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v4 2/3] sdhci: sparx5: Add Sparx5 SoC eMMC driver
2020-06-18 14:13 [PATCH v4 0/3] mmc: Adding support for Microchip Sparx5 SoC Lars Povlsen
2020-06-18 14:13 ` [PATCH v4 1/3] dt-bindings: mmc: Add Sparx5 SDHCI controller bindings Lars Povlsen
@ 2020-06-18 14:13 ` Lars Povlsen
2020-06-18 14:43 ` Adrian Hunter
2020-06-18 14:13 ` [PATCH v4 3/3] arm64: dts: sparx5: Add Sparx5 eMMC support Lars Povlsen
2 siblings, 1 reply; 11+ messages in thread
From: Lars Povlsen @ 2020-06-18 14:13 UTC (permalink / raw)
To: Ulf Hansson, Adrian Hunter, SoC Team
Cc: Lars Povlsen, Microchip Linux Driver Support, linux-mmc,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
This adds the eMMC driver for the Sparx5 SoC. It is based upon the
designware IP, but requires some extra initialization and quirks.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
drivers/mmc/host/Kconfig | 13 ++
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/sdhci-of-sparx5.c | 269 +++++++++++++++++++++++++++++
3 files changed, 283 insertions(+)
create mode 100644 drivers/mmc/host/sdhci-of-sparx5.c
diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index 3b706af35ec31..a3bad4b4ed7ea 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -213,6 +213,19 @@ config MMC_SDHCI_OF_DWCMSHC
If you have a controller with this interface, say Y or M here.
If unsure, say N.
+config MMC_SDHCI_OF_SPARX5
+ tristate "SDHCI OF support for the MCHP Sparx5 SoC"
+ depends on MMC_SDHCI_PLTFM
+ depends on ARCH_SPARX5
+ select MMC_SDHCI_IO_ACCESSORS
+ help
+ This selects the Secure Digital Host Controller Interface (SDHCI)
+ found in the MCHP Sparx5 SoC.
+
+ If you have a Sparx5 SoC with this interface, say Y or M here.
+
+ If unsure, say N.
+
config MMC_SDHCI_CADENCE
tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller"
depends on MMC_SDHCI_PLTFM
diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
index 4d5bcb0144a0a..451c25fc2c692 100644
--- a/drivers/mmc/host/Makefile
+++ b/drivers/mmc/host/Makefile
@@ -94,6 +94,7 @@ obj-$(CONFIG_MMC_SDHCI_OF_AT91) += sdhci-of-at91.o
obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o
obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o
obj-$(CONFIG_MMC_SDHCI_OF_DWCMSHC) += sdhci-of-dwcmshc.o
+obj-$(CONFIG_MMC_SDHCI_OF_SPARX5) += sdhci-of-sparx5.o
obj-$(CONFIG_MMC_SDHCI_BCM_KONA) += sdhci-bcm-kona.o
obj-$(CONFIG_MMC_SDHCI_IPROC) += sdhci-iproc.o
obj-$(CONFIG_MMC_SDHCI_MSM) += sdhci-msm.o
diff --git a/drivers/mmc/host/sdhci-of-sparx5.c b/drivers/mmc/host/sdhci-of-sparx5.c
new file mode 100644
index 0000000000000..2b262c12e5530
--- /dev/null
+++ b/drivers/mmc/host/sdhci-of-sparx5.c
@@ -0,0 +1,269 @@
+// SPDX-License-Identifier: GPL-2.0-or-later
+/*
+ * drivers/mmc/host/sdhci-of-sparx5.c
+ *
+ * MCHP Sparx5 SoC Secure Digital Host Controller Interface.
+ *
+ * Copyright (c) 2019 Microchip Inc.
+ *
+ * Author: Lars Povlsen <lars.povlsen@microchip.com>
+ */
+
+#include <linux/sizes.h>
+#include <linux/delay.h>
+#include <linux/module.h>
+#include <linux/regmap.h>
+#include <linux/of_device.h>
+#include <linux/mfd/syscon.h>
+#include <linux/dma-mapping.h>
+
+#include "sdhci-pltfm.h"
+
+#define CPU_REGS_GENERAL_CTRL (0x22 * 4)
+#define MSHC_DLY_CC_MASK GENMASK(16, 13)
+#define MSHC_DLY_CC_SHIFT 13
+#define MSHC_DLY_CC_MAX 15
+
+#define CPU_REGS_PROC_CTRL (0x2C * 4)
+#define ACP_CACHE_FORCE_ENA BIT(4)
+#define ACP_AWCACHE BIT(3)
+#define ACP_ARCACHE BIT(2)
+#define ACP_CACHE_MASK (ACP_CACHE_FORCE_ENA|ACP_AWCACHE|ACP_ARCACHE)
+
+#define MSHC2_VERSION 0x500 /* Off 0x140, reg 0x0 */
+#define MSHC2_TYPE 0x504 /* Off 0x140, reg 0x1 */
+#define MSHC2_EMMC_CTRL 0x52c /* Off 0x140, reg 0xB */
+#define MSHC2_EMMC_CTRL_EMMC_RST_N BIT(2)
+#define MSHC2_EMMC_CTRL_IS_EMMC BIT(0)
+
+struct sdhci_sparx5_data {
+ struct sdhci_host *host;
+ struct regmap *cpu_ctrl;
+ int delay_clock;
+};
+
+#define BOUNDARY_OK(addr, len) \
+ ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
+
+/*
+ * If DMA addr spans 128MB boundary, we split the DMA transfer into two
+ * so that each DMA transfer doesn't exceed the boundary.
+ */
+static void sdhci_sparx5_adma_write_desc(struct sdhci_host *host, void **desc,
+ dma_addr_t addr, int len,
+ unsigned int cmd)
+{
+ int tmplen, offset;
+
+ if (likely(!len || BOUNDARY_OK(addr, len))) {
+ sdhci_adma_write_desc(host, desc, addr, len, cmd);
+ return;
+ }
+
+ pr_debug("%s: write_desc: splitting dma len %d, offset 0x%0llx\n",
+ mmc_hostname(host->mmc), len, addr);
+
+ offset = addr & (SZ_128M - 1);
+ tmplen = SZ_128M - offset;
+ sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
+
+ addr += tmplen;
+ len -= tmplen;
+ sdhci_adma_write_desc(host, desc, addr, len, cmd);
+}
+
+static void sparx5_set_cacheable(struct sdhci_host *host, u32 value)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_sparx5_data *sdhci_sparx5 = sdhci_pltfm_priv(pltfm_host);
+
+ pr_debug("%s: Set Cacheable = 0x%x\n", mmc_hostname(host->mmc), value);
+
+ /* Update ACP caching attributes in HW */
+ regmap_update_bits(sdhci_sparx5->cpu_ctrl,
+ CPU_REGS_PROC_CTRL, ACP_CACHE_MASK, value);
+}
+
+static void sparx5_set_delay(struct sdhci_host *host, u8 value)
+{
+ struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
+ struct sdhci_sparx5_data *sdhci_sparx5 = sdhci_pltfm_priv(pltfm_host);
+
+ pr_debug("%s: Set DLY_CC = %u\n", mmc_hostname(host->mmc), value);
+
+ /* Update DLY_CC in HW */
+ regmap_update_bits(sdhci_sparx5->cpu_ctrl,
+ CPU_REGS_GENERAL_CTRL,
+ MSHC_DLY_CC_MASK,
+ (value << MSHC_DLY_CC_SHIFT));
+}
+
+static void sdhci_sparx5_set_emmc(struct sdhci_host *host)
+{
+ if (!mmc_card_is_removable(host->mmc)) {
+ u8 value;
+
+ value = sdhci_readb(host, MSHC2_EMMC_CTRL);
+ if (!(value & MSHC2_EMMC_CTRL_IS_EMMC)) {
+ value |= MSHC2_EMMC_CTRL_IS_EMMC;
+ pr_debug("%s: Set EMMC_CTRL: 0x%08x\n",
+ mmc_hostname(host->mmc), value);
+ sdhci_writeb(host, value, MSHC2_EMMC_CTRL);
+ }
+ }
+}
+
+static void sdhci_sparx5_reset_emmc(struct sdhci_host *host)
+{
+ u8 value;
+
+ pr_debug("%s: Toggle EMMC_CTRL.EMMC_RST_N\n", mmc_hostname(host->mmc));
+ value = sdhci_readb(host, MSHC2_EMMC_CTRL) &
+ ~MSHC2_EMMC_CTRL_EMMC_RST_N;
+ sdhci_writeb(host, value, MSHC2_EMMC_CTRL);
+ /* For eMMC, minimum is 1us but give it 10us for good measure */
+ usleep_range(10, 20);
+ sdhci_writeb(host, value | MSHC2_EMMC_CTRL_EMMC_RST_N,
+ MSHC2_EMMC_CTRL);
+ /* For eMMC, minimum is 200us but give it 300us for good measure */
+ usleep_range(300, 400);
+}
+
+static void sdhci_sparx5_reset(struct sdhci_host *host, u8 mask)
+{
+ pr_debug("%s: *** RESET: mask %d\n", mmc_hostname(host->mmc), mask);
+
+ sdhci_reset(host, mask);
+
+ /* Be sure CARD_IS_EMMC stays set */
+ sdhci_sparx5_set_emmc(host);
+}
+
+static const struct sdhci_ops sdhci_sparx5_ops = {
+ .set_clock = sdhci_set_clock,
+ .set_bus_width = sdhci_set_bus_width,
+ .set_uhs_signaling = sdhci_set_uhs_signaling,
+ .get_max_clock = sdhci_pltfm_clk_get_max_clock,
+ .reset = sdhci_sparx5_reset,
+ .adma_write_desc = sdhci_sparx5_adma_write_desc,
+};
+
+static const struct sdhci_pltfm_data sdhci_sparx5_pdata = {
+ .quirks = 0,
+ .quirks2 = SDHCI_QUIRK2_HOST_NO_CMD23 | /* Controller issue */
+ SDHCI_QUIRK2_NO_1_8_V, /* No sdr104, ddr50, etc */
+ .ops = &sdhci_sparx5_ops,
+};
+
+int sdhci_sparx5_probe(struct platform_device *pdev)
+{
+ int ret;
+ const char *syscon = "microchip,sparx5-cpu-syscon";
+ struct sdhci_host *host;
+ struct sdhci_pltfm_host *pltfm_host;
+ struct sdhci_sparx5_data *sdhci_sparx5;
+ struct device_node *np = pdev->dev.of_node;
+ u32 value;
+ u32 extra;
+
+ host = sdhci_pltfm_init(pdev, &sdhci_sparx5_pdata,
+ sizeof(*sdhci_sparx5));
+
+ if (IS_ERR(host))
+ return PTR_ERR(host);
+
+ /*
+ * extra adma table cnt for cross 128M boundary handling.
+ */
+ extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev), SZ_128M);
+ if (extra > SDHCI_MAX_SEGS)
+ extra = SDHCI_MAX_SEGS;
+ host->adma_table_cnt += extra;
+
+ pltfm_host = sdhci_priv(host);
+ sdhci_sparx5 = sdhci_pltfm_priv(pltfm_host);
+ sdhci_sparx5->host = host;
+
+ pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
+ if (IS_ERR(pltfm_host->clk)) {
+ ret = PTR_ERR(pltfm_host->clk);
+ dev_err(&pdev->dev, "failed to get core clk: %d\n", ret);
+ goto free_pltfm;
+ }
+ ret = clk_prepare_enable(pltfm_host->clk);
+ if (ret)
+ goto free_pltfm;
+
+ if (!of_property_read_u32(np, "microchip,clock-delay", &value) &&
+ (value > 0 && value <= MSHC_DLY_CC_MAX))
+ sdhci_sparx5->delay_clock = value;
+
+ sdhci_get_of_property(pdev);
+
+ ret = mmc_of_parse(host->mmc);
+ if (ret)
+ goto err_clk;
+
+ sdhci_sparx5->cpu_ctrl = syscon_regmap_lookup_by_compatible(syscon);
+ if (IS_ERR(sdhci_sparx5->cpu_ctrl)) {
+ dev_err(&pdev->dev, "No CPU syscon regmap !\n");
+ ret = PTR_ERR(sdhci_sparx5->cpu_ctrl);
+ goto err_clk;
+ }
+
+ if (sdhci_sparx5->delay_clock >= 0)
+ sparx5_set_delay(host, sdhci_sparx5->delay_clock);
+
+ if (!mmc_card_is_removable(host->mmc)) {
+ /* Do a HW reset of eMMC card */
+ sdhci_sparx5_reset_emmc(host);
+ /* Update EMMC_CTRL */
+ sdhci_sparx5_set_emmc(host);
+ /* If eMMC, disable SD and SDIO */
+ host->mmc->caps2 |= (MMC_CAP2_NO_SDIO|MMC_CAP2_NO_SD);
+ }
+
+ ret = sdhci_add_host(host);
+ if (ret)
+ goto err_clk;
+
+ /* Set AXI bus master to use un-cached access (for DMA) */
+ if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA) &&
+ IS_ENABLED(CONFIG_DMA_DECLARE_COHERENT))
+ sparx5_set_cacheable(host, ACP_CACHE_FORCE_ENA);
+
+ pr_debug("%s: SDHC version: 0x%08x\n",
+ mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_VERSION));
+ pr_debug("%s: SDHC type: 0x%08x\n",
+ mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_TYPE));
+
+ return ret;
+
+err_clk:
+ clk_disable_unprepare(pltfm_host->clk);
+free_pltfm:
+ sdhci_pltfm_free(pdev);
+ return ret;
+}
+
+static const struct of_device_id sdhci_sparx5_of_match[] = {
+ { .compatible = "microchip,dw-sparx5-sdhci" },
+ { }
+};
+MODULE_DEVICE_TABLE(of, sdhci_sparx5_of_match);
+
+static struct platform_driver sdhci_sparx5_driver = {
+ .driver = {
+ .name = "sdhci-sparx5",
+ .of_match_table = sdhci_sparx5_of_match,
+ .pm = &sdhci_pltfm_pmops,
+ },
+ .probe = sdhci_sparx5_probe,
+ .remove = sdhci_pltfm_unregister,
+};
+
+module_platform_driver(sdhci_sparx5_driver);
+
+MODULE_DESCRIPTION("Sparx5 SDHCI OF driver");
+MODULE_AUTHOR("Lars Povlsen <lars.povlsen@microchip.com>");
+MODULE_LICENSE("GPL v2");
--
2.27.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v4 3/3] arm64: dts: sparx5: Add Sparx5 eMMC support
2020-06-18 14:13 [PATCH v4 0/3] mmc: Adding support for Microchip Sparx5 SoC Lars Povlsen
2020-06-18 14:13 ` [PATCH v4 1/3] dt-bindings: mmc: Add Sparx5 SDHCI controller bindings Lars Povlsen
2020-06-18 14:13 ` [PATCH v4 2/3] sdhci: sparx5: Add Sparx5 SoC eMMC driver Lars Povlsen
@ 2020-06-18 14:13 ` Lars Povlsen
2 siblings, 0 replies; 11+ messages in thread
From: Lars Povlsen @ 2020-06-18 14:13 UTC (permalink / raw)
To: Ulf Hansson, Adrian Hunter, SoC Team
Cc: Lars Povlsen, Microchip Linux Driver Support, linux-mmc,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
This adds eMMC support to the applicable Sparx5 board configuration
files.
Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
---
arch/arm64/boot/dts/microchip/sparx5.dtsi | 24 +++++++++++++++++++
.../boot/dts/microchip/sparx5_pcb125.dts | 23 ++++++++++++++++++
.../boot/dts/microchip/sparx5_pcb134_emmc.dts | 23 ++++++++++++++++++
.../boot/dts/microchip/sparx5_pcb135_emmc.dts | 23 ++++++++++++++++++
4 files changed, 93 insertions(+)
diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 84bca999420ef..c9dbd1a8b22b6 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -5,6 +5,7 @@
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/clock/microchip,sparx5.h>
/ {
compatible = "microchip,sparx5";
@@ -162,6 +163,20 @@ timer1: timer@600105000 {
interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
};
+ sdhci0: sdhci@600800000 {
+ compatible = "microchip,dw-sparx5-sdhci";
+ status = "disabled";
+ reg = <0x6 0x00800000 0x1000>;
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+ clocks = <&clks CLK_ID_AUX1>;
+ clock-names = "core";
+ assigned-clocks = <&clks CLK_ID_AUX1>;
+ assigned-clock-rates = <800000000>;
+ interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
+ bus-width = <8>;
+ };
+
gpio: pinctrl@6110101e0 {
compatible = "microchip,sparx5-pinctrl";
reg = <0x6 0x110101e0 0x90>, <0x6 0x10508010 0x100>;
@@ -191,6 +206,15 @@ i2c2_pins: i2c2-pins {
pins = "GPIO_28", "GPIO_29";
function = "twi2";
};
+
+ emmc_pins: emmc-pins {
+ pins = "GPIO_34", "GPIO_35", "GPIO_36",
+ "GPIO_37", "GPIO_38", "GPIO_39",
+ "GPIO_40", "GPIO_41", "GPIO_42",
+ "GPIO_43", "GPIO_44", "GPIO_45",
+ "GPIO_46", "GPIO_47";
+ function = "emmc";
+ };
};
i2c0: i2c@600101000 {
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
index 91ee5b6cfc37a..573309fe45823 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb125.dts
@@ -16,6 +16,29 @@ memory@0 {
};
};
+&gpio {
+ emmc_pins: emmc-pins {
+ /* NB: No "GPIO_35", "GPIO_36", "GPIO_37"
+ * (N/A: CARD_nDETECT, CARD_WP, CARD_LED)
+ */
+ pins = "GPIO_34", "GPIO_38", "GPIO_39",
+ "GPIO_40", "GPIO_41", "GPIO_42",
+ "GPIO_43", "GPIO_44", "GPIO_45",
+ "GPIO_46", "GPIO_47";
+ drive-strength = <3>;
+ function = "emmc";
+ };
+};
+
+&sdhci0 {
+ status = "okay";
+ bus-width = <8>;
+ non-removable;
+ pinctrl-0 = <&emmc_pins>;
+ max-frequency = <8000000>;
+ microchip,clock-delay = <10>;
+};
+
&i2c1 {
status = "okay";
};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts
index 10081a66961bb..bbb9852c1f151 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb134_emmc.dts
@@ -15,3 +15,26 @@ memory@0 {
reg = <0x00000000 0x00000000 0x10000000>;
};
};
+
+&gpio {
+ emmc_pins: emmc-pins {
+ /* NB: No "GPIO_35", "GPIO_36", "GPIO_37"
+ * (N/A: CARD_nDETECT, CARD_WP, CARD_LED)
+ */
+ pins = "GPIO_34", "GPIO_38", "GPIO_39",
+ "GPIO_40", "GPIO_41", "GPIO_42",
+ "GPIO_43", "GPIO_44", "GPIO_45",
+ "GPIO_46", "GPIO_47";
+ drive-strength = <3>;
+ function = "emmc";
+ };
+};
+
+&sdhci0 {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ non-removable;
+ max-frequency = <52000000>;
+ bus-width = <8>;
+ microchip,clock-delay = <10>;
+};
diff --git a/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts b/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts
index 741f0e12260e5..f82266fe2ad49 100644
--- a/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts
+++ b/arch/arm64/boot/dts/microchip/sparx5_pcb135_emmc.dts
@@ -15,3 +15,26 @@ memory@0 {
reg = <0x00000000 0x00000000 0x10000000>;
};
};
+
+&gpio {
+ emmc_pins: emmc-pins {
+ /* NB: No "GPIO_35", "GPIO_36", "GPIO_37"
+ * (N/A: CARD_nDETECT, CARD_WP, CARD_LED)
+ */
+ pins = "GPIO_34", "GPIO_38", "GPIO_39",
+ "GPIO_40", "GPIO_41", "GPIO_42",
+ "GPIO_43", "GPIO_44", "GPIO_45",
+ "GPIO_46", "GPIO_47";
+ drive-strength = <3>;
+ function = "emmc";
+ };
+};
+
+&sdhci0 {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ non-removable;
+ max-frequency = <52000000>;
+ bus-width = <8>;
+ microchip,clock-delay = <10>;
+};
--
2.27.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v4 2/3] sdhci: sparx5: Add Sparx5 SoC eMMC driver
2020-06-18 14:13 ` [PATCH v4 2/3] sdhci: sparx5: Add Sparx5 SoC eMMC driver Lars Povlsen
@ 2020-06-18 14:43 ` Adrian Hunter
2020-07-22 11:54 ` Lars Povlsen
0 siblings, 1 reply; 11+ messages in thread
From: Adrian Hunter @ 2020-06-18 14:43 UTC (permalink / raw)
To: Lars Povlsen, Ulf Hansson, SoC Team
Cc: Microchip Linux Driver Support, linux-mmc, devicetree,
linux-arm-kernel, linux-kernel, Alexandre Belloni
On 18/06/20 5:13 pm, Lars Povlsen wrote:
> This adds the eMMC driver for the Sparx5 SoC. It is based upon the
> designware IP, but requires some extra initialization and quirks.
>
> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
Acked-by: Adrian Hunter <adrian.hunter@intel.com>
> ---
> drivers/mmc/host/Kconfig | 13 ++
> drivers/mmc/host/Makefile | 1 +
> drivers/mmc/host/sdhci-of-sparx5.c | 269 +++++++++++++++++++++++++++++
> 3 files changed, 283 insertions(+)
> create mode 100644 drivers/mmc/host/sdhci-of-sparx5.c
>
> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> index 3b706af35ec31..a3bad4b4ed7ea 100644
> --- a/drivers/mmc/host/Kconfig
> +++ b/drivers/mmc/host/Kconfig
> @@ -213,6 +213,19 @@ config MMC_SDHCI_OF_DWCMSHC
> If you have a controller with this interface, say Y or M here.
> If unsure, say N.
>
> +config MMC_SDHCI_OF_SPARX5
> + tristate "SDHCI OF support for the MCHP Sparx5 SoC"
> + depends on MMC_SDHCI_PLTFM
> + depends on ARCH_SPARX5
> + select MMC_SDHCI_IO_ACCESSORS
> + help
> + This selects the Secure Digital Host Controller Interface (SDHCI)
> + found in the MCHP Sparx5 SoC.
> +
> + If you have a Sparx5 SoC with this interface, say Y or M here.
> +
> + If unsure, say N.
> +
> config MMC_SDHCI_CADENCE
> tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller"
> depends on MMC_SDHCI_PLTFM
> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> index 4d5bcb0144a0a..451c25fc2c692 100644
> --- a/drivers/mmc/host/Makefile
> +++ b/drivers/mmc/host/Makefile
> @@ -94,6 +94,7 @@ obj-$(CONFIG_MMC_SDHCI_OF_AT91) += sdhci-of-at91.o
> obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o
> obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o
> obj-$(CONFIG_MMC_SDHCI_OF_DWCMSHC) += sdhci-of-dwcmshc.o
> +obj-$(CONFIG_MMC_SDHCI_OF_SPARX5) += sdhci-of-sparx5.o
> obj-$(CONFIG_MMC_SDHCI_BCM_KONA) += sdhci-bcm-kona.o
> obj-$(CONFIG_MMC_SDHCI_IPROC) += sdhci-iproc.o
> obj-$(CONFIG_MMC_SDHCI_MSM) += sdhci-msm.o
> diff --git a/drivers/mmc/host/sdhci-of-sparx5.c b/drivers/mmc/host/sdhci-of-sparx5.c
> new file mode 100644
> index 0000000000000..2b262c12e5530
> --- /dev/null
> +++ b/drivers/mmc/host/sdhci-of-sparx5.c
> @@ -0,0 +1,269 @@
> +// SPDX-License-Identifier: GPL-2.0-or-later
> +/*
> + * drivers/mmc/host/sdhci-of-sparx5.c
> + *
> + * MCHP Sparx5 SoC Secure Digital Host Controller Interface.
> + *
> + * Copyright (c) 2019 Microchip Inc.
> + *
> + * Author: Lars Povlsen <lars.povlsen@microchip.com>
> + */
> +
> +#include <linux/sizes.h>
> +#include <linux/delay.h>
> +#include <linux/module.h>
> +#include <linux/regmap.h>
> +#include <linux/of_device.h>
> +#include <linux/mfd/syscon.h>
> +#include <linux/dma-mapping.h>
> +
> +#include "sdhci-pltfm.h"
> +
> +#define CPU_REGS_GENERAL_CTRL (0x22 * 4)
> +#define MSHC_DLY_CC_MASK GENMASK(16, 13)
> +#define MSHC_DLY_CC_SHIFT 13
> +#define MSHC_DLY_CC_MAX 15
> +
> +#define CPU_REGS_PROC_CTRL (0x2C * 4)
> +#define ACP_CACHE_FORCE_ENA BIT(4)
> +#define ACP_AWCACHE BIT(3)
> +#define ACP_ARCACHE BIT(2)
> +#define ACP_CACHE_MASK (ACP_CACHE_FORCE_ENA|ACP_AWCACHE|ACP_ARCACHE)
> +
> +#define MSHC2_VERSION 0x500 /* Off 0x140, reg 0x0 */
> +#define MSHC2_TYPE 0x504 /* Off 0x140, reg 0x1 */
> +#define MSHC2_EMMC_CTRL 0x52c /* Off 0x140, reg 0xB */
> +#define MSHC2_EMMC_CTRL_EMMC_RST_N BIT(2)
> +#define MSHC2_EMMC_CTRL_IS_EMMC BIT(0)
> +
> +struct sdhci_sparx5_data {
> + struct sdhci_host *host;
> + struct regmap *cpu_ctrl;
> + int delay_clock;
> +};
> +
> +#define BOUNDARY_OK(addr, len) \
> + ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
> +
> +/*
> + * If DMA addr spans 128MB boundary, we split the DMA transfer into two
> + * so that each DMA transfer doesn't exceed the boundary.
> + */
> +static void sdhci_sparx5_adma_write_desc(struct sdhci_host *host, void **desc,
> + dma_addr_t addr, int len,
> + unsigned int cmd)
> +{
> + int tmplen, offset;
> +
> + if (likely(!len || BOUNDARY_OK(addr, len))) {
> + sdhci_adma_write_desc(host, desc, addr, len, cmd);
> + return;
> + }
> +
> + pr_debug("%s: write_desc: splitting dma len %d, offset 0x%0llx\n",
> + mmc_hostname(host->mmc), len, addr);
> +
> + offset = addr & (SZ_128M - 1);
> + tmplen = SZ_128M - offset;
> + sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
> +
> + addr += tmplen;
> + len -= tmplen;
> + sdhci_adma_write_desc(host, desc, addr, len, cmd);
> +}
> +
> +static void sparx5_set_cacheable(struct sdhci_host *host, u32 value)
> +{
> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> + struct sdhci_sparx5_data *sdhci_sparx5 = sdhci_pltfm_priv(pltfm_host);
> +
> + pr_debug("%s: Set Cacheable = 0x%x\n", mmc_hostname(host->mmc), value);
> +
> + /* Update ACP caching attributes in HW */
> + regmap_update_bits(sdhci_sparx5->cpu_ctrl,
> + CPU_REGS_PROC_CTRL, ACP_CACHE_MASK, value);
> +}
> +
> +static void sparx5_set_delay(struct sdhci_host *host, u8 value)
> +{
> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> + struct sdhci_sparx5_data *sdhci_sparx5 = sdhci_pltfm_priv(pltfm_host);
> +
> + pr_debug("%s: Set DLY_CC = %u\n", mmc_hostname(host->mmc), value);
> +
> + /* Update DLY_CC in HW */
> + regmap_update_bits(sdhci_sparx5->cpu_ctrl,
> + CPU_REGS_GENERAL_CTRL,
> + MSHC_DLY_CC_MASK,
> + (value << MSHC_DLY_CC_SHIFT));
> +}
> +
> +static void sdhci_sparx5_set_emmc(struct sdhci_host *host)
> +{
> + if (!mmc_card_is_removable(host->mmc)) {
> + u8 value;
> +
> + value = sdhci_readb(host, MSHC2_EMMC_CTRL);
> + if (!(value & MSHC2_EMMC_CTRL_IS_EMMC)) {
> + value |= MSHC2_EMMC_CTRL_IS_EMMC;
> + pr_debug("%s: Set EMMC_CTRL: 0x%08x\n",
> + mmc_hostname(host->mmc), value);
> + sdhci_writeb(host, value, MSHC2_EMMC_CTRL);
> + }
> + }
> +}
> +
> +static void sdhci_sparx5_reset_emmc(struct sdhci_host *host)
> +{
> + u8 value;
> +
> + pr_debug("%s: Toggle EMMC_CTRL.EMMC_RST_N\n", mmc_hostname(host->mmc));
> + value = sdhci_readb(host, MSHC2_EMMC_CTRL) &
> + ~MSHC2_EMMC_CTRL_EMMC_RST_N;
> + sdhci_writeb(host, value, MSHC2_EMMC_CTRL);
> + /* For eMMC, minimum is 1us but give it 10us for good measure */
> + usleep_range(10, 20);
> + sdhci_writeb(host, value | MSHC2_EMMC_CTRL_EMMC_RST_N,
> + MSHC2_EMMC_CTRL);
> + /* For eMMC, minimum is 200us but give it 300us for good measure */
> + usleep_range(300, 400);
> +}
> +
> +static void sdhci_sparx5_reset(struct sdhci_host *host, u8 mask)
> +{
> + pr_debug("%s: *** RESET: mask %d\n", mmc_hostname(host->mmc), mask);
> +
> + sdhci_reset(host, mask);
> +
> + /* Be sure CARD_IS_EMMC stays set */
> + sdhci_sparx5_set_emmc(host);
> +}
> +
> +static const struct sdhci_ops sdhci_sparx5_ops = {
> + .set_clock = sdhci_set_clock,
> + .set_bus_width = sdhci_set_bus_width,
> + .set_uhs_signaling = sdhci_set_uhs_signaling,
> + .get_max_clock = sdhci_pltfm_clk_get_max_clock,
> + .reset = sdhci_sparx5_reset,
> + .adma_write_desc = sdhci_sparx5_adma_write_desc,
> +};
> +
> +static const struct sdhci_pltfm_data sdhci_sparx5_pdata = {
> + .quirks = 0,
> + .quirks2 = SDHCI_QUIRK2_HOST_NO_CMD23 | /* Controller issue */
> + SDHCI_QUIRK2_NO_1_8_V, /* No sdr104, ddr50, etc */
> + .ops = &sdhci_sparx5_ops,
> +};
> +
> +int sdhci_sparx5_probe(struct platform_device *pdev)
> +{
> + int ret;
> + const char *syscon = "microchip,sparx5-cpu-syscon";
> + struct sdhci_host *host;
> + struct sdhci_pltfm_host *pltfm_host;
> + struct sdhci_sparx5_data *sdhci_sparx5;
> + struct device_node *np = pdev->dev.of_node;
> + u32 value;
> + u32 extra;
> +
> + host = sdhci_pltfm_init(pdev, &sdhci_sparx5_pdata,
> + sizeof(*sdhci_sparx5));
> +
> + if (IS_ERR(host))
> + return PTR_ERR(host);
> +
> + /*
> + * extra adma table cnt for cross 128M boundary handling.
> + */
> + extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev), SZ_128M);
> + if (extra > SDHCI_MAX_SEGS)
> + extra = SDHCI_MAX_SEGS;
> + host->adma_table_cnt += extra;
> +
> + pltfm_host = sdhci_priv(host);
> + sdhci_sparx5 = sdhci_pltfm_priv(pltfm_host);
> + sdhci_sparx5->host = host;
> +
> + pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
> + if (IS_ERR(pltfm_host->clk)) {
> + ret = PTR_ERR(pltfm_host->clk);
> + dev_err(&pdev->dev, "failed to get core clk: %d\n", ret);
> + goto free_pltfm;
> + }
> + ret = clk_prepare_enable(pltfm_host->clk);
> + if (ret)
> + goto free_pltfm;
> +
> + if (!of_property_read_u32(np, "microchip,clock-delay", &value) &&
> + (value > 0 && value <= MSHC_DLY_CC_MAX))
> + sdhci_sparx5->delay_clock = value;
> +
> + sdhci_get_of_property(pdev);
> +
> + ret = mmc_of_parse(host->mmc);
> + if (ret)
> + goto err_clk;
> +
> + sdhci_sparx5->cpu_ctrl = syscon_regmap_lookup_by_compatible(syscon);
> + if (IS_ERR(sdhci_sparx5->cpu_ctrl)) {
> + dev_err(&pdev->dev, "No CPU syscon regmap !\n");
> + ret = PTR_ERR(sdhci_sparx5->cpu_ctrl);
> + goto err_clk;
> + }
> +
> + if (sdhci_sparx5->delay_clock >= 0)
> + sparx5_set_delay(host, sdhci_sparx5->delay_clock);
> +
> + if (!mmc_card_is_removable(host->mmc)) {
> + /* Do a HW reset of eMMC card */
> + sdhci_sparx5_reset_emmc(host);
> + /* Update EMMC_CTRL */
> + sdhci_sparx5_set_emmc(host);
> + /* If eMMC, disable SD and SDIO */
> + host->mmc->caps2 |= (MMC_CAP2_NO_SDIO|MMC_CAP2_NO_SD);
> + }
> +
> + ret = sdhci_add_host(host);
> + if (ret)
> + goto err_clk;
> +
> + /* Set AXI bus master to use un-cached access (for DMA) */
> + if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA) &&
> + IS_ENABLED(CONFIG_DMA_DECLARE_COHERENT))
> + sparx5_set_cacheable(host, ACP_CACHE_FORCE_ENA);
> +
> + pr_debug("%s: SDHC version: 0x%08x\n",
> + mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_VERSION));
> + pr_debug("%s: SDHC type: 0x%08x\n",
> + mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_TYPE));
> +
> + return ret;
> +
> +err_clk:
> + clk_disable_unprepare(pltfm_host->clk);
> +free_pltfm:
> + sdhci_pltfm_free(pdev);
> + return ret;
> +}
> +
> +static const struct of_device_id sdhci_sparx5_of_match[] = {
> + { .compatible = "microchip,dw-sparx5-sdhci" },
> + { }
> +};
> +MODULE_DEVICE_TABLE(of, sdhci_sparx5_of_match);
> +
> +static struct platform_driver sdhci_sparx5_driver = {
> + .driver = {
> + .name = "sdhci-sparx5",
> + .of_match_table = sdhci_sparx5_of_match,
> + .pm = &sdhci_pltfm_pmops,
> + },
> + .probe = sdhci_sparx5_probe,
> + .remove = sdhci_pltfm_unregister,
> +};
> +
> +module_platform_driver(sdhci_sparx5_driver);
> +
> +MODULE_DESCRIPTION("Sparx5 SDHCI OF driver");
> +MODULE_AUTHOR("Lars Povlsen <lars.povlsen@microchip.com>");
> +MODULE_LICENSE("GPL v2");
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v4 1/3] dt-bindings: mmc: Add Sparx5 SDHCI controller bindings
2020-06-18 14:13 ` [PATCH v4 1/3] dt-bindings: mmc: Add Sparx5 SDHCI controller bindings Lars Povlsen
@ 2020-06-29 21:54 ` Rob Herring
0 siblings, 0 replies; 11+ messages in thread
From: Rob Herring @ 2020-06-29 21:54 UTC (permalink / raw)
To: Lars Povlsen
Cc: linux-kernel, devicetree, SoC Team, Rob Herring, Ulf Hansson,
Adrian Hunter, linux-mmc, Microchip Linux Driver Support,
linux-arm-kernel, Alexandre Belloni
On Thu, 18 Jun 2020 16:13:24 +0200, Lars Povlsen wrote:
> The Sparx5 SDHCI controller is based on the Designware controller IP.
>
> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
> ---
> .../mmc/microchip,dw-sparx5-sdhci.yaml | 65 +++++++++++++++++++
> 1 file changed, 65 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml
>
My bot found errors running 'make dt_binding_check' on your patch:
Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.example.dts:20:18: fatal error: dt-bindings/clock/microchip,sparx5.h: No such file or directory
#include <dt-bindings/clock/microchip,sparx5.h>
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
compilation terminated.
scripts/Makefile.lib:315: recipe for target 'Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.example.dt.yaml' failed
make[1]: *** [Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.example.dt.yaml] Error 1
make[1]: *** Waiting for unfinished jobs....
Makefile:1347: recipe for target 'dt_binding_check' failed
make: *** [dt_binding_check] Error 2
See https://patchwork.ozlabs.org/patch/1312158
If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure dt-schema is up to date:
pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade
Please check and re-submit.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v4 2/3] sdhci: sparx5: Add Sparx5 SoC eMMC driver
2020-06-18 14:43 ` Adrian Hunter
@ 2020-07-22 11:54 ` Lars Povlsen
2020-07-24 10:47 ` Ulf Hansson
0 siblings, 1 reply; 11+ messages in thread
From: Lars Povlsen @ 2020-07-22 11:54 UTC (permalink / raw)
To: Adrian Hunter
Cc: Lars Povlsen, Ulf Hansson, SoC Team,
Microchip Linux Driver Support, linux-mmc, devicetree,
linux-arm-kernel, linux-kernel, Alexandre Belloni
Adrian Hunter writes:
> On 18/06/20 5:13 pm, Lars Povlsen wrote:
>> This adds the eMMC driver for the Sparx5 SoC. It is based upon the
>> designware IP, but requires some extra initialization and quirks.
>>
>> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
>
> Acked-by: Adrian Hunter <adrian.hunter@intel.com>
>
Adrian,
Thanks for the ack. I was expecting to see this in linux-next, anything
holding it back?
pinctrl and hwmon drivers have been merged.
Thanks,
---Lars
>> ---
>> drivers/mmc/host/Kconfig | 13 ++
>> drivers/mmc/host/Makefile | 1 +
>> drivers/mmc/host/sdhci-of-sparx5.c | 269 +++++++++++++++++++++++++++++
>> 3 files changed, 283 insertions(+)
>> create mode 100644 drivers/mmc/host/sdhci-of-sparx5.c
>>
>> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
>> index 3b706af35ec31..a3bad4b4ed7ea 100644
>> --- a/drivers/mmc/host/Kconfig
>> +++ b/drivers/mmc/host/Kconfig
>> @@ -213,6 +213,19 @@ config MMC_SDHCI_OF_DWCMSHC
>> If you have a controller with this interface, say Y or M here.
>> If unsure, say N.
>>
>> +config MMC_SDHCI_OF_SPARX5
>> + tristate "SDHCI OF support for the MCHP Sparx5 SoC"
>> + depends on MMC_SDHCI_PLTFM
>> + depends on ARCH_SPARX5
>> + select MMC_SDHCI_IO_ACCESSORS
>> + help
>> + This selects the Secure Digital Host Controller Interface (SDHCI)
>> + found in the MCHP Sparx5 SoC.
>> +
>> + If you have a Sparx5 SoC with this interface, say Y or M here.
>> +
>> + If unsure, say N.
>> +
>> config MMC_SDHCI_CADENCE
>> tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller"
>> depends on MMC_SDHCI_PLTFM
>> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
>> index 4d5bcb0144a0a..451c25fc2c692 100644
>> --- a/drivers/mmc/host/Makefile
>> +++ b/drivers/mmc/host/Makefile
>> @@ -94,6 +94,7 @@ obj-$(CONFIG_MMC_SDHCI_OF_AT91) += sdhci-of-at91.o
>> obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o
>> obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o
>> obj-$(CONFIG_MMC_SDHCI_OF_DWCMSHC) += sdhci-of-dwcmshc.o
>> +obj-$(CONFIG_MMC_SDHCI_OF_SPARX5) += sdhci-of-sparx5.o
>> obj-$(CONFIG_MMC_SDHCI_BCM_KONA) += sdhci-bcm-kona.o
>> obj-$(CONFIG_MMC_SDHCI_IPROC) += sdhci-iproc.o
>> obj-$(CONFIG_MMC_SDHCI_MSM) += sdhci-msm.o
>> diff --git a/drivers/mmc/host/sdhci-of-sparx5.c b/drivers/mmc/host/sdhci-of-sparx5.c
>> new file mode 100644
>> index 0000000000000..2b262c12e5530
>> --- /dev/null
>> +++ b/drivers/mmc/host/sdhci-of-sparx5.c
>> @@ -0,0 +1,269 @@
>> +// SPDX-License-Identifier: GPL-2.0-or-later
>> +/*
>> + * drivers/mmc/host/sdhci-of-sparx5.c
>> + *
>> + * MCHP Sparx5 SoC Secure Digital Host Controller Interface.
>> + *
>> + * Copyright (c) 2019 Microchip Inc.
>> + *
>> + * Author: Lars Povlsen <lars.povlsen@microchip.com>
>> + */
>> +
>> +#include <linux/sizes.h>
>> +#include <linux/delay.h>
>> +#include <linux/module.h>
>> +#include <linux/regmap.h>
>> +#include <linux/of_device.h>
>> +#include <linux/mfd/syscon.h>
>> +#include <linux/dma-mapping.h>
>> +
>> +#include "sdhci-pltfm.h"
>> +
>> +#define CPU_REGS_GENERAL_CTRL (0x22 * 4)
>> +#define MSHC_DLY_CC_MASK GENMASK(16, 13)
>> +#define MSHC_DLY_CC_SHIFT 13
>> +#define MSHC_DLY_CC_MAX 15
>> +
>> +#define CPU_REGS_PROC_CTRL (0x2C * 4)
>> +#define ACP_CACHE_FORCE_ENA BIT(4)
>> +#define ACP_AWCACHE BIT(3)
>> +#define ACP_ARCACHE BIT(2)
>> +#define ACP_CACHE_MASK (ACP_CACHE_FORCE_ENA|ACP_AWCACHE|ACP_ARCACHE)
>> +
>> +#define MSHC2_VERSION 0x500 /* Off 0x140, reg 0x0 */
>> +#define MSHC2_TYPE 0x504 /* Off 0x140, reg 0x1 */
>> +#define MSHC2_EMMC_CTRL 0x52c /* Off 0x140, reg 0xB */
>> +#define MSHC2_EMMC_CTRL_EMMC_RST_N BIT(2)
>> +#define MSHC2_EMMC_CTRL_IS_EMMC BIT(0)
>> +
>> +struct sdhci_sparx5_data {
>> + struct sdhci_host *host;
>> + struct regmap *cpu_ctrl;
>> + int delay_clock;
>> +};
>> +
>> +#define BOUNDARY_OK(addr, len) \
>> + ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
>> +
>> +/*
>> + * If DMA addr spans 128MB boundary, we split the DMA transfer into two
>> + * so that each DMA transfer doesn't exceed the boundary.
>> + */
>> +static void sdhci_sparx5_adma_write_desc(struct sdhci_host *host, void **desc,
>> + dma_addr_t addr, int len,
>> + unsigned int cmd)
>> +{
>> + int tmplen, offset;
>> +
>> + if (likely(!len || BOUNDARY_OK(addr, len))) {
>> + sdhci_adma_write_desc(host, desc, addr, len, cmd);
>> + return;
>> + }
>> +
>> + pr_debug("%s: write_desc: splitting dma len %d, offset 0x%0llx\n",
>> + mmc_hostname(host->mmc), len, addr);
>> +
>> + offset = addr & (SZ_128M - 1);
>> + tmplen = SZ_128M - offset;
>> + sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
>> +
>> + addr += tmplen;
>> + len -= tmplen;
>> + sdhci_adma_write_desc(host, desc, addr, len, cmd);
>> +}
>> +
>> +static void sparx5_set_cacheable(struct sdhci_host *host, u32 value)
>> +{
>> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
>> + struct sdhci_sparx5_data *sdhci_sparx5 = sdhci_pltfm_priv(pltfm_host);
>> +
>> + pr_debug("%s: Set Cacheable = 0x%x\n", mmc_hostname(host->mmc), value);
>> +
>> + /* Update ACP caching attributes in HW */
>> + regmap_update_bits(sdhci_sparx5->cpu_ctrl,
>> + CPU_REGS_PROC_CTRL, ACP_CACHE_MASK, value);
>> +}
>> +
>> +static void sparx5_set_delay(struct sdhci_host *host, u8 value)
>> +{
>> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
>> + struct sdhci_sparx5_data *sdhci_sparx5 = sdhci_pltfm_priv(pltfm_host);
>> +
>> + pr_debug("%s: Set DLY_CC = %u\n", mmc_hostname(host->mmc), value);
>> +
>> + /* Update DLY_CC in HW */
>> + regmap_update_bits(sdhci_sparx5->cpu_ctrl,
>> + CPU_REGS_GENERAL_CTRL,
>> + MSHC_DLY_CC_MASK,
>> + (value << MSHC_DLY_CC_SHIFT));
>> +}
>> +
>> +static void sdhci_sparx5_set_emmc(struct sdhci_host *host)
>> +{
>> + if (!mmc_card_is_removable(host->mmc)) {
>> + u8 value;
>> +
>> + value = sdhci_readb(host, MSHC2_EMMC_CTRL);
>> + if (!(value & MSHC2_EMMC_CTRL_IS_EMMC)) {
>> + value |= MSHC2_EMMC_CTRL_IS_EMMC;
>> + pr_debug("%s: Set EMMC_CTRL: 0x%08x\n",
>> + mmc_hostname(host->mmc), value);
>> + sdhci_writeb(host, value, MSHC2_EMMC_CTRL);
>> + }
>> + }
>> +}
>> +
>> +static void sdhci_sparx5_reset_emmc(struct sdhci_host *host)
>> +{
>> + u8 value;
>> +
>> + pr_debug("%s: Toggle EMMC_CTRL.EMMC_RST_N\n", mmc_hostname(host->mmc));
>> + value = sdhci_readb(host, MSHC2_EMMC_CTRL) &
>> + ~MSHC2_EMMC_CTRL_EMMC_RST_N;
>> + sdhci_writeb(host, value, MSHC2_EMMC_CTRL);
>> + /* For eMMC, minimum is 1us but give it 10us for good measure */
>> + usleep_range(10, 20);
>> + sdhci_writeb(host, value | MSHC2_EMMC_CTRL_EMMC_RST_N,
>> + MSHC2_EMMC_CTRL);
>> + /* For eMMC, minimum is 200us but give it 300us for good measure */
>> + usleep_range(300, 400);
>> +}
>> +
>> +static void sdhci_sparx5_reset(struct sdhci_host *host, u8 mask)
>> +{
>> + pr_debug("%s: *** RESET: mask %d\n", mmc_hostname(host->mmc), mask);
>> +
>> + sdhci_reset(host, mask);
>> +
>> + /* Be sure CARD_IS_EMMC stays set */
>> + sdhci_sparx5_set_emmc(host);
>> +}
>> +
>> +static const struct sdhci_ops sdhci_sparx5_ops = {
>> + .set_clock = sdhci_set_clock,
>> + .set_bus_width = sdhci_set_bus_width,
>> + .set_uhs_signaling = sdhci_set_uhs_signaling,
>> + .get_max_clock = sdhci_pltfm_clk_get_max_clock,
>> + .reset = sdhci_sparx5_reset,
>> + .adma_write_desc = sdhci_sparx5_adma_write_desc,
>> +};
>> +
>> +static const struct sdhci_pltfm_data sdhci_sparx5_pdata = {
>> + .quirks = 0,
>> + .quirks2 = SDHCI_QUIRK2_HOST_NO_CMD23 | /* Controller issue */
>> + SDHCI_QUIRK2_NO_1_8_V, /* No sdr104, ddr50, etc */
>> + .ops = &sdhci_sparx5_ops,
>> +};
>> +
>> +int sdhci_sparx5_probe(struct platform_device *pdev)
>> +{
>> + int ret;
>> + const char *syscon = "microchip,sparx5-cpu-syscon";
>> + struct sdhci_host *host;
>> + struct sdhci_pltfm_host *pltfm_host;
>> + struct sdhci_sparx5_data *sdhci_sparx5;
>> + struct device_node *np = pdev->dev.of_node;
>> + u32 value;
>> + u32 extra;
>> +
>> + host = sdhci_pltfm_init(pdev, &sdhci_sparx5_pdata,
>> + sizeof(*sdhci_sparx5));
>> +
>> + if (IS_ERR(host))
>> + return PTR_ERR(host);
>> +
>> + /*
>> + * extra adma table cnt for cross 128M boundary handling.
>> + */
>> + extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev), SZ_128M);
>> + if (extra > SDHCI_MAX_SEGS)
>> + extra = SDHCI_MAX_SEGS;
>> + host->adma_table_cnt += extra;
>> +
>> + pltfm_host = sdhci_priv(host);
>> + sdhci_sparx5 = sdhci_pltfm_priv(pltfm_host);
>> + sdhci_sparx5->host = host;
>> +
>> + pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
>> + if (IS_ERR(pltfm_host->clk)) {
>> + ret = PTR_ERR(pltfm_host->clk);
>> + dev_err(&pdev->dev, "failed to get core clk: %d\n", ret);
>> + goto free_pltfm;
>> + }
>> + ret = clk_prepare_enable(pltfm_host->clk);
>> + if (ret)
>> + goto free_pltfm;
>> +
>> + if (!of_property_read_u32(np, "microchip,clock-delay", &value) &&
>> + (value > 0 && value <= MSHC_DLY_CC_MAX))
>> + sdhci_sparx5->delay_clock = value;
>> +
>> + sdhci_get_of_property(pdev);
>> +
>> + ret = mmc_of_parse(host->mmc);
>> + if (ret)
>> + goto err_clk;
>> +
>> + sdhci_sparx5->cpu_ctrl = syscon_regmap_lookup_by_compatible(syscon);
>> + if (IS_ERR(sdhci_sparx5->cpu_ctrl)) {
>> + dev_err(&pdev->dev, "No CPU syscon regmap !\n");
>> + ret = PTR_ERR(sdhci_sparx5->cpu_ctrl);
>> + goto err_clk;
>> + }
>> +
>> + if (sdhci_sparx5->delay_clock >= 0)
>> + sparx5_set_delay(host, sdhci_sparx5->delay_clock);
>> +
>> + if (!mmc_card_is_removable(host->mmc)) {
>> + /* Do a HW reset of eMMC card */
>> + sdhci_sparx5_reset_emmc(host);
>> + /* Update EMMC_CTRL */
>> + sdhci_sparx5_set_emmc(host);
>> + /* If eMMC, disable SD and SDIO */
>> + host->mmc->caps2 |= (MMC_CAP2_NO_SDIO|MMC_CAP2_NO_SD);
>> + }
>> +
>> + ret = sdhci_add_host(host);
>> + if (ret)
>> + goto err_clk;
>> +
>> + /* Set AXI bus master to use un-cached access (for DMA) */
>> + if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA) &&
>> + IS_ENABLED(CONFIG_DMA_DECLARE_COHERENT))
>> + sparx5_set_cacheable(host, ACP_CACHE_FORCE_ENA);
>> +
>> + pr_debug("%s: SDHC version: 0x%08x\n",
>> + mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_VERSION));
>> + pr_debug("%s: SDHC type: 0x%08x\n",
>> + mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_TYPE));
>> +
>> + return ret;
>> +
>> +err_clk:
>> + clk_disable_unprepare(pltfm_host->clk);
>> +free_pltfm:
>> + sdhci_pltfm_free(pdev);
>> + return ret;
>> +}
>> +
>> +static const struct of_device_id sdhci_sparx5_of_match[] = {
>> + { .compatible = "microchip,dw-sparx5-sdhci" },
>> + { }
>> +};
>> +MODULE_DEVICE_TABLE(of, sdhci_sparx5_of_match);
>> +
>> +static struct platform_driver sdhci_sparx5_driver = {
>> + .driver = {
>> + .name = "sdhci-sparx5",
>> + .of_match_table = sdhci_sparx5_of_match,
>> + .pm = &sdhci_pltfm_pmops,
>> + },
>> + .probe = sdhci_sparx5_probe,
>> + .remove = sdhci_pltfm_unregister,
>> +};
>> +
>> +module_platform_driver(sdhci_sparx5_driver);
>> +
>> +MODULE_DESCRIPTION("Sparx5 SDHCI OF driver");
>> +MODULE_AUTHOR("Lars Povlsen <lars.povlsen@microchip.com>");
>> +MODULE_LICENSE("GPL v2");
>>
--
Lars Povlsen,
Microchip
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v4 2/3] sdhci: sparx5: Add Sparx5 SoC eMMC driver
2020-07-22 11:54 ` Lars Povlsen
@ 2020-07-24 10:47 ` Ulf Hansson
2020-07-24 11:32 ` Lars Povlsen
0 siblings, 1 reply; 11+ messages in thread
From: Ulf Hansson @ 2020-07-24 10:47 UTC (permalink / raw)
To: Lars Povlsen
Cc: Adrian Hunter, SoC Team, Microchip Linux Driver Support,
linux-mmc, DTML, Linux ARM, Linux Kernel Mailing List,
Alexandre Belloni
On Wed, 22 Jul 2020 at 13:54, Lars Povlsen <lars.povlsen@microchip.com> wrote:
>
>
> Adrian Hunter writes:
>
> > On 18/06/20 5:13 pm, Lars Povlsen wrote:
> >> This adds the eMMC driver for the Sparx5 SoC. It is based upon the
> >> designware IP, but requires some extra initialization and quirks.
> >>
> >> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
> >
> > Acked-by: Adrian Hunter <adrian.hunter@intel.com>
> >
>
> Adrian,
>
> Thanks for the ack. I was expecting to see this in linux-next, anything
> holding it back?
>
> pinctrl and hwmon drivers have been merged.
>
> Thanks,
Hi Lars,
Looks like you got some feedback on the DT patch (patch1/3) from Rob.
I didn't find that you have addressed them and therefore I am holding
back on the $subject patch as well.
Please fix the DT patch and re-submit a new version of the series.
Kind regards
Uffe
>
> ---Lars
>
> >> ---
> >> drivers/mmc/host/Kconfig | 13 ++
> >> drivers/mmc/host/Makefile | 1 +
> >> drivers/mmc/host/sdhci-of-sparx5.c | 269 +++++++++++++++++++++++++++++
> >> 3 files changed, 283 insertions(+)
> >> create mode 100644 drivers/mmc/host/sdhci-of-sparx5.c
> >>
> >> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
> >> index 3b706af35ec31..a3bad4b4ed7ea 100644
> >> --- a/drivers/mmc/host/Kconfig
> >> +++ b/drivers/mmc/host/Kconfig
> >> @@ -213,6 +213,19 @@ config MMC_SDHCI_OF_DWCMSHC
> >> If you have a controller with this interface, say Y or M here.
> >> If unsure, say N.
> >>
> >> +config MMC_SDHCI_OF_SPARX5
> >> + tristate "SDHCI OF support for the MCHP Sparx5 SoC"
> >> + depends on MMC_SDHCI_PLTFM
> >> + depends on ARCH_SPARX5
> >> + select MMC_SDHCI_IO_ACCESSORS
> >> + help
> >> + This selects the Secure Digital Host Controller Interface (SDHCI)
> >> + found in the MCHP Sparx5 SoC.
> >> +
> >> + If you have a Sparx5 SoC with this interface, say Y or M here.
> >> +
> >> + If unsure, say N.
> >> +
> >> config MMC_SDHCI_CADENCE
> >> tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller"
> >> depends on MMC_SDHCI_PLTFM
> >> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
> >> index 4d5bcb0144a0a..451c25fc2c692 100644
> >> --- a/drivers/mmc/host/Makefile
> >> +++ b/drivers/mmc/host/Makefile
> >> @@ -94,6 +94,7 @@ obj-$(CONFIG_MMC_SDHCI_OF_AT91) += sdhci-of-at91.o
> >> obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o
> >> obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o
> >> obj-$(CONFIG_MMC_SDHCI_OF_DWCMSHC) += sdhci-of-dwcmshc.o
> >> +obj-$(CONFIG_MMC_SDHCI_OF_SPARX5) += sdhci-of-sparx5.o
> >> obj-$(CONFIG_MMC_SDHCI_BCM_KONA) += sdhci-bcm-kona.o
> >> obj-$(CONFIG_MMC_SDHCI_IPROC) += sdhci-iproc.o
> >> obj-$(CONFIG_MMC_SDHCI_MSM) += sdhci-msm.o
> >> diff --git a/drivers/mmc/host/sdhci-of-sparx5.c b/drivers/mmc/host/sdhci-of-sparx5.c
> >> new file mode 100644
> >> index 0000000000000..2b262c12e5530
> >> --- /dev/null
> >> +++ b/drivers/mmc/host/sdhci-of-sparx5.c
> >> @@ -0,0 +1,269 @@
> >> +// SPDX-License-Identifier: GPL-2.0-or-later
> >> +/*
> >> + * drivers/mmc/host/sdhci-of-sparx5.c
> >> + *
> >> + * MCHP Sparx5 SoC Secure Digital Host Controller Interface.
> >> + *
> >> + * Copyright (c) 2019 Microchip Inc.
> >> + *
> >> + * Author: Lars Povlsen <lars.povlsen@microchip.com>
> >> + */
> >> +
> >> +#include <linux/sizes.h>
> >> +#include <linux/delay.h>
> >> +#include <linux/module.h>
> >> +#include <linux/regmap.h>
> >> +#include <linux/of_device.h>
> >> +#include <linux/mfd/syscon.h>
> >> +#include <linux/dma-mapping.h>
> >> +
> >> +#include "sdhci-pltfm.h"
> >> +
> >> +#define CPU_REGS_GENERAL_CTRL (0x22 * 4)
> >> +#define MSHC_DLY_CC_MASK GENMASK(16, 13)
> >> +#define MSHC_DLY_CC_SHIFT 13
> >> +#define MSHC_DLY_CC_MAX 15
> >> +
> >> +#define CPU_REGS_PROC_CTRL (0x2C * 4)
> >> +#define ACP_CACHE_FORCE_ENA BIT(4)
> >> +#define ACP_AWCACHE BIT(3)
> >> +#define ACP_ARCACHE BIT(2)
> >> +#define ACP_CACHE_MASK (ACP_CACHE_FORCE_ENA|ACP_AWCACHE|ACP_ARCACHE)
> >> +
> >> +#define MSHC2_VERSION 0x500 /* Off 0x140, reg 0x0 */
> >> +#define MSHC2_TYPE 0x504 /* Off 0x140, reg 0x1 */
> >> +#define MSHC2_EMMC_CTRL 0x52c /* Off 0x140, reg 0xB */
> >> +#define MSHC2_EMMC_CTRL_EMMC_RST_N BIT(2)
> >> +#define MSHC2_EMMC_CTRL_IS_EMMC BIT(0)
> >> +
> >> +struct sdhci_sparx5_data {
> >> + struct sdhci_host *host;
> >> + struct regmap *cpu_ctrl;
> >> + int delay_clock;
> >> +};
> >> +
> >> +#define BOUNDARY_OK(addr, len) \
> >> + ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
> >> +
> >> +/*
> >> + * If DMA addr spans 128MB boundary, we split the DMA transfer into two
> >> + * so that each DMA transfer doesn't exceed the boundary.
> >> + */
> >> +static void sdhci_sparx5_adma_write_desc(struct sdhci_host *host, void **desc,
> >> + dma_addr_t addr, int len,
> >> + unsigned int cmd)
> >> +{
> >> + int tmplen, offset;
> >> +
> >> + if (likely(!len || BOUNDARY_OK(addr, len))) {
> >> + sdhci_adma_write_desc(host, desc, addr, len, cmd);
> >> + return;
> >> + }
> >> +
> >> + pr_debug("%s: write_desc: splitting dma len %d, offset 0x%0llx\n",
> >> + mmc_hostname(host->mmc), len, addr);
> >> +
> >> + offset = addr & (SZ_128M - 1);
> >> + tmplen = SZ_128M - offset;
> >> + sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
> >> +
> >> + addr += tmplen;
> >> + len -= tmplen;
> >> + sdhci_adma_write_desc(host, desc, addr, len, cmd);
> >> +}
> >> +
> >> +static void sparx5_set_cacheable(struct sdhci_host *host, u32 value)
> >> +{
> >> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> >> + struct sdhci_sparx5_data *sdhci_sparx5 = sdhci_pltfm_priv(pltfm_host);
> >> +
> >> + pr_debug("%s: Set Cacheable = 0x%x\n", mmc_hostname(host->mmc), value);
> >> +
> >> + /* Update ACP caching attributes in HW */
> >> + regmap_update_bits(sdhci_sparx5->cpu_ctrl,
> >> + CPU_REGS_PROC_CTRL, ACP_CACHE_MASK, value);
> >> +}
> >> +
> >> +static void sparx5_set_delay(struct sdhci_host *host, u8 value)
> >> +{
> >> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
> >> + struct sdhci_sparx5_data *sdhci_sparx5 = sdhci_pltfm_priv(pltfm_host);
> >> +
> >> + pr_debug("%s: Set DLY_CC = %u\n", mmc_hostname(host->mmc), value);
> >> +
> >> + /* Update DLY_CC in HW */
> >> + regmap_update_bits(sdhci_sparx5->cpu_ctrl,
> >> + CPU_REGS_GENERAL_CTRL,
> >> + MSHC_DLY_CC_MASK,
> >> + (value << MSHC_DLY_CC_SHIFT));
> >> +}
> >> +
> >> +static void sdhci_sparx5_set_emmc(struct sdhci_host *host)
> >> +{
> >> + if (!mmc_card_is_removable(host->mmc)) {
> >> + u8 value;
> >> +
> >> + value = sdhci_readb(host, MSHC2_EMMC_CTRL);
> >> + if (!(value & MSHC2_EMMC_CTRL_IS_EMMC)) {
> >> + value |= MSHC2_EMMC_CTRL_IS_EMMC;
> >> + pr_debug("%s: Set EMMC_CTRL: 0x%08x\n",
> >> + mmc_hostname(host->mmc), value);
> >> + sdhci_writeb(host, value, MSHC2_EMMC_CTRL);
> >> + }
> >> + }
> >> +}
> >> +
> >> +static void sdhci_sparx5_reset_emmc(struct sdhci_host *host)
> >> +{
> >> + u8 value;
> >> +
> >> + pr_debug("%s: Toggle EMMC_CTRL.EMMC_RST_N\n", mmc_hostname(host->mmc));
> >> + value = sdhci_readb(host, MSHC2_EMMC_CTRL) &
> >> + ~MSHC2_EMMC_CTRL_EMMC_RST_N;
> >> + sdhci_writeb(host, value, MSHC2_EMMC_CTRL);
> >> + /* For eMMC, minimum is 1us but give it 10us for good measure */
> >> + usleep_range(10, 20);
> >> + sdhci_writeb(host, value | MSHC2_EMMC_CTRL_EMMC_RST_N,
> >> + MSHC2_EMMC_CTRL);
> >> + /* For eMMC, minimum is 200us but give it 300us for good measure */
> >> + usleep_range(300, 400);
> >> +}
> >> +
> >> +static void sdhci_sparx5_reset(struct sdhci_host *host, u8 mask)
> >> +{
> >> + pr_debug("%s: *** RESET: mask %d\n", mmc_hostname(host->mmc), mask);
> >> +
> >> + sdhci_reset(host, mask);
> >> +
> >> + /* Be sure CARD_IS_EMMC stays set */
> >> + sdhci_sparx5_set_emmc(host);
> >> +}
> >> +
> >> +static const struct sdhci_ops sdhci_sparx5_ops = {
> >> + .set_clock = sdhci_set_clock,
> >> + .set_bus_width = sdhci_set_bus_width,
> >> + .set_uhs_signaling = sdhci_set_uhs_signaling,
> >> + .get_max_clock = sdhci_pltfm_clk_get_max_clock,
> >> + .reset = sdhci_sparx5_reset,
> >> + .adma_write_desc = sdhci_sparx5_adma_write_desc,
> >> +};
> >> +
> >> +static const struct sdhci_pltfm_data sdhci_sparx5_pdata = {
> >> + .quirks = 0,
> >> + .quirks2 = SDHCI_QUIRK2_HOST_NO_CMD23 | /* Controller issue */
> >> + SDHCI_QUIRK2_NO_1_8_V, /* No sdr104, ddr50, etc */
> >> + .ops = &sdhci_sparx5_ops,
> >> +};
> >> +
> >> +int sdhci_sparx5_probe(struct platform_device *pdev)
> >> +{
> >> + int ret;
> >> + const char *syscon = "microchip,sparx5-cpu-syscon";
> >> + struct sdhci_host *host;
> >> + struct sdhci_pltfm_host *pltfm_host;
> >> + struct sdhci_sparx5_data *sdhci_sparx5;
> >> + struct device_node *np = pdev->dev.of_node;
> >> + u32 value;
> >> + u32 extra;
> >> +
> >> + host = sdhci_pltfm_init(pdev, &sdhci_sparx5_pdata,
> >> + sizeof(*sdhci_sparx5));
> >> +
> >> + if (IS_ERR(host))
> >> + return PTR_ERR(host);
> >> +
> >> + /*
> >> + * extra adma table cnt for cross 128M boundary handling.
> >> + */
> >> + extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev), SZ_128M);
> >> + if (extra > SDHCI_MAX_SEGS)
> >> + extra = SDHCI_MAX_SEGS;
> >> + host->adma_table_cnt += extra;
> >> +
> >> + pltfm_host = sdhci_priv(host);
> >> + sdhci_sparx5 = sdhci_pltfm_priv(pltfm_host);
> >> + sdhci_sparx5->host = host;
> >> +
> >> + pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
> >> + if (IS_ERR(pltfm_host->clk)) {
> >> + ret = PTR_ERR(pltfm_host->clk);
> >> + dev_err(&pdev->dev, "failed to get core clk: %d\n", ret);
> >> + goto free_pltfm;
> >> + }
> >> + ret = clk_prepare_enable(pltfm_host->clk);
> >> + if (ret)
> >> + goto free_pltfm;
> >> +
> >> + if (!of_property_read_u32(np, "microchip,clock-delay", &value) &&
> >> + (value > 0 && value <= MSHC_DLY_CC_MAX))
> >> + sdhci_sparx5->delay_clock = value;
> >> +
> >> + sdhci_get_of_property(pdev);
> >> +
> >> + ret = mmc_of_parse(host->mmc);
> >> + if (ret)
> >> + goto err_clk;
> >> +
> >> + sdhci_sparx5->cpu_ctrl = syscon_regmap_lookup_by_compatible(syscon);
> >> + if (IS_ERR(sdhci_sparx5->cpu_ctrl)) {
> >> + dev_err(&pdev->dev, "No CPU syscon regmap !\n");
> >> + ret = PTR_ERR(sdhci_sparx5->cpu_ctrl);
> >> + goto err_clk;
> >> + }
> >> +
> >> + if (sdhci_sparx5->delay_clock >= 0)
> >> + sparx5_set_delay(host, sdhci_sparx5->delay_clock);
> >> +
> >> + if (!mmc_card_is_removable(host->mmc)) {
> >> + /* Do a HW reset of eMMC card */
> >> + sdhci_sparx5_reset_emmc(host);
> >> + /* Update EMMC_CTRL */
> >> + sdhci_sparx5_set_emmc(host);
> >> + /* If eMMC, disable SD and SDIO */
> >> + host->mmc->caps2 |= (MMC_CAP2_NO_SDIO|MMC_CAP2_NO_SD);
> >> + }
> >> +
> >> + ret = sdhci_add_host(host);
> >> + if (ret)
> >> + goto err_clk;
> >> +
> >> + /* Set AXI bus master to use un-cached access (for DMA) */
> >> + if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA) &&
> >> + IS_ENABLED(CONFIG_DMA_DECLARE_COHERENT))
> >> + sparx5_set_cacheable(host, ACP_CACHE_FORCE_ENA);
> >> +
> >> + pr_debug("%s: SDHC version: 0x%08x\n",
> >> + mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_VERSION));
> >> + pr_debug("%s: SDHC type: 0x%08x\n",
> >> + mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_TYPE));
> >> +
> >> + return ret;
> >> +
> >> +err_clk:
> >> + clk_disable_unprepare(pltfm_host->clk);
> >> +free_pltfm:
> >> + sdhci_pltfm_free(pdev);
> >> + return ret;
> >> +}
> >> +
> >> +static const struct of_device_id sdhci_sparx5_of_match[] = {
> >> + { .compatible = "microchip,dw-sparx5-sdhci" },
> >> + { }
> >> +};
> >> +MODULE_DEVICE_TABLE(of, sdhci_sparx5_of_match);
> >> +
> >> +static struct platform_driver sdhci_sparx5_driver = {
> >> + .driver = {
> >> + .name = "sdhci-sparx5",
> >> + .of_match_table = sdhci_sparx5_of_match,
> >> + .pm = &sdhci_pltfm_pmops,
> >> + },
> >> + .probe = sdhci_sparx5_probe,
> >> + .remove = sdhci_pltfm_unregister,
> >> +};
> >> +
> >> +module_platform_driver(sdhci_sparx5_driver);
> >> +
> >> +MODULE_DESCRIPTION("Sparx5 SDHCI OF driver");
> >> +MODULE_AUTHOR("Lars Povlsen <lars.povlsen@microchip.com>");
> >> +MODULE_LICENSE("GPL v2");
> >>
>
> --
> Lars Povlsen,
> Microchip
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v4 2/3] sdhci: sparx5: Add Sparx5 SoC eMMC driver
2020-07-24 10:47 ` Ulf Hansson
@ 2020-07-24 11:32 ` Lars Povlsen
2020-07-24 12:43 ` Ulf Hansson
0 siblings, 1 reply; 11+ messages in thread
From: Lars Povlsen @ 2020-07-24 11:32 UTC (permalink / raw)
To: Ulf Hansson
Cc: Lars Povlsen, Adrian Hunter, SoC Team,
Microchip Linux Driver Support, linux-mmc, DTML, Linux ARM,
Linux Kernel Mailing List, Alexandre Belloni
Ulf Hansson writes:
> On Wed, 22 Jul 2020 at 13:54, Lars Povlsen <lars.povlsen@microchip.com> wrote:
>>
>>
>> Adrian Hunter writes:
>>
>> > On 18/06/20 5:13 pm, Lars Povlsen wrote:
>> >> This adds the eMMC driver for the Sparx5 SoC. It is based upon the
>> >> designware IP, but requires some extra initialization and quirks.
>> >>
>> >> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
>> >
>> > Acked-by: Adrian Hunter <adrian.hunter@intel.com>
>> >
>>
>> Adrian,
>>
>> Thanks for the ack. I was expecting to see this in linux-next, anything
>> holding it back?
>>
>> pinctrl and hwmon drivers have been merged.
>>
>> Thanks,
>
> Hi Lars,
>
> Looks like you got some feedback on the DT patch (patch1/3) from Rob.
> I didn't find that you have addressed them and therefore I am holding
> back on the $subject patch as well.
>
Uffe, thank you for responding.
The automated checker complains about the inclusion of a header file
(#include <dt-bindings/clock/microchip,sparx5.h>) in the example. The
header file itself is part of the "parent" patch series sent to arm-soc,
but is needed to make the example complete.
I e-mailed Rob about how to handle this, but never got a reply.
Can you suggest how to deal with this? I have checked the schema with
dt_binding_check manually - with the header file in place.
I can of course remove the include and associated properties, but that
will make the example incomplete and irrelevant.
---Lars
> Please fix the DT patch and re-submit a new version of the series.
>
> Kind regards
> Uffe
>
>
>>
>> ---Lars
>>
>> >> ---
>> >> drivers/mmc/host/Kconfig | 13 ++
>> >> drivers/mmc/host/Makefile | 1 +
>> >> drivers/mmc/host/sdhci-of-sparx5.c | 269 +++++++++++++++++++++++++++++
>> >> 3 files changed, 283 insertions(+)
>> >> create mode 100644 drivers/mmc/host/sdhci-of-sparx5.c
>> >>
>> >> diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
>> >> index 3b706af35ec31..a3bad4b4ed7ea 100644
>> >> --- a/drivers/mmc/host/Kconfig
>> >> +++ b/drivers/mmc/host/Kconfig
>> >> @@ -213,6 +213,19 @@ config MMC_SDHCI_OF_DWCMSHC
>> >> If you have a controller with this interface, say Y or M here.
>> >> If unsure, say N.
>> >>
>> >> +config MMC_SDHCI_OF_SPARX5
>> >> + tristate "SDHCI OF support for the MCHP Sparx5 SoC"
>> >> + depends on MMC_SDHCI_PLTFM
>> >> + depends on ARCH_SPARX5
>> >> + select MMC_SDHCI_IO_ACCESSORS
>> >> + help
>> >> + This selects the Secure Digital Host Controller Interface (SDHCI)
>> >> + found in the MCHP Sparx5 SoC.
>> >> +
>> >> + If you have a Sparx5 SoC with this interface, say Y or M here.
>> >> +
>> >> + If unsure, say N.
>> >> +
>> >> config MMC_SDHCI_CADENCE
>> >> tristate "SDHCI support for the Cadence SD/SDIO/eMMC controller"
>> >> depends on MMC_SDHCI_PLTFM
>> >> diff --git a/drivers/mmc/host/Makefile b/drivers/mmc/host/Makefile
>> >> index 4d5bcb0144a0a..451c25fc2c692 100644
>> >> --- a/drivers/mmc/host/Makefile
>> >> +++ b/drivers/mmc/host/Makefile
>> >> @@ -94,6 +94,7 @@ obj-$(CONFIG_MMC_SDHCI_OF_AT91) += sdhci-of-at91.o
>> >> obj-$(CONFIG_MMC_SDHCI_OF_ESDHC) += sdhci-of-esdhc.o
>> >> obj-$(CONFIG_MMC_SDHCI_OF_HLWD) += sdhci-of-hlwd.o
>> >> obj-$(CONFIG_MMC_SDHCI_OF_DWCMSHC) += sdhci-of-dwcmshc.o
>> >> +obj-$(CONFIG_MMC_SDHCI_OF_SPARX5) += sdhci-of-sparx5.o
>> >> obj-$(CONFIG_MMC_SDHCI_BCM_KONA) += sdhci-bcm-kona.o
>> >> obj-$(CONFIG_MMC_SDHCI_IPROC) += sdhci-iproc.o
>> >> obj-$(CONFIG_MMC_SDHCI_MSM) += sdhci-msm.o
>> >> diff --git a/drivers/mmc/host/sdhci-of-sparx5.c b/drivers/mmc/host/sdhci-of-sparx5.c
>> >> new file mode 100644
>> >> index 0000000000000..2b262c12e5530
>> >> --- /dev/null
>> >> +++ b/drivers/mmc/host/sdhci-of-sparx5.c
>> >> @@ -0,0 +1,269 @@
>> >> +// SPDX-License-Identifier: GPL-2.0-or-later
>> >> +/*
>> >> + * drivers/mmc/host/sdhci-of-sparx5.c
>> >> + *
>> >> + * MCHP Sparx5 SoC Secure Digital Host Controller Interface.
>> >> + *
>> >> + * Copyright (c) 2019 Microchip Inc.
>> >> + *
>> >> + * Author: Lars Povlsen <lars.povlsen@microchip.com>
>> >> + */
>> >> +
>> >> +#include <linux/sizes.h>
>> >> +#include <linux/delay.h>
>> >> +#include <linux/module.h>
>> >> +#include <linux/regmap.h>
>> >> +#include <linux/of_device.h>
>> >> +#include <linux/mfd/syscon.h>
>> >> +#include <linux/dma-mapping.h>
>> >> +
>> >> +#include "sdhci-pltfm.h"
>> >> +
>> >> +#define CPU_REGS_GENERAL_CTRL (0x22 * 4)
>> >> +#define MSHC_DLY_CC_MASK GENMASK(16, 13)
>> >> +#define MSHC_DLY_CC_SHIFT 13
>> >> +#define MSHC_DLY_CC_MAX 15
>> >> +
>> >> +#define CPU_REGS_PROC_CTRL (0x2C * 4)
>> >> +#define ACP_CACHE_FORCE_ENA BIT(4)
>> >> +#define ACP_AWCACHE BIT(3)
>> >> +#define ACP_ARCACHE BIT(2)
>> >> +#define ACP_CACHE_MASK (ACP_CACHE_FORCE_ENA|ACP_AWCACHE|ACP_ARCACHE)
>> >> +
>> >> +#define MSHC2_VERSION 0x500 /* Off 0x140, reg 0x0 */
>> >> +#define MSHC2_TYPE 0x504 /* Off 0x140, reg 0x1 */
>> >> +#define MSHC2_EMMC_CTRL 0x52c /* Off 0x140, reg 0xB */
>> >> +#define MSHC2_EMMC_CTRL_EMMC_RST_N BIT(2)
>> >> +#define MSHC2_EMMC_CTRL_IS_EMMC BIT(0)
>> >> +
>> >> +struct sdhci_sparx5_data {
>> >> + struct sdhci_host *host;
>> >> + struct regmap *cpu_ctrl;
>> >> + int delay_clock;
>> >> +};
>> >> +
>> >> +#define BOUNDARY_OK(addr, len) \
>> >> + ((addr | (SZ_128M - 1)) == ((addr + len - 1) | (SZ_128M - 1)))
>> >> +
>> >> +/*
>> >> + * If DMA addr spans 128MB boundary, we split the DMA transfer into two
>> >> + * so that each DMA transfer doesn't exceed the boundary.
>> >> + */
>> >> +static void sdhci_sparx5_adma_write_desc(struct sdhci_host *host, void **desc,
>> >> + dma_addr_t addr, int len,
>> >> + unsigned int cmd)
>> >> +{
>> >> + int tmplen, offset;
>> >> +
>> >> + if (likely(!len || BOUNDARY_OK(addr, len))) {
>> >> + sdhci_adma_write_desc(host, desc, addr, len, cmd);
>> >> + return;
>> >> + }
>> >> +
>> >> + pr_debug("%s: write_desc: splitting dma len %d, offset 0x%0llx\n",
>> >> + mmc_hostname(host->mmc), len, addr);
>> >> +
>> >> + offset = addr & (SZ_128M - 1);
>> >> + tmplen = SZ_128M - offset;
>> >> + sdhci_adma_write_desc(host, desc, addr, tmplen, cmd);
>> >> +
>> >> + addr += tmplen;
>> >> + len -= tmplen;
>> >> + sdhci_adma_write_desc(host, desc, addr, len, cmd);
>> >> +}
>> >> +
>> >> +static void sparx5_set_cacheable(struct sdhci_host *host, u32 value)
>> >> +{
>> >> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
>> >> + struct sdhci_sparx5_data *sdhci_sparx5 = sdhci_pltfm_priv(pltfm_host);
>> >> +
>> >> + pr_debug("%s: Set Cacheable = 0x%x\n", mmc_hostname(host->mmc), value);
>> >> +
>> >> + /* Update ACP caching attributes in HW */
>> >> + regmap_update_bits(sdhci_sparx5->cpu_ctrl,
>> >> + CPU_REGS_PROC_CTRL, ACP_CACHE_MASK, value);
>> >> +}
>> >> +
>> >> +static void sparx5_set_delay(struct sdhci_host *host, u8 value)
>> >> +{
>> >> + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
>> >> + struct sdhci_sparx5_data *sdhci_sparx5 = sdhci_pltfm_priv(pltfm_host);
>> >> +
>> >> + pr_debug("%s: Set DLY_CC = %u\n", mmc_hostname(host->mmc), value);
>> >> +
>> >> + /* Update DLY_CC in HW */
>> >> + regmap_update_bits(sdhci_sparx5->cpu_ctrl,
>> >> + CPU_REGS_GENERAL_CTRL,
>> >> + MSHC_DLY_CC_MASK,
>> >> + (value << MSHC_DLY_CC_SHIFT));
>> >> +}
>> >> +
>> >> +static void sdhci_sparx5_set_emmc(struct sdhci_host *host)
>> >> +{
>> >> + if (!mmc_card_is_removable(host->mmc)) {
>> >> + u8 value;
>> >> +
>> >> + value = sdhci_readb(host, MSHC2_EMMC_CTRL);
>> >> + if (!(value & MSHC2_EMMC_CTRL_IS_EMMC)) {
>> >> + value |= MSHC2_EMMC_CTRL_IS_EMMC;
>> >> + pr_debug("%s: Set EMMC_CTRL: 0x%08x\n",
>> >> + mmc_hostname(host->mmc), value);
>> >> + sdhci_writeb(host, value, MSHC2_EMMC_CTRL);
>> >> + }
>> >> + }
>> >> +}
>> >> +
>> >> +static void sdhci_sparx5_reset_emmc(struct sdhci_host *host)
>> >> +{
>> >> + u8 value;
>> >> +
>> >> + pr_debug("%s: Toggle EMMC_CTRL.EMMC_RST_N\n", mmc_hostname(host->mmc));
>> >> + value = sdhci_readb(host, MSHC2_EMMC_CTRL) &
>> >> + ~MSHC2_EMMC_CTRL_EMMC_RST_N;
>> >> + sdhci_writeb(host, value, MSHC2_EMMC_CTRL);
>> >> + /* For eMMC, minimum is 1us but give it 10us for good measure */
>> >> + usleep_range(10, 20);
>> >> + sdhci_writeb(host, value | MSHC2_EMMC_CTRL_EMMC_RST_N,
>> >> + MSHC2_EMMC_CTRL);
>> >> + /* For eMMC, minimum is 200us but give it 300us for good measure */
>> >> + usleep_range(300, 400);
>> >> +}
>> >> +
>> >> +static void sdhci_sparx5_reset(struct sdhci_host *host, u8 mask)
>> >> +{
>> >> + pr_debug("%s: *** RESET: mask %d\n", mmc_hostname(host->mmc), mask);
>> >> +
>> >> + sdhci_reset(host, mask);
>> >> +
>> >> + /* Be sure CARD_IS_EMMC stays set */
>> >> + sdhci_sparx5_set_emmc(host);
>> >> +}
>> >> +
>> >> +static const struct sdhci_ops sdhci_sparx5_ops = {
>> >> + .set_clock = sdhci_set_clock,
>> >> + .set_bus_width = sdhci_set_bus_width,
>> >> + .set_uhs_signaling = sdhci_set_uhs_signaling,
>> >> + .get_max_clock = sdhci_pltfm_clk_get_max_clock,
>> >> + .reset = sdhci_sparx5_reset,
>> >> + .adma_write_desc = sdhci_sparx5_adma_write_desc,
>> >> +};
>> >> +
>> >> +static const struct sdhci_pltfm_data sdhci_sparx5_pdata = {
>> >> + .quirks = 0,
>> >> + .quirks2 = SDHCI_QUIRK2_HOST_NO_CMD23 | /* Controller issue */
>> >> + SDHCI_QUIRK2_NO_1_8_V, /* No sdr104, ddr50, etc */
>> >> + .ops = &sdhci_sparx5_ops,
>> >> +};
>> >> +
>> >> +int sdhci_sparx5_probe(struct platform_device *pdev)
>> >> +{
>> >> + int ret;
>> >> + const char *syscon = "microchip,sparx5-cpu-syscon";
>> >> + struct sdhci_host *host;
>> >> + struct sdhci_pltfm_host *pltfm_host;
>> >> + struct sdhci_sparx5_data *sdhci_sparx5;
>> >> + struct device_node *np = pdev->dev.of_node;
>> >> + u32 value;
>> >> + u32 extra;
>> >> +
>> >> + host = sdhci_pltfm_init(pdev, &sdhci_sparx5_pdata,
>> >> + sizeof(*sdhci_sparx5));
>> >> +
>> >> + if (IS_ERR(host))
>> >> + return PTR_ERR(host);
>> >> +
>> >> + /*
>> >> + * extra adma table cnt for cross 128M boundary handling.
>> >> + */
>> >> + extra = DIV_ROUND_UP_ULL(dma_get_required_mask(&pdev->dev), SZ_128M);
>> >> + if (extra > SDHCI_MAX_SEGS)
>> >> + extra = SDHCI_MAX_SEGS;
>> >> + host->adma_table_cnt += extra;
>> >> +
>> >> + pltfm_host = sdhci_priv(host);
>> >> + sdhci_sparx5 = sdhci_pltfm_priv(pltfm_host);
>> >> + sdhci_sparx5->host = host;
>> >> +
>> >> + pltfm_host->clk = devm_clk_get(&pdev->dev, "core");
>> >> + if (IS_ERR(pltfm_host->clk)) {
>> >> + ret = PTR_ERR(pltfm_host->clk);
>> >> + dev_err(&pdev->dev, "failed to get core clk: %d\n", ret);
>> >> + goto free_pltfm;
>> >> + }
>> >> + ret = clk_prepare_enable(pltfm_host->clk);
>> >> + if (ret)
>> >> + goto free_pltfm;
>> >> +
>> >> + if (!of_property_read_u32(np, "microchip,clock-delay", &value) &&
>> >> + (value > 0 && value <= MSHC_DLY_CC_MAX))
>> >> + sdhci_sparx5->delay_clock = value;
>> >> +
>> >> + sdhci_get_of_property(pdev);
>> >> +
>> >> + ret = mmc_of_parse(host->mmc);
>> >> + if (ret)
>> >> + goto err_clk;
>> >> +
>> >> + sdhci_sparx5->cpu_ctrl = syscon_regmap_lookup_by_compatible(syscon);
>> >> + if (IS_ERR(sdhci_sparx5->cpu_ctrl)) {
>> >> + dev_err(&pdev->dev, "No CPU syscon regmap !\n");
>> >> + ret = PTR_ERR(sdhci_sparx5->cpu_ctrl);
>> >> + goto err_clk;
>> >> + }
>> >> +
>> >> + if (sdhci_sparx5->delay_clock >= 0)
>> >> + sparx5_set_delay(host, sdhci_sparx5->delay_clock);
>> >> +
>> >> + if (!mmc_card_is_removable(host->mmc)) {
>> >> + /* Do a HW reset of eMMC card */
>> >> + sdhci_sparx5_reset_emmc(host);
>> >> + /* Update EMMC_CTRL */
>> >> + sdhci_sparx5_set_emmc(host);
>> >> + /* If eMMC, disable SD and SDIO */
>> >> + host->mmc->caps2 |= (MMC_CAP2_NO_SDIO|MMC_CAP2_NO_SD);
>> >> + }
>> >> +
>> >> + ret = sdhci_add_host(host);
>> >> + if (ret)
>> >> + goto err_clk;
>> >> +
>> >> + /* Set AXI bus master to use un-cached access (for DMA) */
>> >> + if (host->flags & (SDHCI_USE_SDMA | SDHCI_USE_ADMA) &&
>> >> + IS_ENABLED(CONFIG_DMA_DECLARE_COHERENT))
>> >> + sparx5_set_cacheable(host, ACP_CACHE_FORCE_ENA);
>> >> +
>> >> + pr_debug("%s: SDHC version: 0x%08x\n",
>> >> + mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_VERSION));
>> >> + pr_debug("%s: SDHC type: 0x%08x\n",
>> >> + mmc_hostname(host->mmc), sdhci_readl(host, MSHC2_TYPE));
>> >> +
>> >> + return ret;
>> >> +
>> >> +err_clk:
>> >> + clk_disable_unprepare(pltfm_host->clk);
>> >> +free_pltfm:
>> >> + sdhci_pltfm_free(pdev);
>> >> + return ret;
>> >> +}
>> >> +
>> >> +static const struct of_device_id sdhci_sparx5_of_match[] = {
>> >> + { .compatible = "microchip,dw-sparx5-sdhci" },
>> >> + { }
>> >> +};
>> >> +MODULE_DEVICE_TABLE(of, sdhci_sparx5_of_match);
>> >> +
>> >> +static struct platform_driver sdhci_sparx5_driver = {
>> >> + .driver = {
>> >> + .name = "sdhci-sparx5",
>> >> + .of_match_table = sdhci_sparx5_of_match,
>> >> + .pm = &sdhci_pltfm_pmops,
>> >> + },
>> >> + .probe = sdhci_sparx5_probe,
>> >> + .remove = sdhci_pltfm_unregister,
>> >> +};
>> >> +
>> >> +module_platform_driver(sdhci_sparx5_driver);
>> >> +
>> >> +MODULE_DESCRIPTION("Sparx5 SDHCI OF driver");
>> >> +MODULE_AUTHOR("Lars Povlsen <lars.povlsen@microchip.com>");
>> >> +MODULE_LICENSE("GPL v2");
>> >>
>>
>> --
>> Lars Povlsen,
>> Microchip
--
Lars Povlsen,
Microchip
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v4 2/3] sdhci: sparx5: Add Sparx5 SoC eMMC driver
2020-07-24 11:32 ` Lars Povlsen
@ 2020-07-24 12:43 ` Ulf Hansson
0 siblings, 0 replies; 11+ messages in thread
From: Ulf Hansson @ 2020-07-24 12:43 UTC (permalink / raw)
To: Lars Povlsen
Cc: Adrian Hunter, SoC Team, Microchip Linux Driver Support,
linux-mmc, DTML, Linux ARM, Linux Kernel Mailing List,
Alexandre Belloni
On Fri, 24 Jul 2020 at 13:32, Lars Povlsen <lars.povlsen@microchip.com> wrote:
>
>
> Ulf Hansson writes:
>
> > On Wed, 22 Jul 2020 at 13:54, Lars Povlsen <lars.povlsen@microchip.com> wrote:
> >>
> >>
> >> Adrian Hunter writes:
> >>
> >> > On 18/06/20 5:13 pm, Lars Povlsen wrote:
> >> >> This adds the eMMC driver for the Sparx5 SoC. It is based upon the
> >> >> designware IP, but requires some extra initialization and quirks.
> >> >>
> >> >> Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com>
> >> >
> >> > Acked-by: Adrian Hunter <adrian.hunter@intel.com>
> >> >
> >>
> >> Adrian,
> >>
> >> Thanks for the ack. I was expecting to see this in linux-next, anything
> >> holding it back?
> >>
> >> pinctrl and hwmon drivers have been merged.
> >>
> >> Thanks,
> >
> > Hi Lars,
> >
> > Looks like you got some feedback on the DT patch (patch1/3) from Rob.
> > I didn't find that you have addressed them and therefore I am holding
> > back on the $subject patch as well.
> >
>
> Uffe, thank you for responding.
>
> The automated checker complains about the inclusion of a header file
> (#include <dt-bindings/clock/microchip,sparx5.h>) in the example. The
> header file itself is part of the "parent" patch series sent to arm-soc,
> but is needed to make the example complete.
>
> I e-mailed Rob about how to handle this, but never got a reply.
>
> Can you suggest how to deal with this? I have checked the schema with
> dt_binding_check manually - with the header file in place.
I see, thanks for clarifying.
When this kind of dependy happens, we have a couple of options.
1. Wait for a new rc to have the dependent changes included.
2. Share the changes between maintainers's git trees, through
immutable branches.
Looks like 1) would be easiest here. So, I suggest you re-post the
series when v5.9-rc1 is out.
>
> I can of course remove the include and associated properties, but that
> will make the example incomplete and irrelevant.
No, that doesn't sound right.
[...]
Kind regards
Uffe
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v4 0/3] mmc: Adding support for Microchip Sparx5 SoC
@ 2020-08-24 15:10 Lars Povlsen
0 siblings, 0 replies; 11+ messages in thread
From: Lars Povlsen @ 2020-08-24 15:10 UTC (permalink / raw)
To: Ulf Hansson, Adrian Hunter, SoC Team
Cc: Lars Povlsen, Microchip Linux Driver Support, linux-mmc,
devicetree, linux-arm-kernel, linux-kernel, Alexandre Belloni
(This is a resend of an identical patch set, sent at a time where
Sparx5 support was not integrated yet. With the Sparx5 clock driver
and associated header now in place in the v5.9rc series, the driver is
now resubmitted for inclusion).
The patch adds eMMC support for Sparx5, by adding a driver for the SoC
SDHCI controller, DT configuration and DT binding documentation.
Changes in v4:
- Disable clock if sdhci_add_host() fails
- Remove dev_err if sdhci_add_host() fails
Changes in v3:
- Add dt-bindings for property "microchip,clock-delay"
- Enforce "microchip,clock-delay" valid range in driver
- Removed a noisy pr_debug() in sdhci_sparx5_adma_write_desc()
Changes in v2:
- Changes in driver as per review comments
- Drop debug code
- Drop sysfs code
- use usleep_range()
- use mmc_hostname() in pr_debug()
- Remove deactivated code
- Minor cosmetics
Lars Povlsen (3):
dt-bindings: mmc: Add Sparx5 SDHCI controller bindings
sdhci: sparx5: Add Sparx5 SoC eMMC driver
arm64: dts: sparx5: Add Sparx5 eMMC support
.../mmc/microchip,dw-sparx5-sdhci.yaml | 65 +++++
arch/arm64/boot/dts/microchip/sparx5.dtsi | 24 ++
.../boot/dts/microchip/sparx5_pcb125.dts | 23 ++
.../boot/dts/microchip/sparx5_pcb134_emmc.dts | 23 ++
.../boot/dts/microchip/sparx5_pcb135_emmc.dts | 23 ++
drivers/mmc/host/Kconfig | 13 +
drivers/mmc/host/Makefile | 1 +
drivers/mmc/host/sdhci-of-sparx5.c | 269 ++++++++++++++++++
8 files changed, 441 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mmc/microchip,dw-sparx5-sdhci.yaml
create mode 100644 drivers/mmc/host/sdhci-of-sparx5.c
--
2.27.0
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2020-08-24 15:11 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2020-06-18 14:13 [PATCH v4 0/3] mmc: Adding support for Microchip Sparx5 SoC Lars Povlsen
2020-06-18 14:13 ` [PATCH v4 1/3] dt-bindings: mmc: Add Sparx5 SDHCI controller bindings Lars Povlsen
2020-06-29 21:54 ` Rob Herring
2020-06-18 14:13 ` [PATCH v4 2/3] sdhci: sparx5: Add Sparx5 SoC eMMC driver Lars Povlsen
2020-06-18 14:43 ` Adrian Hunter
2020-07-22 11:54 ` Lars Povlsen
2020-07-24 10:47 ` Ulf Hansson
2020-07-24 11:32 ` Lars Povlsen
2020-07-24 12:43 ` Ulf Hansson
2020-06-18 14:13 ` [PATCH v4 3/3] arm64: dts: sparx5: Add Sparx5 eMMC support Lars Povlsen
2020-08-24 15:10 [PATCH v4 0/3] mmc: Adding support for Microchip Sparx5 SoC Lars Povlsen
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