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From: Joerg Roedel <joro@8bytes.org>
To: x86@kernel.org
Cc: Joerg Roedel <joro@8bytes.org>, Joerg Roedel <jroedel@suse.de>,
	hpa@zytor.com, Andy Lutomirski <luto@kernel.org>,
	Dave Hansen <dave.hansen@linux.intel.com>,
	Peter Zijlstra <peterz@infradead.org>,
	Jiri Slaby <jslaby@suse.cz>,
	Dan Williams <dan.j.williams@intel.com>,
	Tom Lendacky <thomas.lendacky@amd.com>,
	Juergen Gross <jgross@suse.com>,
	Kees Cook <keescook@chromium.org>,
	David Rientjes <rientjes@google.com>,
	Cfir Cohen <cfir@google.com>, Erdem Aktas <erdemaktas@google.com>,
	Masami Hiramatsu <mhiramat@kernel.org>,
	Mike Stunes <mstunes@vmware.com>,
	Sean Christopherson <sean.j.christopherson@intel.com>,
	Martin Radev <martin.b.radev@gmail.com>,
	linux-kernel@vger.kernel.org, kvm@vger.kernel.org,
	virtualization@lists.linux-foundation.org
Subject: [PATCH v6 13/76] x86/boot/compressed/64: Add IDT Infrastructure
Date: Mon, 24 Aug 2020 10:54:08 +0200	[thread overview]
Message-ID: <20200824085511.7553-14-joro@8bytes.org> (raw)
In-Reply-To: <20200824085511.7553-1-joro@8bytes.org>

From: Joerg Roedel <jroedel@suse.de>

Add code needed to setup an IDT in the early pre-decompression
boot-code. The IDT is loaded first in startup_64, which is after
EfiExitBootServices() has been called, and later reloaded when the
kernel image has been relocated to the end of the decompression area.

This allows to setup different IDT handlers before and after the
relocation.

Signed-off-by: Joerg Roedel <jroedel@suse.de>
Link: https://lore.kernel.org/r/20200724160336.5435-13-joro@8bytes.org
---
 arch/x86/boot/compressed/Makefile          |  1 +
 arch/x86/boot/compressed/head_64.S         | 25 +++++++-
 arch/x86/boot/compressed/idt_64.c          | 44 ++++++++++++++
 arch/x86/boot/compressed/idt_handlers_64.S | 70 ++++++++++++++++++++++
 arch/x86/boot/compressed/misc.h            |  5 ++
 arch/x86/include/asm/desc_defs.h           |  3 +
 6 files changed, 147 insertions(+), 1 deletion(-)
 create mode 100644 arch/x86/boot/compressed/idt_64.c
 create mode 100644 arch/x86/boot/compressed/idt_handlers_64.S

diff --git a/arch/x86/boot/compressed/Makefile b/arch/x86/boot/compressed/Makefile
index 0acdaa8a7dab..ce85b24898b8 100644
--- a/arch/x86/boot/compressed/Makefile
+++ b/arch/x86/boot/compressed/Makefile
@@ -78,6 +78,7 @@ vmlinux-objs-$(CONFIG_EARLY_PRINTK) += $(obj)/early_serial_console.o
 vmlinux-objs-$(CONFIG_RANDOMIZE_BASE) += $(obj)/kaslr.o
 ifdef CONFIG_X86_64
 	vmlinux-objs-$(CONFIG_RANDOMIZE_BASE) += $(obj)/kaslr_64.o
+	vmlinux-objs-y += $(obj)/idt_64.o $(obj)/idt_handlers_64.o
 	vmlinux-objs-y += $(obj)/mem_encrypt.o
 	vmlinux-objs-y += $(obj)/pgtable_64.o
 endif
diff --git a/arch/x86/boot/compressed/head_64.S b/arch/x86/boot/compressed/head_64.S
index 9e46729cf162..260c7940f960 100644
--- a/arch/x86/boot/compressed/head_64.S
+++ b/arch/x86/boot/compressed/head_64.S
@@ -33,6 +33,7 @@
 #include <asm/processor-flags.h>
 #include <asm/asm-offsets.h>
 #include <asm/bootparam.h>
+#include <asm/desc_defs.h>
 #include "pgtable.h"
 
 /*
@@ -415,6 +416,10 @@ SYM_CODE_START(startup_64)
 
 .Lon_kernel_cs:
 
+	pushq	%rsi
+	call	load_stage1_idt
+	popq	%rsi
+
 	/*
 	 * paging_prepare() sets up the trampoline and checks if we need to
 	 * enable 5-level paging.
@@ -527,6 +532,13 @@ SYM_FUNC_START_LOCAL_NOALIGN(.Lrelocated)
 	shrq	$3, %rcx
 	rep	stosq
 
+/*
+ * Load stage2 IDT
+ */
+	pushq	%rsi
+	call	load_stage2_idt
+	popq	%rsi
+
 /*
  * Do the extraction, and jump to the new kernel..
  */
@@ -659,10 +671,21 @@ SYM_DATA_START_LOCAL(gdt)
 	.quad   0x0000000000000000	/* TS continued */
 SYM_DATA_END_LABEL(gdt, SYM_L_LOCAL, gdt_end)
 
+SYM_DATA_START(boot_idt_desc)
+	.word	boot_idt_end - boot_idt
+	.quad	0
+SYM_DATA_END(boot_idt_desc)
+	.balign 8
+SYM_DATA_START(boot_idt)
+	.rept	BOOT_IDT_ENTRIES
+	.quad	0
+	.quad	0
+	.endr
+SYM_DATA_END_LABEL(boot_idt, SYM_L_GLOBAL, boot_idt_end)
+
 #ifdef CONFIG_EFI_STUB
 SYM_DATA(image_offset, .long 0)
 #endif
-
 #ifdef CONFIG_EFI_MIXED
 SYM_DATA_LOCAL(efi32_boot_args, .long 0, 0, 0)
 SYM_DATA(efi_is64, .byte 1)
diff --git a/arch/x86/boot/compressed/idt_64.c b/arch/x86/boot/compressed/idt_64.c
new file mode 100644
index 000000000000..082cd6bca033
--- /dev/null
+++ b/arch/x86/boot/compressed/idt_64.c
@@ -0,0 +1,44 @@
+// SPDX-License-Identifier: GPL-2.0-only
+#include <asm/trap_pf.h>
+#include <asm/segment.h>
+#include <asm/trapnr.h>
+#include "misc.h"
+
+static void set_idt_entry(int vector, void (*handler)(void))
+{
+	unsigned long address = (unsigned long)handler;
+	gate_desc entry;
+
+	memset(&entry, 0, sizeof(entry));
+
+	entry.offset_low    = (u16)(address & 0xffff);
+	entry.segment       = __KERNEL_CS;
+	entry.bits.type     = GATE_TRAP;
+	entry.bits.p        = 1;
+	entry.offset_middle = (u16)((address >> 16) & 0xffff);
+	entry.offset_high   = (u32)(address >> 32);
+
+	memcpy(&boot_idt[vector], &entry, sizeof(entry));
+}
+
+/* Have this here so we don't need to include <asm/desc.h> */
+static void load_boot_idt(const struct desc_ptr *dtr)
+{
+	asm volatile("lidt %0"::"m" (*dtr));
+}
+
+/* Setup IDT before kernel jumping to  .Lrelocated */
+void load_stage1_idt(void)
+{
+	boot_idt_desc.address = (unsigned long)boot_idt;
+
+	load_boot_idt(&boot_idt_desc);
+}
+
+/* Setup IDT after kernel jumping to  .Lrelocated */
+void load_stage2_idt(void)
+{
+	boot_idt_desc.address = (unsigned long)boot_idt;
+
+	load_boot_idt(&boot_idt_desc);
+}
diff --git a/arch/x86/boot/compressed/idt_handlers_64.S b/arch/x86/boot/compressed/idt_handlers_64.S
new file mode 100644
index 000000000000..36dee2f40a8b
--- /dev/null
+++ b/arch/x86/boot/compressed/idt_handlers_64.S
@@ -0,0 +1,70 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Early IDT handler entry points
+ *
+ * Copyright (C) 2019 SUSE
+ *
+ * Author: Joerg Roedel <jroedel@suse.de>
+ */
+
+#include <asm/segment.h>
+
+/* For ORIG_RAX */
+#include "../../entry/calling.h"
+
+.macro EXCEPTION_HANDLER name function error_code=0
+SYM_FUNC_START(\name)
+
+	/* Build pt_regs */
+	.if \error_code == 0
+	pushq   $0
+	.endif
+
+	pushq   %rdi
+	pushq   %rsi
+	pushq   %rdx
+	pushq   %rcx
+	pushq   %rax
+	pushq   %r8
+	pushq   %r9
+	pushq   %r10
+	pushq   %r11
+	pushq   %rbx
+	pushq   %rbp
+	pushq   %r12
+	pushq   %r13
+	pushq   %r14
+	pushq   %r15
+
+	/* Call handler with pt_regs */
+	movq    %rsp, %rdi
+	/* Error code is second parameter */
+	movq	ORIG_RAX(%rsp), %rsi
+	call    \function
+
+	/* Restore regs */
+	popq    %r15
+	popq    %r14
+	popq    %r13
+	popq    %r12
+	popq    %rbp
+	popq    %rbx
+	popq    %r11
+	popq    %r10
+	popq    %r9
+	popq    %r8
+	popq    %rax
+	popq    %rcx
+	popq    %rdx
+	popq    %rsi
+	popq    %rdi
+
+	/* Remove error code and return */
+	addq    $8, %rsp
+
+	iretq
+SYM_FUNC_END(\name)
+	.endm
+
+	.text
+	.code64
diff --git a/arch/x86/boot/compressed/misc.h b/arch/x86/boot/compressed/misc.h
index 3efce27ba35c..8feb5f6f329e 100644
--- a/arch/x86/boot/compressed/misc.h
+++ b/arch/x86/boot/compressed/misc.h
@@ -23,6 +23,7 @@
 #include <asm/page.h>
 #include <asm/boot.h>
 #include <asm/bootparam.h>
+#include <asm/desc_defs.h>
 
 #define BOOT_CTYPE_H
 #include <linux/acpi.h>
@@ -133,4 +134,8 @@ int count_immovable_mem_regions(void);
 static inline int count_immovable_mem_regions(void) { return 0; }
 #endif
 
+/* idt_64.c */
+extern gate_desc boot_idt[BOOT_IDT_ENTRIES];
+extern struct desc_ptr boot_idt_desc;
+
 #endif /* BOOT_COMPRESSED_MISC_H */
diff --git a/arch/x86/include/asm/desc_defs.h b/arch/x86/include/asm/desc_defs.h
index a91f3b6e4f2a..5621fb3f2d1a 100644
--- a/arch/x86/include/asm/desc_defs.h
+++ b/arch/x86/include/asm/desc_defs.h
@@ -109,6 +109,9 @@ struct desc_ptr {
 
 #endif /* !__ASSEMBLY__ */
 
+/* Boot IDT definitions */
+#define	BOOT_IDT_ENTRIES	32
+
 /* Access rights as returned by LAR */
 #define AR_TYPE_RODATA		(0 * (1 << 9))
 #define AR_TYPE_RWDATA		(1 * (1 << 9))
-- 
2.28.0


  parent reply	other threads:[~2020-08-24  8:56 UTC|newest]

Thread overview: 116+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-08-24  8:53 [PATCH v6 00/76] x86: SEV-ES Guest Support Joerg Roedel
2020-08-24  8:53 ` [PATCH v6 01/76] KVM: SVM: nested: Don't allocate VMCB structures on stack Joerg Roedel
2020-08-24  8:53 ` [PATCH v6 02/76] KVM: SVM: Add GHCB definitions Joerg Roedel
2020-08-24 10:44   ` Borislav Petkov
2020-08-25  9:22     ` Joerg Roedel
2020-08-25 11:04       ` Borislav Petkov
2020-08-27 16:01         ` Arvind Sankar
2020-08-28 11:54           ` Joerg Roedel
2020-08-24  8:53 ` [PATCH v6 03/76] KVM: SVM: Add GHCB Accessor functions Joerg Roedel
2020-08-24  8:53 ` [PATCH v6 04/76] KVM: SVM: Use __packed shorthand Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 05/76] x86/cpufeatures: Add SEV-ES CPU feature Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 06/76] x86/traps: Move pf error codes to <asm/trap_pf.h> Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 07/76] x86/insn: Make inat-tables.c suitable for pre-decompression code Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 08/76] x86/umip: Factor out instruction fetch Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 09/76] x86/umip: Factor out instruction decoding Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 10/76] x86/insn: Add insn_get_modrm_reg_off() Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 11/76] x86/insn: Add insn_has_rep_prefix() helper Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 12/76] x86/boot/compressed/64: Disable red-zone usage Joerg Roedel
2020-08-24  8:54 ` Joerg Roedel [this message]
2020-08-27 15:26   ` [PATCH v6 13/76] x86/boot/compressed/64: Add IDT Infrastructure Arvind Sankar
2020-08-28 12:12     ` Joerg Roedel
2020-08-28 15:09       ` Arvind Sankar
2020-08-24  8:54 ` [PATCH v6 14/76] x86/boot/compressed/64: Rename kaslr_64.c to ident_map_64.c Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 15/76] x86/boot/compressed/64: Add page-fault handler Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 16/76] x86/boot/compressed/64: Always switch to own page-table Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 17/76] x86/boot/compressed/64: Don't pre-map memory in KASLR code Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 18/76] x86/boot/compressed/64: Change add_identity_map() to take start and end Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 19/76] x86/boot/compressed/64: Add stage1 #VC handler Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 20/76] x86/boot/compressed/64: Call set_sev_encryption_mask earlier Joerg Roedel
2020-08-27  9:36   ` Borislav Petkov
2020-08-24  8:54 ` [PATCH v6 21/76] x86/boot/compressed/64: Check return value of kernel_ident_mapping_init() Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 22/76] x86/boot/compressed/64: Add set_page_en/decrypted() helpers Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 23/76] x86/boot/compressed/64: Setup GHCB Based VC Exception handler Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 24/76] x86/boot/compressed/64: Unmap GHCB page before booting the kernel Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 25/76] x86/sev-es: Add support for handling IOIO exceptions Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 26/76] x86/fpu: Move xgetbv()/xsetbv() into separate header Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 27/76] x86/sev-es: Add CPUID handling to #VC handler Joerg Roedel
2020-08-27 22:48   ` Arvind Sankar
2020-08-28 12:33     ` Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 28/76] x86/idt: Move IDT to data segment Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 29/76] x86/idt: Split idt_data setup out of set_intr_gate() Joerg Roedel
2020-08-28 15:16   ` Borislav Petkov
2020-08-24  8:54 ` [PATCH v6 30/76] x86/head/64: Install startup GDT Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 31/76] x86/head/64: Setup MSR_GS_BASE before calling into C code Joerg Roedel
2020-08-28 18:13   ` Borislav Petkov
2020-09-01 12:09     ` Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 32/76] x86/head/64: Load GDT after switch to virtual addresses Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 33/76] x86/head/64: Load segment registers earlier Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 34/76] x86/head/64: Switch to initial stack earlier Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 35/76] x86/head/64: Make fixup_pointer() static inline Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 36/76] x86/head/64: Load IDT earlier Joerg Roedel
2020-08-29 10:24   ` Borislav Petkov
2020-09-01 12:13     ` Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 37/76] x86/head/64: Move early exception dispatch to C code Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 38/76] x86/head/64: Set CR4.FSGSBASE early Joerg Roedel
2020-08-29 15:55   ` Borislav Petkov
2020-08-31  8:58     ` Joerg Roedel
2020-08-31  9:26       ` Borislav Petkov
2020-08-24  8:54 ` [PATCH v6 39/76] x86/sev-es: Add SEV-ES Feature Detection Joerg Roedel
2020-08-29 16:25   ` Borislav Petkov
2020-08-24  8:54 ` [PATCH v6 40/76] x86/sev-es: Print SEV-ES info into kernel log Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 41/76] x86/sev-es: Compile early handler code into kernel image Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 42/76] x86/sev-es: Setup early #VC handler Joerg Roedel
2020-08-31  9:45   ` Borislav Petkov
2020-09-01 12:59     ` Joerg Roedel
2020-09-01 13:35       ` Borislav Petkov
2021-09-04  9:39   ` Lai Jiangshan
2021-09-06  5:07     ` Juergen Gross
2020-08-24  8:54 ` [PATCH v6 43/76] x86/sev-es: Setup GHCB based boot " Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 44/76] x86/sev-es: Setup per-cpu GHCBs for the runtime handler Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 45/76] x86/sev-es: Allocate and Map IST stack for #VC handler Joerg Roedel
2020-08-31 10:27   ` Borislav Petkov
2020-08-24  8:54 ` [PATCH v6 46/76] x86/sev-es: Adjust #VC IST Stack on entering NMI handler Joerg Roedel
2020-08-31 11:05   ` Borislav Petkov
2020-08-24  8:54 ` [PATCH v6 47/76] x86/dumpstack/64: Add noinstr version of get_stack_info() Joerg Roedel
2020-08-31 11:11   ` Borislav Petkov
2020-08-24  8:54 ` [PATCH v6 48/76] x86/entry/64: Add entry code for #VC handler Joerg Roedel
2020-08-31 11:30   ` Borislav Petkov
2020-09-01 13:29     ` Joerg Roedel
2020-08-31 17:30   ` Borislav Petkov
2020-08-24  8:54 ` [PATCH v6 49/76] x86/sev-es: Add Runtime #VC Exception Handler Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 50/76] x86/sev-es: Wire up existing #VC exit-code handlers Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 51/76] x86/sev-es: Handle instruction fetches from user-space Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 52/76] x86/sev-es: Handle MMIO events Joerg Roedel
2020-08-31 15:47   ` Borislav Petkov
2020-08-24  8:54 ` [PATCH v6 53/76] x86/sev-es: Handle MMIO String Instructions Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 54/76] x86/sev-es: Handle MSR events Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 55/76] x86/sev-es: Handle DR7 read/write events Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 56/76] x86/sev-es: Handle WBINVD Events Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 57/76] x86/sev-es: Handle RDTSC(P) Events Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 58/76] x86/sev-es: Handle RDPMC Events Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 59/76] x86/sev-es: Handle INVD Events Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 60/76] x86/sev-es: Handle MONITOR/MONITORX Events Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 61/76] x86/sev-es: Handle MWAIT/MWAITX Events Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 62/76] x86/sev-es: Handle VMMCALL Events Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 63/76] x86/sev-es: Handle #AC Events Joerg Roedel
2020-08-24  8:54 ` [PATCH v6 64/76] x86/sev-es: Handle #DB Events Joerg Roedel
2020-08-31 16:19   ` Borislav Petkov
2020-08-24  8:55 ` [PATCH v6 65/76] x86/paravirt: Allow hypervisor specific VMMCALL handling under SEV-ES Joerg Roedel
2020-08-24  8:55 ` [PATCH v6 66/76] x86/kvm: Add KVM " Joerg Roedel
2020-08-24  8:55 ` [PATCH v6 67/76] x86/vmware: Add VMware specific handling for VMMCALL " Joerg Roedel
2020-08-24  8:55 ` [PATCH v6 68/76] x86/realmode: Add SEV-ES specific trampoline entry point Joerg Roedel
2020-08-24  8:55 ` [PATCH v6 69/76] x86/realmode: Setup AP jump table Joerg Roedel
2020-08-31 17:09   ` Borislav Petkov
2020-09-01 13:55     ` Joerg Roedel
2020-08-24  8:55 ` [PATCH v6 70/76] x86/smpboot: Setup TSS for starting AP Joerg Roedel
2020-08-31 17:25   ` Borislav Petkov
2020-08-24  8:55 ` [PATCH v6 71/76] x86/head/64: Don't call verify_cpu() on starting APs Joerg Roedel
2020-08-24  8:55 ` [PATCH v6 72/76] x86/head/64: Rename start_cpu0 Joerg Roedel
2020-08-31 17:29   ` Borislav Petkov
2020-08-24  8:55 ` [PATCH v6 73/76] x86/sev-es: Support CPU offline/online Joerg Roedel
2020-08-24  8:55 ` [PATCH v6 74/76] x86/sev-es: Handle NMI State Joerg Roedel
2020-08-24  8:55 ` [PATCH v6 75/76] x86/efi: Add GHCB mappings when SEV-ES is active Joerg Roedel
2020-08-24  8:55 ` [PATCH v6 76/76] x86/sev-es: Check required CPU features for SEV-ES Joerg Roedel
2020-08-25  0:21 ` [PATCH v6 00/76] x86: SEV-ES Guest Support Mike Stunes
2020-08-25  6:24   ` Joerg Roedel

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